Static Timing Analysis

Project : CharLCDmp_Demo
Build Time : 03/20/13 20:48:40
Device : CY8C3866AXA-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LCD:Cntl_Port:Sync:ctrl_reg\/control_1 D5(0)_PAD 25.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_155 \LCD:Cntl_Port:Sync:ctrl_reg\/control_1 D5(0)/pin_input 6.660
iocell P1[5] 1 D5(0) D5(0)/pin_input D5(0)/pad_out 16.200
Route 1 D5(0)_PAD D5(0)/pad_out D5(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_4 E(0)_PAD 25.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_140 \LCD:Cntl_Port:Sync:ctrl_reg\/control_4 E(0)/pin_input 6.518
iocell P2[5] 1 E(0) E(0)/pin_input E(0)/pad_out 16.200
Route 1 E(0)_PAD E(0)/pad_out E(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_5 RS(0)_PAD 25.294
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_139 \LCD:Cntl_Port:Sync:ctrl_reg\/control_5 RS(0)/pin_input 6.514
iocell P2[4] 1 RS(0) RS(0)/pin_input RS(0)/pad_out 16.200
Route 1 RS(0)_PAD RS(0)/pad_out RS(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_3 D7(0)_PAD 24.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_157 \LCD:Cntl_Port:Sync:ctrl_reg\/control_3 D7(0)/pin_input 5.889
iocell P1[7] 1 D7(0) D7(0)/pin_input D7(0)/pad_out 16.200
Route 1 D7(0)_PAD D7(0)/pad_out D7(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_0 D4(0)_PAD 24.627
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_141 \LCD:Cntl_Port:Sync:ctrl_reg\/control_0 D4(0)/pin_input 5.847
iocell P1[4] 1 D4(0) D4(0)/pin_input D4(0)/pad_out 16.200
Route 1 D4(0)_PAD D4(0)/pad_out D4(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_2 D6(0)_PAD 24.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_156 \LCD:Cntl_Port:Sync:ctrl_reg\/control_2 D6(0)/pin_input 5.767
iocell P1[6] 1 D6(0) D6(0)/pin_input D6(0)/pad_out 16.200
Route 1 D6(0)_PAD D6(0)/pad_out D6(0)_PAD 0.000
Clock Clock path delay 0.000