\LCD:Cntl_Port:Sync:ctrl_reg\/control_0 |
Pin_DB4(0)_PAD |
23.188 |
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,0) |
1 |
\LCD:Cntl_Port:Sync:ctrl_reg\ |
\LCD:Cntl_Port:Sync:ctrl_reg\/busclk |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_0 |
2.050 |
Route |
|
1 |
Net_20 |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_0 |
Pin_DB4(0)/pin_input |
6.151 |
iocell5 |
P3[4] |
1 |
Pin_DB4(0) |
Pin_DB4(0)/pin_input |
Pin_DB4(0)/pad_out |
14.987 |
Route |
|
1 |
Pin_DB4(0)_PAD |
Pin_DB4(0)/pad_out |
Pin_DB4(0)_PAD |
0.000 |
Clock |
|
|
|
|
Clock path delay |
0.000 |
|
\LCD:Cntl_Port:Sync:ctrl_reg\/control_2 |
Pin_DB6(0)_PAD |
22.831 |
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,0) |
1 |
\LCD:Cntl_Port:Sync:ctrl_reg\ |
\LCD:Cntl_Port:Sync:ctrl_reg\/busclk |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_2 |
2.050 |
Route |
|
1 |
Net_22 |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_2 |
Pin_DB6(0)/pin_input |
6.190 |
iocell7 |
P3[6] |
1 |
Pin_DB6(0) |
Pin_DB6(0)/pin_input |
Pin_DB6(0)/pad_out |
14.591 |
Route |
|
1 |
Pin_DB6(0)_PAD |
Pin_DB6(0)/pad_out |
Pin_DB6(0)_PAD |
0.000 |
Clock |
|
|
|
|
Clock path delay |
0.000 |
|
\LCD:Cntl_Port:Sync:ctrl_reg\/control_1 |
Pin_DB5(0)_PAD |
22.692 |
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,0) |
1 |
\LCD:Cntl_Port:Sync:ctrl_reg\ |
\LCD:Cntl_Port:Sync:ctrl_reg\/busclk |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_1 |
2.050 |
Route |
|
1 |
Net_21 |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_1 |
Pin_DB5(0)/pin_input |
5.304 |
iocell6 |
P3[5] |
1 |
Pin_DB5(0) |
Pin_DB5(0)/pin_input |
Pin_DB5(0)/pad_out |
15.338 |
Route |
|
1 |
Pin_DB5(0)_PAD |
Pin_DB5(0)/pad_out |
Pin_DB5(0)_PAD |
0.000 |
Clock |
|
|
|
|
Clock path delay |
0.000 |
|
\LCD:Cntl_Port:Sync:ctrl_reg\/control_3 |
Pin_DB7(0)_PAD |
22.479 |
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,0) |
1 |
\LCD:Cntl_Port:Sync:ctrl_reg\ |
\LCD:Cntl_Port:Sync:ctrl_reg\/busclk |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_3 |
2.050 |
Route |
|
1 |
Net_23 |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_3 |
Pin_DB7(0)/pin_input |
5.268 |
iocell8 |
P3[7] |
1 |
Pin_DB7(0) |
Pin_DB7(0)/pin_input |
Pin_DB7(0)/pad_out |
15.161 |
Route |
|
1 |
Pin_DB7(0)_PAD |
Pin_DB7(0)/pad_out |
Pin_DB7(0)_PAD |
0.000 |
Clock |
|
|
|
|
Clock path delay |
0.000 |
|
\LCD:Cntl_Port:Sync:ctrl_reg\/control_5 |
Pin_RS(0)_PAD |
22.381 |
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,0) |
1 |
\LCD:Cntl_Port:Sync:ctrl_reg\ |
\LCD:Cntl_Port:Sync:ctrl_reg\/busclk |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_5 |
2.050 |
Route |
|
1 |
Net_18 |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_5 |
Pin_RS(0)/pin_input |
5.352 |
iocell3 |
P3[1] |
1 |
Pin_RS(0) |
Pin_RS(0)/pin_input |
Pin_RS(0)/pad_out |
14.979 |
Route |
|
1 |
Pin_RS(0)_PAD |
Pin_RS(0)/pad_out |
Pin_RS(0)_PAD |
0.000 |
Clock |
|
|
|
|
Clock path delay |
0.000 |
|
\LCD:Cntl_Port:Sync:ctrl_reg\/control_4 |
Pin_EN(0)_PAD |
21.917 |
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(3,0) |
1 |
\LCD:Cntl_Port:Sync:ctrl_reg\ |
\LCD:Cntl_Port:Sync:ctrl_reg\/busclk |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_4 |
2.050 |
Route |
|
1 |
Net_19 |
\LCD:Cntl_Port:Sync:ctrl_reg\/control_4 |
Pin_EN(0)/pin_input |
5.276 |
iocell4 |
P3[3] |
1 |
Pin_EN(0) |
Pin_EN(0)/pin_input |
Pin_EN(0)/pad_out |
14.591 |
Route |
|
1 |
Pin_EN(0)_PAD |
Pin_EN(0)/pad_out |
Pin_EN(0)_PAD |
0.000 |
Clock |
|
|
|
|
Clock path delay |
0.000 |
|