Static Timing Analysis

Project : i2c_prueba
Build Time : 11/05/20 20:23:20
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LCD:Cntl_Port:Sync:ctrl_reg\/control_0 Pin_DB4(0)_PAD 23.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_20 \LCD:Cntl_Port:Sync:ctrl_reg\/control_0 Pin_DB4(0)/pin_input 6.151
iocell5 P3[4] 1 Pin_DB4(0) Pin_DB4(0)/pin_input Pin_DB4(0)/pad_out 14.987
Route 1 Pin_DB4(0)_PAD Pin_DB4(0)/pad_out Pin_DB4(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_2 Pin_DB6(0)_PAD 22.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_22 \LCD:Cntl_Port:Sync:ctrl_reg\/control_2 Pin_DB6(0)/pin_input 6.190
iocell7 P3[6] 1 Pin_DB6(0) Pin_DB6(0)/pin_input Pin_DB6(0)/pad_out 14.591
Route 1 Pin_DB6(0)_PAD Pin_DB6(0)/pad_out Pin_DB6(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_1 Pin_DB5(0)_PAD 22.692
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_21 \LCD:Cntl_Port:Sync:ctrl_reg\/control_1 Pin_DB5(0)/pin_input 5.304
iocell6 P3[5] 1 Pin_DB5(0) Pin_DB5(0)/pin_input Pin_DB5(0)/pad_out 15.338
Route 1 Pin_DB5(0)_PAD Pin_DB5(0)/pad_out Pin_DB5(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_3 Pin_DB7(0)_PAD 22.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_23 \LCD:Cntl_Port:Sync:ctrl_reg\/control_3 Pin_DB7(0)/pin_input 5.268
iocell8 P3[7] 1 Pin_DB7(0) Pin_DB7(0)/pin_input Pin_DB7(0)/pad_out 15.161
Route 1 Pin_DB7(0)_PAD Pin_DB7(0)/pad_out Pin_DB7(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_5 Pin_RS(0)_PAD 22.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_18 \LCD:Cntl_Port:Sync:ctrl_reg\/control_5 Pin_RS(0)/pin_input 5.352
iocell3 P3[1] 1 Pin_RS(0) Pin_RS(0)/pin_input Pin_RS(0)/pad_out 14.979
Route 1 Pin_RS(0)_PAD Pin_RS(0)/pad_out Pin_RS(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_4 Pin_EN(0)_PAD 21.917
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_19 \LCD:Cntl_Port:Sync:ctrl_reg\/control_4 Pin_EN(0)/pin_input 5.276
iocell4 P3[3] 1 Pin_EN(0) Pin_EN(0)/pin_input Pin_EN(0)/pad_out 14.591
Route 1 Pin_EN(0)_PAD Pin_EN(0)/pad_out Pin_EN(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2C:I2C_FF\/scl_out SCL(0)_PAD:out 20.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/scl_out 1.000
Route 1 \I2C:Net_643_0\ \I2C:I2C_FF\/scl_out SCL(0)/pin_input 2.900
iocell1 P12[4] 1 SCL(0) SCL(0)/pin_input SCL(0)/pad_out 16.615
Route 1 SCL(0)_PAD SCL(0)/pad_out SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C:I2C_FF\/sda_out SDA(0)_PAD:out 19.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/sda_out 1.000
Route 1 \I2C:sda_x_wire\ \I2C:I2C_FF\/sda_out SDA(0)/pin_input 2.901
iocell2 P12[5] 1 SDA(0) SDA(0)/pin_input SDA(0)/pad_out 16.038
Route 1 SDA(0)_PAD SDA(0)/pad_out SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000