enocan3  2.0.0.0
enocean3.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN3_H
36 #define ENOCEAN3_H
37 
42 #ifdef PREINIT_SUPPORTED
43 #include "preinit.h"
44 #endif
45 
46 #ifdef MikroCCoreVersion
47  #if MikroCCoreVersion >= 1
48  #include "delays.h"
49  #endif
50 #endif
51 
52 #include "drv_digital_out.h"
53 #include "drv_digital_in.h"
54 #include "drv_uart.h"
55 
56 
57 // -------------------------------------------------------------- PUBLIC MACROS
67 #define ENOCEAN3_MAP_MIKROBUS( cfg, mikrobus ) \
68  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
69  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX ); \
70  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST )
71 
78 #define ENOCEAN3_RETVAL uint8_t
79 
80 #define ENOCEAN3_OK 0x00
81 #define ENOCEAN3_INIT_ERROR 0xFF
82 
88 #define DRV_RX_BUFFER_SIZE 500
89 #define DRV_TX_BUFFER_SIZE 100
90 
93 #define ENOCEAN3_SYNC_BYTE 0x55
94 #define ENOCEAN3_MAX_BUFF_SIZE 256
95 #define ENOCEAN3_HEADER_SIZE 0x04
96 #define ENOCEAN3_BUFF_EMPTY 0x00
97 
98 
99 #define ENOCEAN3_RESPONSE_READY 0x01
100 #define ENOCEAN3_RESPONSE_NOT_READY 0x00
101 #define ENOCEAN3_UART_RX_READY 0x01
102 #define ENOCEAN3_UART_RX_NOT_READY 0x00
103 #define ENOCEAN3_OK 0x00
104 #define ENOCEAN3_INVALID_PACKET_SIZE 0x01
105 
106 #define ENOCEAN3_PACK_TYPE_EVENT 0x04
107 #define ENOCEAN3_PACK_TYPE_COMMON_COMMAND 0x05
108 #define ENOCEAN3_CO_EVENT_SECUREDEVICES 0x05
109 #define ENOCEAN3_CO_WR_FILTER_ADD 0x0B
110 #define ENOCEAN3_CO_WR_FILTER_ENABLE 0x0E
111 #define ENOCEAN3_CO_WR_REPEATER 0x09
112 #define ENOCEAN3_CO_SET_NOISETHRESHOLD 0x32
113 
114 #define ENOCEAN3_FILT_TYPE_SOURCE_ID 0x00
115 #define ENOCEAN3_FILT_TYPE_R_ORG 0x01
116 #define ENOCEAN3_FILT_TYPE_RSSI 0x02
117 #define ENOCEAN3_FILT_TYPE_DEST_ID 0x03
118 #define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD 0x00
119 #define ENOCEAN3_FILT_KIND_POS_TEL_FWRD 0x80
120 #define ENOCEAN3_FILT_KIND_NEG_TEL_RPT 0x40
121 #define ENOCEAN3_FILT_KIND_POS_TEL_RPT 0xC0
122 #define ENOCEAN3_FILT_FWRD_OFF 0x00
123 #define ENOCEAN3_FILT_FWRD_ON 0x01
124 #define ENOCEAN3_FILT_OP_OR_ALL_FILT 0x00
125 #define ENOCEAN3_FILT_OP_AND_ALL_FILT 0x01
126 #define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT 0x08
127 #define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT 0x09
128 #define ENOCEAN3_RPT_OFF 0x00
129 #define ENOCEAN3_RPT_ALL_TELEG 0x01
130 #define ENOCEAN3_RPT_SELECTIVE 0x02
131 #define ENOCEAN3_RPT_LEVEL_OFF 0x00
132 #define ENOCEAN3_RPT_LEVEL_ONE 0x01
133 #define ENOCEAN3_RPT_LEVEL_TWO 0x02
134 #define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG 0x2E
135 #define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG 0x2F
136 #define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG 0x30
137 #define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG 0x31
138 #define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG 0x32
139 #define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG 0x33
140 #define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG 0x34
141 #define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG 0x35
142 #define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG 0x36
143 #define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG 0x37
144 #define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG 0x38
145  // End group macro
147 // --------------------------------------------------------------- PUBLIC TYPES /** @{ */
153 
154 typedef struct {
155 
156  uint16_t data_length;
157  uint8_t opt_length;
158  uint8_t packet_type;
159  uint8_t data_buff[ 256 ];
160 
162 
163 typedef void ( *enocean3_hdl_t )( enocean3_packet_t*, uint16_t* );
164 
168 typedef struct
169 {
170  // Output pins
171 
172  digital_out_t rst;
173 
174  // Modules
175 
176  uart_t uart;
177 
178  char uart_rx_buffer[ DRV_RX_BUFFER_SIZE ];
179  char uart_tx_buffer[ DRV_TX_BUFFER_SIZE ];
180 
182  uint8_t response_ready;
183 
184 } enocean3_t;
185 
189 typedef struct
190 {
191  // Communication gpio pins
192 
193  pin_name_t rx_pin;
194  pin_name_t tx_pin;
195 
196  // Additional gpio pins
197 
198  pin_name_t rst;
199 
200  // static variable
201 
202  uint32_t baud_rate; // Clock speed.
204  uart_data_bits_t data_bit; // Data bits.
205  uart_parity_t parity_bit; // Parity bit.
206  uart_stop_bits_t stop_bit; // Stop bits.
207 
209 
213 typedef uint8_t enocean3_error_t;
214  // End types group
216 
217 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
218 
224 #ifdef __cplusplus
225 extern "C"{
226 #endif
227 
237 
246 
252 void enocean3_set_rst_pin ( enocean3_t *ctx, uint8_t state );
253 
260 void enocean3_generic_write ( enocean3_t *ctx, char *data_buf, uint16_t len );
261 
269 int32_t enocean3_generic_read ( enocean3_t *ctx, char *data_buf, uint16_t max_len );
270 
280 
292 
303 
313 
314 
315 #ifdef __cplusplus
316 }
317 #endif
318 #endif // _ENOCEAN3_H_
319  // End public_function group
322 
323 // ------------------------------------------------------------------------- END
enocean3_response_ready
uint8_t enocean3_response_ready(enocean3_t *ctx)
Response Ready function.
enocean3_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocean3.h:193
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocean3.h:88
enocean3_t
Click ctx object definition.
Definition: enocean3.h:169
enocean3_error_t
uint8_t enocean3_error_t
Error type.
Definition: enocean3.h:213
ENOCEAN3_RETVAL
#define ENOCEAN3_RETVAL
Definition: enocean3.h:78
enocean3_response_handler_set
void enocean3_response_handler_set(enocean3_t *ctx, enocean3_hdl_t handler)
Handler Set function.
enocean3_t::driver_hdl
enocean3_hdl_t driver_hdl
Definition: enocean3.h:181
enocean3_t::response_ready
uint8_t response_ready
Definition: enocean3.h:182
enocean3_generic_read
int32_t enocean3_generic_read(enocean3_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocean3_cfg_t
Click configuration structure definition.
Definition: enocean3.h:190
enocean3_packet_t::opt_length
uint8_t opt_length
Definition: enocean3.h:157
enocean3_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocean3.h:194
enocean3_t::uart
uart_t uart
Definition: enocean3.h:176
enocean3_cfg_setup
void enocean3_cfg_setup(enocean3_cfg_t *cfg)
Config Object Initialization function.
enocean3_set_rst_pin
void enocean3_set_rst_pin(enocean3_t *ctx, uint8_t state)
Set RST ( reset ) pin state.
enocean3_cfg_t::rst
pin_name_t rst
Definition: enocean3.h:198
enocean3_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocean3.h:206
enocean3_packet_t::packet_type
uint8_t packet_type
Definition: enocean3.h:158
enocean3_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocean3.h:202
enocean3_send_packet
uint8_t enocean3_send_packet(enocean3_t *ctx, enocean3_packet_t *packet)
Packet Send function.
enocean3_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocean3.h:204
enocean3_t::rst
digital_out_t rst
Definition: enocean3.h:172
DRV_TX_BUFFER_SIZE
#define DRV_TX_BUFFER_SIZE
Definition: enocean3.h:89
enocean3_uart_isr
void enocean3_uart_isr(enocean3_t *ctx)
UART Interrupt Routine function.
enocean3_packet_t::data_length
uint16_t data_length
Definition: enocean3.h:156
enocean3_cfg_t::uart_blocking
bool uart_blocking
Definition: enocean3.h:203
enocean3_init
ENOCEAN3_RETVAL enocean3_init(enocean3_t *ctx, enocean3_cfg_t *cfg)
Initialization function.
enocean3_packet_t
Definition: enocean3.h:154
enocean3_hdl_t
void(* enocean3_hdl_t)(enocean3_packet_t *, uint16_t *)
Definition: enocean3.h:163
enocean3_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocean3.h:205
enocean3_generic_write
void enocean3_generic_write(enocean3_t *ctx, char *data_buf, uint16_t len)
Generic write function.