nfc5  2.1.0.0
Macros
NFC 5 Registers Settings

Settings for registers of NFC 5 Click driver. More...

Macros

#define NFC5_MODE_REG_WRITE   0x00
 NFC 5 Communication operation mode setting. More...
 
#define NFC5_MODE_REG_READ   0x40
 
#define NFC5_MODE_FIFO_LOAD   0x80
 
#define NFC5_MODE_PT_MEM_LOAD_A_CFG   0xA0
 
#define NFC5_MODE_PT_MEM_LOAD_F_CFG   0xA8
 
#define NFC5_MODE_PT_MEM_LOAD_TSN_DATA   0xAC
 
#define NFC5_MODE_PT_MEM_READ   0xBF
 
#define NFC5_MODE_FIFO_READ   0x9F
 
#define NFC5_MODE_DIRECT_COMMAND   0xC0
 
#define NFC5_IC_TYPE_CODE   0x05
 NFC 5 IC Identity default value. More...
 
#define NFC5_IC_REVISION_CODE_MASK   0x07
 
#define NFC5_IRQ_MASK_ALL   0xFFFFFFFFul
 NFC 5 IRQ masks. More...
 
#define NFC5_IRQ_MASK_NONE   0x00000000ul
 
#define NFC5_IRQ_MASK_OSC   0x00000080ul
 
#define NFC5_IRQ_MASK_FWL   0x00000040ul
 
#define NFC5_IRQ_MASK_RXS   0x00000020ul
 
#define NFC5_IRQ_MASK_RXE   0x00000010ul
 
#define NFC5_IRQ_MASK_TXE   0x00000008ul
 
#define NFC5_IRQ_MASK_COL   0x00000004ul
 
#define NFC5_IRQ_MASK_RX_REST   0x00000002ul
 
#define NFC5_IRQ_MASK_RFU   0x00000001ul
 
#define NFC5_IRQ_MASK_DCT   0x00008000ul
 
#define NFC5_IRQ_MASK_NRE   0x00004000ul
 
#define NFC5_IRQ_MASK_GPE   0x00002000ul
 
#define NFC5_IRQ_MASK_EON   0x00001000ul
 
#define NFC5_IRQ_MASK_EOF   0x00000800ul
 
#define NFC5_IRQ_MASK_CAC   0x00000400ul
 
#define NFC5_IRQ_MASK_CAT   0x00000200ul
 
#define NFC5_IRQ_MASK_NFCT   0x00000100ul
 
#define NFC5_IRQ_MASK_CRC   0x00800000ul
 
#define NFC5_IRQ_MASK_PAR   0x00400000ul
 
#define NFC5_IRQ_MASK_ERR2   0x00200000ul
 
#define NFC5_IRQ_MASK_ERR1   0x00100000ul
 
#define NFC5_IRQ_MASK_WT   0x00080000ul
 
#define NFC5_IRQ_MASK_WAM   0x00040000ul
 
#define NFC5_IRQ_MASK_WPH   0x00020000ul
 
#define NFC5_IRQ_MASK_WCAP   0x00010000ul
 
#define NFC5_IRQ_MASK_PPON2   0x80000000ul
 
#define NFC5_IRQ_MASK_SL_WL   0x40000000ul
 
#define NFC5_IRQ_MASK_APON   0x20000000ul
 
#define NFC5_IRQ_MASK_RXE_PTA   0x10000000ul
 
#define NFC5_IRQ_MASK_WU_F   0x08000000ul
 
#define NFC5_IRQ_MASK_RFU2   0x04000000ul
 
#define NFC5_IRQ_MASK_WU_A_X   0x02000000ul
 
#define NFC5_IRQ_MASK_WU_A   0x01000000ul
 
#define NFC5_TEST_REG_INDICATOR   0x0080
 NFC 5 Click analog config values. More...
 
#define NFC5_ANALOG_CONFIG_LUT_NOT_FOUND   0xFF
 
#define NFC5_ANALOG_CONFIG_BITRATE_MASK   0x00F0
 
#define NFC5_ANALOG_CONFIG_DIRECTION_MASK   0x000F
 
#define NFC5_ANALOG_CONFIG_BITRATE_SHIFT   4
 
#define NFC5_ANALOG_CONFIG_DIRECTION_SHIFT   0
 
#define NFC5_ANALOG_CONFIG_POLL   0x0000
 
#define NFC5_ANALOG_CONFIG_LISTEN   0x8000
 
#define NFC5_ANALOG_CONFIG_TECH_CHIP   0x0000
 
#define NFC5_ANALOG_CONFIG_TECH_NFCA   0x0100
 
#define NFC5_ANALOG_CONFIG_BITRATE_COMMON   0x0000
 
#define NFC5_ANALOG_CONFIG_BITRATE_106   0x0010
 
#define NFC5_ANALOG_CONFIG_TX   0x0001
 
#define NFC5_ANALOG_CONFIG_RX   0x0002
 
#define NFC5_ANALOG_CONFIG_ANTICOL   0x0003
 
#define NFC5_ANALOG_CONFIG_CHIP_INIT   0x0000
 
#define NFC5_ANALOG_CONFIG_CHIP_DEINIT   0x0001
 
#define NFC5_ANALOG_CONFIG_CHIP_FIELD_ON   0x0002
 
#define NFC5_ANALOG_CONFIG_CHIP_FIELD_OFF   0x0003
 
#define NFC5_ANALOG_CONFIG_CHIP_POLL_COMMON   0x0008
 
#define NFC5_1FC_IN_4096FC   4096u
 NFC 5 Click RFAL macros. More...
 
#define NFC5_1FC_IN_512FC   512u
 
#define NFC5_1FC_IN_64FC   64u
 
#define NFC5_1FC_IN_8FC   8u
 
#define NFC5_US_IN_MS   1000u
 
#define NFC5_1MS_IN_1FC   13560u
 
#define NFC5_BITS_IN_BYTE   8u
 
#define NFC5_CRC_LEN   2u
 
#define NFC5_RFAL_CONV_1FC_TO_64FC(T)   ( uint32_t ) ( ( uint32_t ) ( T ) / NFC5_1FC_IN_64FC )
 
#define NFC5_RFAL_CONV_64FC_TO_1FC(T)   ( uint32_t ) ( ( uint32_t ) ( T ) * NFC5_1FC_IN_64FC )
 
#define NFC5_RFAL_CONV_BITS_TO_BYTES(N)
 
#define NFC5_RFAL_CONV_BYTES_TO_BITS(N)   ( uint32_t ) ( ( uint32_t) ( N ) * ( NFC5_BITS_IN_BYTE ) )
 
#define NFC5_RFAL_CONV_1FC_TO_4096FC(T)   ( uint32_t ) ( ( uint32_t) ( T ) / NFC5_1FC_IN_4096FC )
 
#define NFC5_RFAL_CONV_4096FC_TO_1FC(T)   ( uint32_t ) ( ( uint32_t) ( T ) * NFC5_1FC_IN_4096FC )
 
#define NFC5_RFAL_CONV_1FC_TO_MS(T)   ( uint32_t ) ( ( uint32_t) ( T ) / NFC5_1MS_IN_1FC )
 
#define NFC5_RFAL_CONV_MS_TO_1FC(T)   ( uint32_t ) ( ( uint32_t) ( T ) * NFC5_1MS_IN_1FC )
 
#define NFC5_FWT_NONE   0xFFFFFFFFul
 
#define NFC5_FWT_ADJUSTMENT   64u
 
#define NFC5_FWT_A_ADJUSTMENT   ( 512u + 64u )
 
#define NFC5_NRT_MAX_1FC   NFC5_RFAL_CONV_4096FC_TO_1FC( 0xFFFFu )
 
#define NFC5_MRT_MIN_1FC   NFC5_RFAL_CONV_64FC_TO_1FC( 0x0004u )
 
#define NFC5_NRT_DISABLED   0u
 
#define NFC5_NRT_MAX   0xFFFFu
 
#define NFC5_RFAL_CALC_NUM_BYTES(NBITS)   ( ( ( uint32_t )( NBITS ) + 7u ) / 8u )
 
#define NFC5_RFAL_CREATE_BYTE_FLAGS_TX_RX_CONTEXT(CTX, TB, TBL, RB, RBL, RDL, FL, T)
 NFC 5 Click rfal create byte flags tx rx context macro. More...
 
#define NFC5_NFCA_CASCADE_1_UID_LEN   4u
 NFC 5 Click RFAL NFC macros. More...
 
#define NFC5_NFCA_CASCADE_2_UID_LEN   7u
 
#define NFC5_NFCA_CASCADE_3_UID_LEN   10u
 
#define NFC5_NFC_MAX_DEVICES   5u
 
#define NFC5_THLD_DO_NOT_SET   0xFFu
 
#define NFC5_NFCA_FDTMIN   1620u
 
#define NFC5_RFAL_NFCA_CLN2_SEL_CMD(CL)   ( uint8_t )( ( uint8_t )( NFC5_NFCA_CMD_SEL_CL1 ) + ( 2u * ( CL ) ) )
 
#define NFC5_RFAL_NFCA_SEL_PAR(NBY, NBI)   ( uint8_t )( ( ( ( NBY ) << 4u ) & 0xF0u ) | ( ( NBI ) &0x0Fu ) )
 
#define NFC5_RFAL_NFCA_NFC_ID_LEN_2CL(LEN)   ( ( LEN ) / 5u )
 
#define NFC5_NFCA_SLP_FWT   NFC5_RFAL_CONV_MS_TO_1FC ( 1 )
 
#define NFC5_NFCA_SLP_CMD   0x50u
 
#define NFC5_NFCA_SLP_BYTE2   0x00u
 
#define NFC5_NFCA_SLP_CMD_POS   0u
 
#define NFC5_NFCA_SLP_BYTE2_POS   1u
 
#define NFC5_NFCA_SDD_CT   0x88u
 
#define NFC5_NFCA_SDD_CT_LEN   1u
 
#define NFC5_NFCA_SLP_REQ_LEN   2u
 
#define NFC5_NFCA_SEL_CMD_LEN   1u
 
#define NFC5_NFCA_SEL_PAR_LEN   1u
 
#define NFC5_NFCA_SEL_SELPAR   NFC5_RFAL_NFCA_SEL_PAR( 7u, 0u )
 
#define NFC5_NFCA_BCC_LEN   1u
 
#define NFC5_NFCA_SDD_REQ_LEN   ( NFC5_NFCA_SEL_CMD_LEN + NFC5_NFCA_SEL_PAR_LEN )
 
#define NFC5_NFCA_SDD_RES_LEN   ( NFC5_NFCA_CASCADE_1_UID_LEN + NFC5_NFCA_BCC_LEN )
 
#define NFC5_NFCA_N_RETRANS   2u
 
#define NFC5_ISO14443A_SDD_RES_LEN   5u
 
#define NFC5_TXRX_FLAGS_DEFAULT
 
#define NFC5_FIFO_DEPTH   512u
 NFC 5 Click NFC FIFO macros. More...
 
#define NFC5_FIFO_STATUS_REG1   0u
 
#define NFC5_FIFO_STATUS_REG2   1u
 
#define NFC5_FIFO_STATUS_INVALID   0xFFu
 
#define NFC5_FIFO_IN_WL   200u
 
#define NFC5_FIFO_OUT_WL   ( NFC5_FIFO_DEPTH - NFC5_FIFO_IN_WL )
 
#define NFC5_IO_CFG_1_SINGLE   ( 1u << 7 )
 NFC 5 Click register bits value. More...
 
#define NFC5_IO_CFG_1_RFO2   ( 1u << 6 )
 
#define NFC5_IO_CFG_1_I2C_THD1   ( 1u << 5 )
 
#define NFC5_IO_CFG_1_I2C_THD0   ( 1u << 4 )
 
#define NFC5_IO_CFG_1_I2C_THD_MASK   ( 3u << 4 )
 
#define NFC5_IO_CFG_1_I2C_THD_SHIFT   ( 4u )
 
#define NFC5_IO_CFG_1_RFU   ( 1u << 3 )
 
#define NFC5_IO_CFG_1_OUT_CL1   ( 1u << 2 )
 
#define NFC5_IO_CFG_1_OUT_CL0   ( 1u << 1 )
 
#define NFC5_IO_CFG_1_OUT_CL_DISABLED   ( 3u << 1 )
 
#define NFC5_IO_CFG_1_OUT_CL_13_56MHZ   ( 2u << 1 )
 
#define NFC5_IO_CFG_1_OUT_CL_4_78MHZ   ( 1u << 1 )
 
#define NFC5_IO_CFG_1_OUT_CL_3_39MHZ   ( 0u << 1 )
 
#define NFC5_IO_CFG_1_OUT_CL_MASK   ( 3u << 1 )
 
#define NFC5_IO_CFG_1_OUT_CL_SHIFT   ( 1u )
 
#define NFC5_IO_CFG_1_LF_CLK_OFF   ( 1u << 0 )
 
#define NFC5_IO_CFG_1_LF_CLK_OFF_ON   ( 1u << 0 )
 
#define NFC5_IO_CFG_1_LF_CLK_OFF_OFF   ( 0u << 0 )
 
#define NFC5_IO_CFG_2_SUP3V   ( 1u << 7 )
 
#define NFC5_IO_CFG_2_SUP3V_3V   ( 1u << 7 )
 
#define NFC5_IO_CFG_2_SUP3V_5V   ( 0u << 7 )
 
#define NFC5_IO_CFG_2_VSPD_OFF   ( 1u << 6 )
 
#define NFC5_IO_CFG_2_AAT_EN   ( 1u << 5 )
 
#define NFC5_IO_CFG_2_MISO_PD2   ( 1u << 4 )
 
#define NFC5_IO_CFG_2_MISO_PD1   ( 1u << 3 )
 
#define NFC5_IO_CFG_2_IO_DRV_LVL   ( 1u << 2 )
 
#define NFC5_IO_CFG_2_SLOW_UP   ( 1u << 0 )
 
#define NFC5_ISO14443A_NFC_NO_TX_PAR   ( 1u << 7 )
 
#define NFC5_ISO14443A_NFC_NO_TX_PAR_OFF   ( 0u << 7 )
 
#define NFC5_ISO14443A_NFC_NO_RX_PAR   ( 1u << 6 )
 
#define NFC5_ISO14443A_NFC_NO_RX_PAR_OFF   ( 0u << 6 )
 
#define NFC5_ISO14443A_NFC_NFC_F0   ( 1u << 5 )
 
#define NFC5_ISO14443A_NFC_NFC_F0_OFF   ( 0u << 5 )
 
#define NFC5_ISO14443A_NFC_P_LEN3   ( 1u << 4 )
 
#define NFC5_ISO14443A_NFC_P_LEN2   ( 1u << 3 )
 
#define NFC5_ISO14443A_NFC_P_LEN1   ( 1u << 2 )
 
#define NFC5_ISO14443A_NFC_P_LEN0   ( 1u << 1 )
 
#define NFC5_ISO14443A_NFC_P_LEN_MASK   ( 0xFu << 1 )
 
#define NFC5_ISO14443A_NFC_P_LEN_SHIFT   ( 1u )
 
#define NFC5_ISO14443A_NFC_ANTCL   ( 1u << 0 )
 
#define NFC5_RX_CFG_2_DEMOD_MODE   ( 1u << 7 )
 
#define NFC5_RX_CFG_2_AMD_SEL   ( 1u << 6 )
 
#define NFC5_RX_CFG_2_AMD_SEL_MIXER   ( 1u << 6 )
 
#define NFC5_RX_CFG_2_AMD_SEL_PEAK   ( 0u << 6 )
 
#define NFC5_RX_CFG_2_SQM_DYN   ( 1u << 5 )
 
#define NFC5_RX_CFG_2_PULZ_61   ( 1u << 4 )
 
#define NFC5_RX_CFG_2_AGC_EN   ( 1u << 3 )
 
#define NFC5_RX_CFG_2_AGC_M   ( 1u << 2 )
 
#define NFC5_RX_CFG_2_AGC_ALG   ( 1u << 1 )
 
#define NFC5_RX_CFG_2_AGC6_3   ( 1u << 0 )
 
#define NFC5_OP_CTRL_EN   ( 1u << 7 )
 
#define NFC5_OP_CTRL_RX_EN   ( 1u << 6 )
 
#define NFC5_OP_CTRL_RX_CHN   ( 1u << 5 )
 
#define NFC5_OP_CTRL_RX_MAN   ( 1u << 4 )
 
#define NFC5_OP_CTRL_TX_EN   ( 1u << 3 )
 
#define NFC5_OP_CTRL_WU   ( 1u << 2 )
 
#define NFC5_OP_CTRL_EN_FD_C1   ( 1u << 1 )
 
#define NFC5_OP_CTRL_EN_FD_C0   ( 1u << 0 )
 
#define NFC5_OP_CTRL_EN_FD_EFD_OFF   ( 0u << 0 )
 
#define NFC5_OP_CTRL_EN_FD_MANUAL_EFD_CA   ( 1u << 0 )
 
#define NFC5_OP_CTRL_EN_FD_MANUAL_EFD_PDT   ( 2u << 0 )
 
#define NFC5_OP_CTRL_EN_FD_AUTO_EFD   ( 3u << 0 )
 
#define NFC5_OP_CTRL_EN_FD_SHIFT   ( 0u )
 
#define NFC5_OP_CTRL_EN_FD_MASK   ( 3u << 0 )
 
#define NFC5_NFCIP1_BIT_RATE_NFC_RFU1   ( 1u << 7 )
 
#define NFC5_NFCIP1_BIT_RATE_NFC_RFU0   ( 1u << 6 )
 
#define NFC5_NFCIP1_BIT_RATE_NFC_RATE1   ( 1u << 5 )
 
#define NFC5_NFCIP1_BIT_RATE_NFC_RATE0   ( 1u << 4 )
 
#define NFC5_NFCIP1_BIT_RATE_NFC_RATE_MASK   ( 0x3u << 4 )
 
#define NFC5_NFCIP1_BIT_RATE_NFC_RATE_SHIFT   ( 4u )
 
#define NFC5_NFCIP1_BIT_RATE_PPT2_ON   ( 1u << 3 )
 
#define NFC5_NFCIP1_BIT_RATE_GPT_ON   ( 1u << 2 )
 
#define NFC5_NFCIP1_BIT_RATE_NRT_ON   ( 1u << 1 )
 
#define NFC5_NFCIP1_BIT_RATE_MRT_ON   ( 1u << 0 )
 
#define NFC5_AUX_DISPLAY_A_CHA   ( 1u << 7 )
 
#define NFC5_AUX_DISPLAY_EFD_O   ( 1u << 6 )
 
#define NFC5_AUX_DISPLAY_TX_ON   ( 1u << 5 )
 
#define NFC5_AUX_DISPLAY_OSC_OK   ( 1u << 4 )
 
#define NFC5_AUX_DISPLAY_RX_ON   ( 1u << 3 )
 
#define NFC5_AUX_DISPLAY_RX_ACT   ( 1u << 2 )
 
#define NFC5_AUX_DISPLAY_EN_PEER   ( 1u << 1 )
 
#define NFC5_AUX_DISPLAY_EN_AC   ( 1u << 0 )
 
#define NFC5_FIFO_STATUS2_FIFO_B9   ( 1u << 7 )
 
#define NFC5_FIFO_STATUS2_FIFO_B8   ( 1u << 6 )
 
#define NFC5_FIFO_STATUS2_FIFO_B_MASK   ( 3u << 6 )
 
#define NFC5_FIFO_STATUS2_FIFO_B_SHIFT   ( 6u )
 
#define NFC5_FIFO_STATUS2_FIFO_UNF   ( 1u << 5 )
 
#define NFC5_FIFO_STATUS2_FIFO_OVR   ( 1u << 4 )
 
#define NFC5_FIFO_STATUS2_FIFO_LB2   ( 1u << 3 )
 
#define NFC5_FIFO_STATUS2_FIFO_LB1   ( 1u << 2 )
 
#define NFC5_FIFO_STATUS2_FIFO_LB0   ( 1u << 1 )
 
#define NFC5_FIFO_STATUS2_FIFO_LB_MASK   ( 7u << 1 )
 
#define NFC5_FIFO_STATUS2_FIFO_LB_SHIFT   ( 1u )
 
#define NFC5_FIFO_STATUS2_NP_LB   ( 1u << 0 )
 
#define NFC5_MODE_TARG   ( 1u << 7 )
 
#define NFC5_MODE_TARG_TARG   ( 1u << 7 )
 
#define NFC5_MODE_TARG_INIT   ( 0u << 7 )
 
#define NFC5_MODE_OM3   ( 1u << 6 )
 
#define NFC5_MODE_OM2   ( 1u << 5 )
 
#define NFC5_MODE_OM1   ( 1u << 4 )
 
#define NFC5_MODE_OM0   ( 1u << 3 )
 
#define NFC5_MODE_OM_BPSK_STREAM   ( 0xFu << 3 )
 
#define NFC5_MODE_OM_SUBCARRIER_STREAM   ( 0xEu << 3 )
 
#define NFC5_MODE_OM_TOPAZ   ( 0x4u << 3 )
 
#define NFC5_MODE_OM_FELICA   ( 0x3u << 3 )
 
#define NFC5_MODE_OM_ISO14443B   ( 0x2u << 3 )
 
#define NFC5_MODE_OM_ISO14443A   ( 0x1u << 3 )
 
#define NFC5_MODE_OM_TARG_NFCA   ( 0x1u << 3 )
 
#define NFC5_MODE_OM_TARG_NFCB   ( 0x2u << 3 )
 
#define NFC5_MODE_OM_TARG_NFCF   ( 0x4u << 3 )
 
#define NFC5_MODE_OM_TARG_NFCIP   ( 0x7u << 3 )
 
#define NFC5_MODE_OM_NFC   ( 0x0u << 3 )
 
#define NFC5_MODE_OM_MASK   ( 0xFu << 3 )
 
#define NFC5_MODE_OM_SHIFT   ( 3u )
 
#define NFC5_MODE_TR_AM   ( 1u << 2 )
 
#define NFC5_MODE_TR_AM_OOK   ( 0u << 2 )
 
#define NFC5_MODE_TR_AM_AM   ( 1u << 2 )
 
#define NFC5_MODE_NFC_AR1   ( 1u << 1 )
 
#define NFC5_MODE_NFC_AR0   ( 1u << 0 )
 
#define NFC5_MODE_NFC_AR_OFF   ( 0u << 0 )
 
#define NFC5_MODE_NFC_AR_AUTO_RX   ( 1u << 0 )
 
#define NFC5_MODE_NFC_AR_EOF   ( 2u << 0 )
 
#define NFC5_MODE_NFC_AR_RFU   ( 3u << 0 )
 
#define NFC5_MODE_NFC_AR_MASK   ( 3u << 0 )
 
#define NFC5_MODE_NFC_AR_SHIFT   ( 0u )
 
#define NFC5_BIT_RATE_TXRATE_106   ( 0x0u << 4 )
 
#define NFC5_BIT_RATE_TXRATE_212   ( 0x1u << 4 )
 
#define NFC5_BIT_RATE_TXRATE_424   ( 0x2u << 4 )
 
#define NFC5_BIT_RATE_TXRATE_848   ( 0x3u << 4 )
 
#define NFC5_BIT_RATE_TXRATE_MASK   ( 0x3u << 4 )
 
#define NFC5_BIT_RATE_TXRATE_SHIFT   ( 4u )
 
#define NFC5_BIT_RATE_RXRATE_106   ( 0x0u << 0 )
 
#define NFC5_BIT_RATE_RXRATE_212   ( 0x1u << 0 )
 
#define NFC5_BIT_RATE_RXRATE_424   ( 0x2u << 0 )
 
#define NFC5_BIT_RATE_RXRATE_848   ( 0x3u << 0 )
 
#define NFC5_BIT_RATE_RXRATE_MASK   ( 0x3u << 0 )
 
#define NFC5_BIT_RATE_RXRATE_SHIFT   ( 0u )
 
#define NFC5_AUX_MOD_DIS_REG_AM   ( 1u << 7 )
 
#define NFC5_AUX_MOD_LM_EXT_POL   ( 1u << 6 )
 
#define NFC5_AUX_MOD_LM_EXT   ( 1u << 5 )
 
#define NFC5_AUX_MOD_LM_DRI   ( 1u << 4 )
 
#define NFC5_AUX_MOD_RES_AM   ( 1u << 3 )
 
#define NFC5_AUX_MOD_RFU2   ( 1u << 2 )
 
#define NFC5_AUX_MOD_RFU1   ( 1u << 1 )
 
#define NFC5_AUX_MOD_RFU0   ( 1u << 0 )
 
#define NFC5_PASSIVE_TARGET_FDEL_3   ( 1u << 7 )
 
#define NFC5_PASSIVE_TARGET_FDEL_2   ( 1u << 6 )
 
#define NFC5_PASSIVE_TARGET_FDEL_1   ( 1u << 5 )
 
#define NFC5_PASSIVE_TARGET_FDEL_0   ( 1u << 4 )
 
#define NFC5_PASSIVE_TARGET_FDEL_MASK   ( 0xFu << 4 )
 
#define NFC5_PASSIVE_TARGET_FDEL_SHIFT   ( 4u )
 
#define NFC5_PASSIVE_TARGET_D_AC_AP2P   ( 1u << 3 )
 
#define NFC5_PASSIVE_TARGET_D_212_424_1R   ( 1u << 2 )
 
#define NFC5_PASSIVE_TARGET_RFU   ( 1u << 1 )
 
#define NFC5_PASSIVE_TARGET_D_106_AC_A   ( 1u << 0 )
 
#define NFC5_PT_MOD_PTM_RES3   ( 1u << 7 )
 
#define NFC5_PT_MOD_PTM_RES2   ( 1u << 6 )
 
#define NFC5_PT_MOD_PTM_RES1   ( 1u << 5 )
 
#define NFC5_PT_MOD_PTM_RES0   ( 1u << 4 )
 
#define NFC5_PT_MOD_PTM_RES_MASK   ( 0xFu << 4 )
 
#define NFC5_PT_MOD_PTM_RES_SHIFT   ( 4u )
 
#define NFC5_PT_MOD_PT_RES3   ( 1u << 3 )
 
#define NFC5_PT_MOD_PT_RES2   ( 1u << 2 )
 
#define NFC5_PT_MOD_PT_RES1   ( 1u << 1 )
 
#define NFC5_PT_MOD_PT_RES0   ( 1u << 0 )
 
#define NFC5_PT_MOD_PT_RES_MASK   ( 0xFu << 0 )
 
#define NFC5_PT_MOD_PT_RES_SHIFT   ( 0u )
 
#define NFC5_EMD_SUP_CFG_EMD_EMV   ( 1u << 7 )
 
#define NFC5_EMD_SUP_CFG_EMD_EMV_ON   ( 1u << 7 )
 
#define NFC5_EMD_SUP_CFG_EMD_EMV_OFF   ( 0u << 7 )
 
#define NFC5_EMD_SUP_CFG_RX_START_EMV   ( 1u << 6 )
 
#define NFC5_EMD_SUP_CFG_RX_START_EMV_ON   ( 1u << 6 )
 
#define NFC5_EMD_SUP_CFG_RX_START_EMV_OFF   ( 0u << 6 )
 
#define NFC5_EMD_SUP_CFG_RFU1   ( 1u << 5 )
 
#define NFC5_EMD_SUP_CFG_RFU0   ( 1u << 4 )
 
#define NFC5_EMD_SUP_CFG_EMD_THLD3   ( 1u << 3 )
 
#define NFC5_EMD_SUP_CFG_EMD_THLD2   ( 1u << 2 )
 
#define NFC5_EMD_SUP_CFG_EMD_THLD1   ( 1u << 1 )
 
#define NFC5_EMD_SUP_CFG_EMD_THLD0   ( 1u << 0 )
 
#define NFC5_EMD_SUP_CFG_EMD_THLD_MASK   ( 0xFu << 0 )
 
#define NFC5_EMD_SUP_CFG_EMD_THLD_SHIFT   ( 0u )
 
#define NFC5_AUX_NO_CRC_RX   ( 1u << 7 )
 
#define NFC5_AUX_RFU   ( 1u << 6 )
 
#define NFC5_AUX_NFC_ID1   ( 1u << 5 )
 
#define NFC5_AUX_NFC_ID0   ( 1u << 4 )
 
#define NFC5_AUX_NFC_ID_7BYTES   ( 1u << 4 )
 
#define NFC5_AUX_NFC_ID_4BYTES   ( 0u << 4 )
 
#define NFC5_AUX_NFC_ID_MASK   ( 3u << 4 )
 
#define NFC5_AUX_NFC_ID_SHIFT   ( 4u )
 
#define NFC5_AUX_MFAZ_CL90   ( 1u << 3 )
 
#define NFC5_AUX_DIS_CORR   ( 1u << 2 )
 
#define NFC5_AUX_DIS_CORR_COHERENT   ( 1u << 2 )
 
#define NFC5_AUX_DIS_CORR_CORRELATOR   ( 0u << 2 )
 
#define NFC5_AUX_NFC_N1   ( 1u << 1 )
 
#define NFC5_AUX_NFC_N0   ( 1u << 0 )
 
#define NFC5_AUX_NFC_N_MASK   ( 3u << 0 )
 
#define NFC5_AUX_NFC_N_SHIFT   ( 0u )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC2   ( 1u << 7 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC1   ( 1u << 6 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC0   ( 1u << 5 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC_NO_TRIGGER   ( 0u << 5 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC_ERX   ( 1u << 5 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC_SRX   ( 2u << 5 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC_ETX_NFC   ( 3u << 5 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC_MASK   ( 7u << 5 )
 
#define NFC5_TIMER_EMV_CONTROL_GPTC_SHIFT   ( 5u )
 
#define NFC5_TIMER_EMV_CONTROL_RFU   ( 1u << 4 )
 
#define NFC5_TIMER_EMV_CONTROL_MRT_STEP   ( 1u << 3 )
 
#define NFC5_TIMER_EMV_CONTROL_MRT_STEP_512   ( 1u << 3 )
 
#define NFC5_TIMER_EMV_CONTROL_MRT_STEP_64   ( 0u << 3 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_NFC   ( 1u << 2 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_NFC_ON   ( 1u << 2 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_NFC_OFF   ( 0u << 2 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_EMV   ( 1u << 1 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_EMV_ON   ( 1u << 1 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_EMV_OFF   ( 0u << 1 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_STEP   ( 1u << 0 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_STEP_64FC   ( 0u << 0 )
 
#define NFC5_TIMER_EMV_CONTROL_NRT_STEP_4096_FC   ( 1u << 0 )
 
#define NFC5_COLLISION_STATUS_C_BYTE3   ( 1u << 7 )
 
#define NFC5_COLLISION_STATUS_C_BYTE2   ( 1u << 6 )
 
#define NFC5_COLLISION_STATUS_C_BYTE1   ( 1u << 5 )
 
#define NFC5_COLLISION_STATUS_C_BYTE0   ( 1u << 4 )
 
#define NFC5_COLLISION_STATUS_C_BYTE_MASK   ( 0xFu << 4 )
 
#define NFC5_COLLISION_STATUS_C_BYTE_SHIFT   ( 4u )
 
#define NFC5_COLLISION_STATUS_C_BIT2   ( 1u << 3 )
 
#define NFC5_COLLISION_STATUS_C_BIT1   ( 1u << 2 )
 
#define NFC5_COLLISION_STATUS_C_BIT0   ( 1u << 1 )
 
#define NFC5_COLLISION_STATUS_C_PB   ( 1u << 0 )
 
#define NFC5_COLLISION_STATUS_C_BIT_MASK   ( 3u << 1 )
 
#define NFC5_COLLISION_STATUS_C_BIT_SHIFT   ( 1u )
 
#define NFC5_CORR_CFG_1_CORR_S7   ( 1u << 7 )
 
#define NFC5_CORR_CFG_1_CORR_S6   ( 1u << 6 )
 
#define NFC5_CORR_CFG_1_CORR_S5   ( 1u << 5 )
 
#define NFC5_CORR_CFG_1_CORR_S4   ( 1u << 4 )
 
#define NFC5_CORR_CFG_1_CORR_S3   ( 1u << 3 )
 
#define NFC5_CORR_CFG_1_CORR_S2   ( 1u << 2 )
 
#define NFC5_CORR_CFG_1_CORR_S1   ( 1u << 1 )
 
#define NFC5_CORR_CFG_1_CORR_S0   ( 1u << 0 )
 
#define NFC5_TX_DRIVER_AM_MOD3   ( 1u << 7 )
 
#define NFC5_TX_DRIVER_AM_MOD2   ( 1u << 6 )
 
#define NFC5_TX_DRIVER_AM_MOD1   ( 1u << 5 )
 
#define NFC5_TX_DRIVER_AM_MOD0   ( 1u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_5PERCENT   ( 0x0u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_6PERCENT   ( 0x1u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_7PERCENT   ( 0x2u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_8PERCENT   ( 0x3u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_9PERCENT   ( 0x4u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_10PERCENT   ( 0x5u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_11PERCENT   ( 0x6u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_12PERCENT   ( 0x7u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_13PERCENT   ( 0x8u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_14PERCENT   ( 0x9u << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_15PERCENT   ( 0xAu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_17PERCENT   ( 0xBu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_19PERCENT   ( 0xCu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_22PERCENT   ( 0xDu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_26PERCENT   ( 0xEu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_40PERCENT   ( 0xFu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_MASK   ( 0xFu << 4 )
 
#define NFC5_TX_DRIVER_AM_MOD_SHIFT   ( 4u )
 
#define NFC5_TX_DRIVER_D_RES3   ( 1u << 3 )
 
#define NFC5_TX_DRIVER_D_RES2   ( 1u << 2 )
 
#define NFC5_TX_DRIVER_D_RES1   ( 1u << 1 )
 
#define NFC5_TX_DRIVER_D_RES0   ( 1u << 0 )
 
#define NFC5_TX_DRIVER_D_RES_MASK   ( 0xFu << 0 )
 
#define NFC5_TX_DRIVER_D_RES_SHIFT   ( 0u )
 
#define NFC5_FIELD_THLD_ACT_TRG_L2A   ( 1u << 6 )
 
#define NFC5_FIELD_THLD_ACT_TRG_L1A   ( 1u << 5 )
 
#define NFC5_FIELD_THLD_ACT_TRG_L0A   ( 1u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_75MV   ( 0x0u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_105MV   ( 0x1u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_150MV   ( 0x2u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_205MV   ( 0x3u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_290MV   ( 0x4u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_400MV   ( 0x5u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_560MV   ( 0x6u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_800MV   ( 0x7u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_MASK   ( 7u << 4 )
 
#define NFC5_FIELD_THLD_ACT_TRG_SHIFT   ( 4u )
 
#define NFC5_FIELD_THLD_ACT_RFE_T3A   ( 1u << 3 )
 
#define NFC5_FIELD_THLD_ACT_RFE_T2A   ( 1u << 2 )
 
#define NFC5_FIELD_THLD_ACT_RFE_T1A   ( 1u << 1 )
 
#define NFC5_FIELD_THLD_ACT_RFE_T0A   ( 1u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_75MV   ( 0x0u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_105MV   ( 0x1u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_150MV   ( 0x2u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_205MV   ( 0x3u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_290MV   ( 0x4u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_400MV   ( 0x5u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_560MV   ( 0x6u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_800MV   ( 0x7u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_25MV   ( 0x8u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_33MV   ( 0x9u << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_47MV   ( 0xAu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_64MV   ( 0xBu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_90MV   ( 0xCu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_125MV   ( 0xDu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_175MV   ( 0xEu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_250MV   ( 0xFu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_MASK   ( 0xFu << 0 )
 
#define NFC5_FIELD_THLD_ACT_RFE_SHIFT   ( 0u )
 
#define NFC5_FIELD_THLD_DEACT_TRG_L2D   ( 1u << 6 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_L1D   ( 1u << 5 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_L0D   ( 1u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_75MV   ( 0x0u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_105MV   ( 0x1u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_150MV   ( 0x2u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_205MV   ( 0x3u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_290MV   ( 0x4u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_400MV   ( 0x5u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_560MV   ( 0x6u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_800MV   ( 0x7u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_MASK   ( 7u << 4 )
 
#define NFC5_FIELD_THLD_DEACT_TRG_SHIFT   ( 4u )
 
#define NFC5_FIELD_THLD_DEACT_RFE_T3D   ( 1u << 3 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_T2D   ( 1u << 2 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_T1D   ( 1u << 1 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_T0D   ( 1u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_75MV   ( 0x0u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_105MV   ( 0x1u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_150MV   ( 0x2u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_205MV   ( 0x3u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_290MV   ( 0x4u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_400MV   ( 0x5u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_560MV   ( 0x6u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_800MV   ( 0x7u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_25MV   ( 0x8u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_33MV   ( 0x9u << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_47MV   ( 0xAu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_64MV   ( 0xBu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_90MV   ( 0xCu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_125MV   ( 0xDu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_175MV   ( 0xEu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_250MV   ( 0xFu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_MASK   ( 0xFu << 0 )
 
#define NFC5_FIELD_THLD_DEACT_RFE_SHIFT   ( 0u )
 
#define NFC5_REGULATOR_CTRL_REG_S   ( 1u << 7 )
 
#define NFC5_REGULATOR_CTRL_REGE_3   ( 1u << 6 )
 
#define NFC5_REGULATOR_CTRL_REGE_2   ( 1u << 5 )
 
#define NFC5_REGULATOR_CTRL_REGE_1   ( 1u << 4 )
 
#define NFC5_REGULATOR_CTRL_REGE_0   ( 1u << 3 )
 
#define NFC5_REGULATOR_CTRL_REGE_MASK   ( 0xFu << 3 )
 
#define NFC5_REGULATOR_CTRL_REGE_SHIFT   ( 3u )
 
#define NFC5_REGULATOR_CTRL_MPSV2   ( 2u << 2 )
 
#define NFC5_REGULATOR_CTRL_MPSV1   ( 1u << 1 )
 
#define NFC5_REGULATOR_CTRL_MPSV0   ( 1u << 0 )
 
#define NFC5_REGULATOR_CTRL_MPSV_VDD   ( 0u )
 
#define NFC5_REGULATOR_CTRL_MPSV_VDD_A   ( 1u )
 
#define NFC5_REGULATOR_CTRL_MPSV_VDD_D   ( 2u )
 
#define NFC5_REGULATOR_CTRL_MPSV_VDD_RF   ( 3u )
 
#define NFC5_REGULATOR_CTRL_MPSV_VDD_AM   ( 4u )
 
#define NFC5_REGULATOR_CTRL_RFU   ( 5u )
 
#define NFC5_REGULATOR_CTRL_RFU1   ( 6u )
 
#define NFC5_REGULATOR_CTRL_RFU2   ( 7u )
 
#define NFC5_REGULATOR_CTRL_MPSV_MASK   ( 7u )
 
#define NFC5_REGULATOR_CTRL_MPSV_SHIFT   ( 0u )
 
#define NFC5_DEVICE_ADDRESS   0x50
 NFC 5 device address setting. More...
 
#define NFC5_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
 Data sample selection. More...
 
#define NFC5_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE
 

Detailed Description

Settings for registers of NFC 5 Click driver.

Macro Definition Documentation

◆ NFC5_1FC_IN_4096FC

#define NFC5_1FC_IN_4096FC   4096u

NFC 5 Click RFAL macros.

Specified macros for RFAL library. Number of 1/fc cycles in one 4096/fc.

◆ NFC5_1FC_IN_512FC

#define NFC5_1FC_IN_512FC   512u

Number of 1/fc cycles in one 512/fc.

◆ NFC5_1FC_IN_64FC

#define NFC5_1FC_IN_64FC   64u

Number of 1/fc cycles in one 64/fc.

◆ NFC5_1FC_IN_8FC

#define NFC5_1FC_IN_8FC   8u

Number of 1/fc cycles in one 8/fc.

◆ NFC5_1MS_IN_1FC

#define NFC5_1MS_IN_1FC   13560u

Number of 1/fc cycles in 1ms.

◆ NFC5_ANALOG_CONFIG_ANTICOL

#define NFC5_ANALOG_CONFIG_ANTICOL   0x0003

Anticollision setting in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_BITRATE_106

#define NFC5_ANALOG_CONFIG_BITRATE_106   0x0010

106kbits/s settings in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_BITRATE_COMMON

#define NFC5_ANALOG_CONFIG_BITRATE_COMMON   0x0000

Common settings for all bit rates in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_BITRATE_MASK

#define NFC5_ANALOG_CONFIG_BITRATE_MASK   0x00F0

Mask bits for Bit rate in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_BITRATE_SHIFT

#define NFC5_ANALOG_CONFIG_BITRATE_SHIFT   4

Shift value for Technology in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_CHIP_DEINIT

#define NFC5_ANALOG_CONFIG_CHIP_DEINIT   0x0001

Chip-Specific event: Deinitialize.

◆ NFC5_ANALOG_CONFIG_CHIP_FIELD_OFF

#define NFC5_ANALOG_CONFIG_CHIP_FIELD_OFF   0x0003

Chip-Specific event: Field Off.

◆ NFC5_ANALOG_CONFIG_CHIP_FIELD_ON

#define NFC5_ANALOG_CONFIG_CHIP_FIELD_ON   0x0002

Chip-Specific event: Field On.

◆ NFC5_ANALOG_CONFIG_CHIP_INIT

#define NFC5_ANALOG_CONFIG_CHIP_INIT   0x0000

Chip-Specific event: Startup;Reset;Initialize.

◆ NFC5_ANALOG_CONFIG_CHIP_POLL_COMMON

#define NFC5_ANALOG_CONFIG_CHIP_POLL_COMMON   0x0008

Chip-Specific event: Poll common.

◆ NFC5_ANALOG_CONFIG_DIRECTION_MASK

#define NFC5_ANALOG_CONFIG_DIRECTION_MASK   0x000F

Mask bits for Direction in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_DIRECTION_SHIFT

#define NFC5_ANALOG_CONFIG_DIRECTION_SHIFT   0

Shift value for Direction in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_LISTEN

#define NFC5_ANALOG_CONFIG_LISTEN   0x8000

Listen Mode bit setting in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_LUT_NOT_FOUND

#define NFC5_ANALOG_CONFIG_LUT_NOT_FOUND   0xFF

Index value indicating no Configuration IDs found.

◆ NFC5_ANALOG_CONFIG_POLL

#define NFC5_ANALOG_CONFIG_POLL   0x0000

Poll Mode bit setting in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_RX

#define NFC5_ANALOG_CONFIG_RX   0x0002

Reception bit setting in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_TECH_CHIP

#define NFC5_ANALOG_CONFIG_TECH_CHIP   0x0000

Chip-Specific bit setting in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_TECH_NFCA

#define NFC5_ANALOG_CONFIG_TECH_NFCA   0x0100

NFC-A Technology bits setting in Analog Configuration ID.

◆ NFC5_ANALOG_CONFIG_TX

#define NFC5_ANALOG_CONFIG_TX   0x0001

Transmission bit setting in Analog Configuration ID.

◆ NFC5_AUX_DIS_CORR

#define NFC5_AUX_DIS_CORR   ( 1u << 2 )

◆ NFC5_AUX_DIS_CORR_COHERENT

#define NFC5_AUX_DIS_CORR_COHERENT   ( 1u << 2 )

◆ NFC5_AUX_DIS_CORR_CORRELATOR

#define NFC5_AUX_DIS_CORR_CORRELATOR   ( 0u << 2 )

◆ NFC5_AUX_DISPLAY_A_CHA

#define NFC5_AUX_DISPLAY_A_CHA   ( 1u << 7 )

◆ NFC5_AUX_DISPLAY_EFD_O

#define NFC5_AUX_DISPLAY_EFD_O   ( 1u << 6 )

◆ NFC5_AUX_DISPLAY_EN_AC

#define NFC5_AUX_DISPLAY_EN_AC   ( 1u << 0 )

◆ NFC5_AUX_DISPLAY_EN_PEER

#define NFC5_AUX_DISPLAY_EN_PEER   ( 1u << 1 )

◆ NFC5_AUX_DISPLAY_OSC_OK

#define NFC5_AUX_DISPLAY_OSC_OK   ( 1u << 4 )

◆ NFC5_AUX_DISPLAY_RX_ACT

#define NFC5_AUX_DISPLAY_RX_ACT   ( 1u << 2 )

◆ NFC5_AUX_DISPLAY_RX_ON

#define NFC5_AUX_DISPLAY_RX_ON   ( 1u << 3 )

◆ NFC5_AUX_DISPLAY_TX_ON

#define NFC5_AUX_DISPLAY_TX_ON   ( 1u << 5 )

◆ NFC5_AUX_MFAZ_CL90

#define NFC5_AUX_MFAZ_CL90   ( 1u << 3 )

◆ NFC5_AUX_MOD_DIS_REG_AM

#define NFC5_AUX_MOD_DIS_REG_AM   ( 1u << 7 )

◆ NFC5_AUX_MOD_LM_DRI

#define NFC5_AUX_MOD_LM_DRI   ( 1u << 4 )

◆ NFC5_AUX_MOD_LM_EXT

#define NFC5_AUX_MOD_LM_EXT   ( 1u << 5 )

◆ NFC5_AUX_MOD_LM_EXT_POL

#define NFC5_AUX_MOD_LM_EXT_POL   ( 1u << 6 )

◆ NFC5_AUX_MOD_RES_AM

#define NFC5_AUX_MOD_RES_AM   ( 1u << 3 )

◆ NFC5_AUX_MOD_RFU0

#define NFC5_AUX_MOD_RFU0   ( 1u << 0 )

◆ NFC5_AUX_MOD_RFU1

#define NFC5_AUX_MOD_RFU1   ( 1u << 1 )

◆ NFC5_AUX_MOD_RFU2

#define NFC5_AUX_MOD_RFU2   ( 1u << 2 )

◆ NFC5_AUX_NFC_ID0

#define NFC5_AUX_NFC_ID0   ( 1u << 4 )

◆ NFC5_AUX_NFC_ID1

#define NFC5_AUX_NFC_ID1   ( 1u << 5 )

◆ NFC5_AUX_NFC_ID_4BYTES

#define NFC5_AUX_NFC_ID_4BYTES   ( 0u << 4 )

◆ NFC5_AUX_NFC_ID_7BYTES

#define NFC5_AUX_NFC_ID_7BYTES   ( 1u << 4 )

◆ NFC5_AUX_NFC_ID_MASK

#define NFC5_AUX_NFC_ID_MASK   ( 3u << 4 )

◆ NFC5_AUX_NFC_ID_SHIFT

#define NFC5_AUX_NFC_ID_SHIFT   ( 4u )

◆ NFC5_AUX_NFC_N0

#define NFC5_AUX_NFC_N0   ( 1u << 0 )

◆ NFC5_AUX_NFC_N1

#define NFC5_AUX_NFC_N1   ( 1u << 1 )

◆ NFC5_AUX_NFC_N_MASK

#define NFC5_AUX_NFC_N_MASK   ( 3u << 0 )

◆ NFC5_AUX_NFC_N_SHIFT

#define NFC5_AUX_NFC_N_SHIFT   ( 0u )

◆ NFC5_AUX_NO_CRC_RX

#define NFC5_AUX_NO_CRC_RX   ( 1u << 7 )

◆ NFC5_AUX_RFU

#define NFC5_AUX_RFU   ( 1u << 6 )

◆ NFC5_BIT_RATE_RXRATE_106

#define NFC5_BIT_RATE_RXRATE_106   ( 0x0u << 0 )

◆ NFC5_BIT_RATE_RXRATE_212

#define NFC5_BIT_RATE_RXRATE_212   ( 0x1u << 0 )

◆ NFC5_BIT_RATE_RXRATE_424

#define NFC5_BIT_RATE_RXRATE_424   ( 0x2u << 0 )

◆ NFC5_BIT_RATE_RXRATE_848

#define NFC5_BIT_RATE_RXRATE_848   ( 0x3u << 0 )

◆ NFC5_BIT_RATE_RXRATE_MASK

#define NFC5_BIT_RATE_RXRATE_MASK   ( 0x3u << 0 )

◆ NFC5_BIT_RATE_RXRATE_SHIFT

#define NFC5_BIT_RATE_RXRATE_SHIFT   ( 0u )

◆ NFC5_BIT_RATE_TXRATE_106

#define NFC5_BIT_RATE_TXRATE_106   ( 0x0u << 4 )

◆ NFC5_BIT_RATE_TXRATE_212

#define NFC5_BIT_RATE_TXRATE_212   ( 0x1u << 4 )

◆ NFC5_BIT_RATE_TXRATE_424

#define NFC5_BIT_RATE_TXRATE_424   ( 0x2u << 4 )

◆ NFC5_BIT_RATE_TXRATE_848

#define NFC5_BIT_RATE_TXRATE_848   ( 0x3u << 4 )

◆ NFC5_BIT_RATE_TXRATE_MASK

#define NFC5_BIT_RATE_TXRATE_MASK   ( 0x3u << 4 )

◆ NFC5_BIT_RATE_TXRATE_SHIFT

#define NFC5_BIT_RATE_TXRATE_SHIFT   ( 4u )

◆ NFC5_BITS_IN_BYTE

#define NFC5_BITS_IN_BYTE   8u

Number of bits in one byte.

◆ NFC5_COLLISION_STATUS_C_BIT0

#define NFC5_COLLISION_STATUS_C_BIT0   ( 1u << 1 )

◆ NFC5_COLLISION_STATUS_C_BIT1

#define NFC5_COLLISION_STATUS_C_BIT1   ( 1u << 2 )

◆ NFC5_COLLISION_STATUS_C_BIT2

#define NFC5_COLLISION_STATUS_C_BIT2   ( 1u << 3 )

◆ NFC5_COLLISION_STATUS_C_BIT_MASK

#define NFC5_COLLISION_STATUS_C_BIT_MASK   ( 3u << 1 )

◆ NFC5_COLLISION_STATUS_C_BIT_SHIFT

#define NFC5_COLLISION_STATUS_C_BIT_SHIFT   ( 1u )

◆ NFC5_COLLISION_STATUS_C_BYTE0

#define NFC5_COLLISION_STATUS_C_BYTE0   ( 1u << 4 )

◆ NFC5_COLLISION_STATUS_C_BYTE1

#define NFC5_COLLISION_STATUS_C_BYTE1   ( 1u << 5 )

◆ NFC5_COLLISION_STATUS_C_BYTE2

#define NFC5_COLLISION_STATUS_C_BYTE2   ( 1u << 6 )

◆ NFC5_COLLISION_STATUS_C_BYTE3

#define NFC5_COLLISION_STATUS_C_BYTE3   ( 1u << 7 )

◆ NFC5_COLLISION_STATUS_C_BYTE_MASK

#define NFC5_COLLISION_STATUS_C_BYTE_MASK   ( 0xFu << 4 )

◆ NFC5_COLLISION_STATUS_C_BYTE_SHIFT

#define NFC5_COLLISION_STATUS_C_BYTE_SHIFT   ( 4u )

◆ NFC5_COLLISION_STATUS_C_PB

#define NFC5_COLLISION_STATUS_C_PB   ( 1u << 0 )

◆ NFC5_CORR_CFG_1_CORR_S0

#define NFC5_CORR_CFG_1_CORR_S0   ( 1u << 0 )

◆ NFC5_CORR_CFG_1_CORR_S1

#define NFC5_CORR_CFG_1_CORR_S1   ( 1u << 1 )

◆ NFC5_CORR_CFG_1_CORR_S2

#define NFC5_CORR_CFG_1_CORR_S2   ( 1u << 2 )

◆ NFC5_CORR_CFG_1_CORR_S3

#define NFC5_CORR_CFG_1_CORR_S3   ( 1u << 3 )

◆ NFC5_CORR_CFG_1_CORR_S4

#define NFC5_CORR_CFG_1_CORR_S4   ( 1u << 4 )

◆ NFC5_CORR_CFG_1_CORR_S5

#define NFC5_CORR_CFG_1_CORR_S5   ( 1u << 5 )

◆ NFC5_CORR_CFG_1_CORR_S6

#define NFC5_CORR_CFG_1_CORR_S6   ( 1u << 6 )

◆ NFC5_CORR_CFG_1_CORR_S7

#define NFC5_CORR_CFG_1_CORR_S7   ( 1u << 7 )

◆ NFC5_CRC_LEN

#define NFC5_CRC_LEN   2u

RF CRC LEN. Converts the given t from 1/fc to 64/fc.

◆ NFC5_DEVICE_ADDRESS

#define NFC5_DEVICE_ADDRESS   0x50

NFC 5 device address setting.

Specified setting for device slave address selection of NFC 5 Click driver.

◆ NFC5_EMD_SUP_CFG_EMD_EMV

#define NFC5_EMD_SUP_CFG_EMD_EMV   ( 1u << 7 )

◆ NFC5_EMD_SUP_CFG_EMD_EMV_OFF

#define NFC5_EMD_SUP_CFG_EMD_EMV_OFF   ( 0u << 7 )

◆ NFC5_EMD_SUP_CFG_EMD_EMV_ON

#define NFC5_EMD_SUP_CFG_EMD_EMV_ON   ( 1u << 7 )

◆ NFC5_EMD_SUP_CFG_EMD_THLD0

#define NFC5_EMD_SUP_CFG_EMD_THLD0   ( 1u << 0 )

◆ NFC5_EMD_SUP_CFG_EMD_THLD1

#define NFC5_EMD_SUP_CFG_EMD_THLD1   ( 1u << 1 )

◆ NFC5_EMD_SUP_CFG_EMD_THLD2

#define NFC5_EMD_SUP_CFG_EMD_THLD2   ( 1u << 2 )

◆ NFC5_EMD_SUP_CFG_EMD_THLD3

#define NFC5_EMD_SUP_CFG_EMD_THLD3   ( 1u << 3 )

◆ NFC5_EMD_SUP_CFG_EMD_THLD_MASK

#define NFC5_EMD_SUP_CFG_EMD_THLD_MASK   ( 0xFu << 0 )

◆ NFC5_EMD_SUP_CFG_EMD_THLD_SHIFT

#define NFC5_EMD_SUP_CFG_EMD_THLD_SHIFT   ( 0u )

◆ NFC5_EMD_SUP_CFG_RFU0

#define NFC5_EMD_SUP_CFG_RFU0   ( 1u << 4 )

◆ NFC5_EMD_SUP_CFG_RFU1

#define NFC5_EMD_SUP_CFG_RFU1   ( 1u << 5 )

◆ NFC5_EMD_SUP_CFG_RX_START_EMV

#define NFC5_EMD_SUP_CFG_RX_START_EMV   ( 1u << 6 )

◆ NFC5_EMD_SUP_CFG_RX_START_EMV_OFF

#define NFC5_EMD_SUP_CFG_RX_START_EMV_OFF   ( 0u << 6 )

◆ NFC5_EMD_SUP_CFG_RX_START_EMV_ON

#define NFC5_EMD_SUP_CFG_RX_START_EMV_ON   ( 1u << 6 )

◆ NFC5_FIELD_THLD_ACT_RFE_105MV

#define NFC5_FIELD_THLD_ACT_RFE_105MV   ( 0x1u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_125MV

#define NFC5_FIELD_THLD_ACT_RFE_125MV   ( 0xDu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_150MV

#define NFC5_FIELD_THLD_ACT_RFE_150MV   ( 0x2u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_175MV

#define NFC5_FIELD_THLD_ACT_RFE_175MV   ( 0xEu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_205MV

#define NFC5_FIELD_THLD_ACT_RFE_205MV   ( 0x3u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_250MV

#define NFC5_FIELD_THLD_ACT_RFE_250MV   ( 0xFu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_25MV

#define NFC5_FIELD_THLD_ACT_RFE_25MV   ( 0x8u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_290MV

#define NFC5_FIELD_THLD_ACT_RFE_290MV   ( 0x4u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_33MV

#define NFC5_FIELD_THLD_ACT_RFE_33MV   ( 0x9u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_400MV

#define NFC5_FIELD_THLD_ACT_RFE_400MV   ( 0x5u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_47MV

#define NFC5_FIELD_THLD_ACT_RFE_47MV   ( 0xAu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_560MV

#define NFC5_FIELD_THLD_ACT_RFE_560MV   ( 0x6u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_64MV

#define NFC5_FIELD_THLD_ACT_RFE_64MV   ( 0xBu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_75MV

#define NFC5_FIELD_THLD_ACT_RFE_75MV   ( 0x0u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_800MV

#define NFC5_FIELD_THLD_ACT_RFE_800MV   ( 0x7u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_90MV

#define NFC5_FIELD_THLD_ACT_RFE_90MV   ( 0xCu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_MASK

#define NFC5_FIELD_THLD_ACT_RFE_MASK   ( 0xFu << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_SHIFT

#define NFC5_FIELD_THLD_ACT_RFE_SHIFT   ( 0u )

◆ NFC5_FIELD_THLD_ACT_RFE_T0A

#define NFC5_FIELD_THLD_ACT_RFE_T0A   ( 1u << 0 )

◆ NFC5_FIELD_THLD_ACT_RFE_T1A

#define NFC5_FIELD_THLD_ACT_RFE_T1A   ( 1u << 1 )

◆ NFC5_FIELD_THLD_ACT_RFE_T2A

#define NFC5_FIELD_THLD_ACT_RFE_T2A   ( 1u << 2 )

◆ NFC5_FIELD_THLD_ACT_RFE_T3A

#define NFC5_FIELD_THLD_ACT_RFE_T3A   ( 1u << 3 )

◆ NFC5_FIELD_THLD_ACT_TRG_105MV

#define NFC5_FIELD_THLD_ACT_TRG_105MV   ( 0x1u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_150MV

#define NFC5_FIELD_THLD_ACT_TRG_150MV   ( 0x2u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_205MV

#define NFC5_FIELD_THLD_ACT_TRG_205MV   ( 0x3u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_290MV

#define NFC5_FIELD_THLD_ACT_TRG_290MV   ( 0x4u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_400MV

#define NFC5_FIELD_THLD_ACT_TRG_400MV   ( 0x5u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_560MV

#define NFC5_FIELD_THLD_ACT_TRG_560MV   ( 0x6u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_75MV

#define NFC5_FIELD_THLD_ACT_TRG_75MV   ( 0x0u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_800MV

#define NFC5_FIELD_THLD_ACT_TRG_800MV   ( 0x7u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_L0A

#define NFC5_FIELD_THLD_ACT_TRG_L0A   ( 1u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_L1A

#define NFC5_FIELD_THLD_ACT_TRG_L1A   ( 1u << 5 )

◆ NFC5_FIELD_THLD_ACT_TRG_L2A

#define NFC5_FIELD_THLD_ACT_TRG_L2A   ( 1u << 6 )

◆ NFC5_FIELD_THLD_ACT_TRG_MASK

#define NFC5_FIELD_THLD_ACT_TRG_MASK   ( 7u << 4 )

◆ NFC5_FIELD_THLD_ACT_TRG_SHIFT

#define NFC5_FIELD_THLD_ACT_TRG_SHIFT   ( 4u )

◆ NFC5_FIELD_THLD_DEACT_RFE_105MV

#define NFC5_FIELD_THLD_DEACT_RFE_105MV   ( 0x1u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_125MV

#define NFC5_FIELD_THLD_DEACT_RFE_125MV   ( 0xDu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_150MV

#define NFC5_FIELD_THLD_DEACT_RFE_150MV   ( 0x2u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_175MV

#define NFC5_FIELD_THLD_DEACT_RFE_175MV   ( 0xEu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_205MV

#define NFC5_FIELD_THLD_DEACT_RFE_205MV   ( 0x3u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_250MV

#define NFC5_FIELD_THLD_DEACT_RFE_250MV   ( 0xFu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_25MV

#define NFC5_FIELD_THLD_DEACT_RFE_25MV   ( 0x8u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_290MV

#define NFC5_FIELD_THLD_DEACT_RFE_290MV   ( 0x4u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_33MV

#define NFC5_FIELD_THLD_DEACT_RFE_33MV   ( 0x9u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_400MV

#define NFC5_FIELD_THLD_DEACT_RFE_400MV   ( 0x5u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_47MV

#define NFC5_FIELD_THLD_DEACT_RFE_47MV   ( 0xAu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_560MV

#define NFC5_FIELD_THLD_DEACT_RFE_560MV   ( 0x6u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_64MV

#define NFC5_FIELD_THLD_DEACT_RFE_64MV   ( 0xBu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_75MV

#define NFC5_FIELD_THLD_DEACT_RFE_75MV   ( 0x0u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_800MV

#define NFC5_FIELD_THLD_DEACT_RFE_800MV   ( 0x7u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_90MV

#define NFC5_FIELD_THLD_DEACT_RFE_90MV   ( 0xCu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_MASK

#define NFC5_FIELD_THLD_DEACT_RFE_MASK   ( 0xFu << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_SHIFT

#define NFC5_FIELD_THLD_DEACT_RFE_SHIFT   ( 0u )

◆ NFC5_FIELD_THLD_DEACT_RFE_T0D

#define NFC5_FIELD_THLD_DEACT_RFE_T0D   ( 1u << 0 )

◆ NFC5_FIELD_THLD_DEACT_RFE_T1D

#define NFC5_FIELD_THLD_DEACT_RFE_T1D   ( 1u << 1 )

◆ NFC5_FIELD_THLD_DEACT_RFE_T2D

#define NFC5_FIELD_THLD_DEACT_RFE_T2D   ( 1u << 2 )

◆ NFC5_FIELD_THLD_DEACT_RFE_T3D

#define NFC5_FIELD_THLD_DEACT_RFE_T3D   ( 1u << 3 )

◆ NFC5_FIELD_THLD_DEACT_TRG_105MV

#define NFC5_FIELD_THLD_DEACT_TRG_105MV   ( 0x1u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_150MV

#define NFC5_FIELD_THLD_DEACT_TRG_150MV   ( 0x2u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_205MV

#define NFC5_FIELD_THLD_DEACT_TRG_205MV   ( 0x3u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_290MV

#define NFC5_FIELD_THLD_DEACT_TRG_290MV   ( 0x4u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_400MV

#define NFC5_FIELD_THLD_DEACT_TRG_400MV   ( 0x5u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_560MV

#define NFC5_FIELD_THLD_DEACT_TRG_560MV   ( 0x6u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_75MV

#define NFC5_FIELD_THLD_DEACT_TRG_75MV   ( 0x0u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_800MV

#define NFC5_FIELD_THLD_DEACT_TRG_800MV   ( 0x7u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_L0D

#define NFC5_FIELD_THLD_DEACT_TRG_L0D   ( 1u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_L1D

#define NFC5_FIELD_THLD_DEACT_TRG_L1D   ( 1u << 5 )

◆ NFC5_FIELD_THLD_DEACT_TRG_L2D

#define NFC5_FIELD_THLD_DEACT_TRG_L2D   ( 1u << 6 )

◆ NFC5_FIELD_THLD_DEACT_TRG_MASK

#define NFC5_FIELD_THLD_DEACT_TRG_MASK   ( 7u << 4 )

◆ NFC5_FIELD_THLD_DEACT_TRG_SHIFT

#define NFC5_FIELD_THLD_DEACT_TRG_SHIFT   ( 4u )

◆ NFC5_FIFO_DEPTH

#define NFC5_FIFO_DEPTH   512u

NFC 5 Click NFC FIFO macros.

Specified macros for NFC FIFO. Depth of FIFO.

◆ NFC5_FIFO_IN_WL

#define NFC5_FIFO_IN_WL   200u

Number of bytes in the FIFO when WL interrupt occurs while Tx.

◆ NFC5_FIFO_OUT_WL

#define NFC5_FIFO_OUT_WL   ( NFC5_FIFO_DEPTH - NFC5_FIFO_IN_WL )

Number of bytes sent/out of the FIFO when WL interrupt occurs while Tx.

◆ NFC5_FIFO_STATUS2_FIFO_B8

#define NFC5_FIFO_STATUS2_FIFO_B8   ( 1u << 6 )

◆ NFC5_FIFO_STATUS2_FIFO_B9

#define NFC5_FIFO_STATUS2_FIFO_B9   ( 1u << 7 )

◆ NFC5_FIFO_STATUS2_FIFO_B_MASK

#define NFC5_FIFO_STATUS2_FIFO_B_MASK   ( 3u << 6 )

◆ NFC5_FIFO_STATUS2_FIFO_B_SHIFT

#define NFC5_FIFO_STATUS2_FIFO_B_SHIFT   ( 6u )

◆ NFC5_FIFO_STATUS2_FIFO_LB0

#define NFC5_FIFO_STATUS2_FIFO_LB0   ( 1u << 1 )

◆ NFC5_FIFO_STATUS2_FIFO_LB1

#define NFC5_FIFO_STATUS2_FIFO_LB1   ( 1u << 2 )

◆ NFC5_FIFO_STATUS2_FIFO_LB2

#define NFC5_FIFO_STATUS2_FIFO_LB2   ( 1u << 3 )

◆ NFC5_FIFO_STATUS2_FIFO_LB_MASK

#define NFC5_FIFO_STATUS2_FIFO_LB_MASK   ( 7u << 1 )

◆ NFC5_FIFO_STATUS2_FIFO_LB_SHIFT

#define NFC5_FIFO_STATUS2_FIFO_LB_SHIFT   ( 1u )

◆ NFC5_FIFO_STATUS2_FIFO_OVR

#define NFC5_FIFO_STATUS2_FIFO_OVR   ( 1u << 4 )

◆ NFC5_FIFO_STATUS2_FIFO_UNF

#define NFC5_FIFO_STATUS2_FIFO_UNF   ( 1u << 5 )

◆ NFC5_FIFO_STATUS2_NP_LB

#define NFC5_FIFO_STATUS2_NP_LB   ( 1u << 0 )

◆ NFC5_FIFO_STATUS_INVALID

#define NFC5_FIFO_STATUS_INVALID   0xFFu

Value indicating that the local FIFO status in invalid|cleared.

◆ NFC5_FIFO_STATUS_REG1

#define NFC5_FIFO_STATUS_REG1   0u

Location of FIFO status register 1 in local copy.

◆ NFC5_FIFO_STATUS_REG2

#define NFC5_FIFO_STATUS_REG2   1u

Location of FIFO status register 2 in local copy.

◆ NFC5_FWT_A_ADJUSTMENT

#define NFC5_FWT_A_ADJUSTMENT   ( 512u + 64u )

Max NRT steps in 1fc (0xFFFF steps of 4096/FC => 0xFFFF * 302us = 19.8s ).

◆ NFC5_FWT_ADJUSTMENT

#define NFC5_FWT_ADJUSTMENT   64u

FWT ISO14443A adjustment: 512 - 4bit length, 64 - Half a bit duration due to ST25R3918 Coherent receiver ( 1 / FC ).

◆ NFC5_FWT_NONE

#define NFC5_FWT_NONE   0xFFFFFFFFul

FWT adjustment: 64 : NRT jitter between TXE and NRT start.

◆ NFC5_IC_REVISION_CODE_MASK

#define NFC5_IC_REVISION_CODE_MASK   0x07

◆ NFC5_IC_TYPE_CODE

#define NFC5_IC_TYPE_CODE   0x05

NFC 5 IC Identity default value.

Specified value for IC Identity of NFC 5 Click driver.

◆ NFC5_IO_CFG_1_I2C_THD0

#define NFC5_IO_CFG_1_I2C_THD0   ( 1u << 4 )

◆ NFC5_IO_CFG_1_I2C_THD1

#define NFC5_IO_CFG_1_I2C_THD1   ( 1u << 5 )

◆ NFC5_IO_CFG_1_I2C_THD_MASK

#define NFC5_IO_CFG_1_I2C_THD_MASK   ( 3u << 4 )

◆ NFC5_IO_CFG_1_I2C_THD_SHIFT

#define NFC5_IO_CFG_1_I2C_THD_SHIFT   ( 4u )

◆ NFC5_IO_CFG_1_LF_CLK_OFF

#define NFC5_IO_CFG_1_LF_CLK_OFF   ( 1u << 0 )

◆ NFC5_IO_CFG_1_LF_CLK_OFF_OFF

#define NFC5_IO_CFG_1_LF_CLK_OFF_OFF   ( 0u << 0 )

◆ NFC5_IO_CFG_1_LF_CLK_OFF_ON

#define NFC5_IO_CFG_1_LF_CLK_OFF_ON   ( 1u << 0 )

◆ NFC5_IO_CFG_1_OUT_CL0

#define NFC5_IO_CFG_1_OUT_CL0   ( 1u << 1 )

◆ NFC5_IO_CFG_1_OUT_CL1

#define NFC5_IO_CFG_1_OUT_CL1   ( 1u << 2 )

◆ NFC5_IO_CFG_1_OUT_CL_13_56MHZ

#define NFC5_IO_CFG_1_OUT_CL_13_56MHZ   ( 2u << 1 )

◆ NFC5_IO_CFG_1_OUT_CL_3_39MHZ

#define NFC5_IO_CFG_1_OUT_CL_3_39MHZ   ( 0u << 1 )

◆ NFC5_IO_CFG_1_OUT_CL_4_78MHZ

#define NFC5_IO_CFG_1_OUT_CL_4_78MHZ   ( 1u << 1 )

◆ NFC5_IO_CFG_1_OUT_CL_DISABLED

#define NFC5_IO_CFG_1_OUT_CL_DISABLED   ( 3u << 1 )

◆ NFC5_IO_CFG_1_OUT_CL_MASK

#define NFC5_IO_CFG_1_OUT_CL_MASK   ( 3u << 1 )

◆ NFC5_IO_CFG_1_OUT_CL_SHIFT

#define NFC5_IO_CFG_1_OUT_CL_SHIFT   ( 1u )

◆ NFC5_IO_CFG_1_RFO2

#define NFC5_IO_CFG_1_RFO2   ( 1u << 6 )

◆ NFC5_IO_CFG_1_RFU

#define NFC5_IO_CFG_1_RFU   ( 1u << 3 )

◆ NFC5_IO_CFG_1_SINGLE

#define NFC5_IO_CFG_1_SINGLE   ( 1u << 7 )

NFC 5 Click register bits value.

Specified values of registers bits.

◆ NFC5_IO_CFG_2_AAT_EN

#define NFC5_IO_CFG_2_AAT_EN   ( 1u << 5 )

◆ NFC5_IO_CFG_2_IO_DRV_LVL

#define NFC5_IO_CFG_2_IO_DRV_LVL   ( 1u << 2 )

◆ NFC5_IO_CFG_2_MISO_PD1

#define NFC5_IO_CFG_2_MISO_PD1   ( 1u << 3 )

◆ NFC5_IO_CFG_2_MISO_PD2

#define NFC5_IO_CFG_2_MISO_PD2   ( 1u << 4 )

◆ NFC5_IO_CFG_2_SLOW_UP

#define NFC5_IO_CFG_2_SLOW_UP   ( 1u << 0 )

◆ NFC5_IO_CFG_2_SUP3V

#define NFC5_IO_CFG_2_SUP3V   ( 1u << 7 )

◆ NFC5_IO_CFG_2_SUP3V_3V

#define NFC5_IO_CFG_2_SUP3V_3V   ( 1u << 7 )

◆ NFC5_IO_CFG_2_SUP3V_5V

#define NFC5_IO_CFG_2_SUP3V_5V   ( 0u << 7 )

◆ NFC5_IO_CFG_2_VSPD_OFF

#define NFC5_IO_CFG_2_VSPD_OFF   ( 1u << 6 )

◆ NFC5_IRQ_MASK_ALL

#define NFC5_IRQ_MASK_ALL   0xFFFFFFFFul

NFC 5 IRQ masks.

Specified masks for IRQ of NFC 5 Click driver. All NFC 5 interrupt sources.

◆ NFC5_IRQ_MASK_APON

#define NFC5_IRQ_MASK_APON   0x20000000ul

NFC 5 Anticollision done and Field On interrupt.

◆ NFC5_IRQ_MASK_CAC

#define NFC5_IRQ_MASK_CAC   0x00000400ul

NFC 5 collision during RF collision avoidance interrupt.

◆ NFC5_IRQ_MASK_CAT

#define NFC5_IRQ_MASK_CAT   0x00000200ul

NFC 5 minimum guard time expired interrupt.

◆ NFC5_IRQ_MASK_COL

#define NFC5_IRQ_MASK_COL   0x00000004ul

NFC 5 bit collision interrupt.

◆ NFC5_IRQ_MASK_CRC

#define NFC5_IRQ_MASK_CRC   0x00800000ul

NFC 5 CRC error interrupt.

◆ NFC5_IRQ_MASK_DCT

#define NFC5_IRQ_MASK_DCT   0x00008000ul

NFC 5 termination of direct command interrupt.

◆ NFC5_IRQ_MASK_EOF

#define NFC5_IRQ_MASK_EOF   0x00000800ul

NFC 5 external field off interrupt.

◆ NFC5_IRQ_MASK_EON

#define NFC5_IRQ_MASK_EON   0x00001000ul

NFC 5 external field on interrupt.

◆ NFC5_IRQ_MASK_ERR1

#define NFC5_IRQ_MASK_ERR1   0x00100000ul

NFC 5 hard framing error interrupt.

◆ NFC5_IRQ_MASK_ERR2

#define NFC5_IRQ_MASK_ERR2   0x00200000ul

NFC 5 soft framing error interrupt.

◆ NFC5_IRQ_MASK_FWL

#define NFC5_IRQ_MASK_FWL   0x00000040ul

NFC 5 FIFO water level interrupt.

◆ NFC5_IRQ_MASK_GPE

#define NFC5_IRQ_MASK_GPE   0x00002000ul

NFC 5 general purpose timer expired interrupt.

◆ NFC5_IRQ_MASK_NFCT

#define NFC5_IRQ_MASK_NFCT   0x00000100ul

NFC 5 initiator bit rate recognised interrupt.

◆ NFC5_IRQ_MASK_NONE

#define NFC5_IRQ_MASK_NONE   0x00000000ul

No NFC 5 interrupt source.

◆ NFC5_IRQ_MASK_NRE

#define NFC5_IRQ_MASK_NRE   0x00004000ul

NFC 5 no-response timer expired interrupt.

◆ NFC5_IRQ_MASK_OSC

#define NFC5_IRQ_MASK_OSC   0x00000080ul

NFC 5 oscillator stable interrupt.

◆ NFC5_IRQ_MASK_PAR

#define NFC5_IRQ_MASK_PAR   0x00400000ul

NFC 5 parity error interrupt.

◆ NFC5_IRQ_MASK_PPON2

#define NFC5_IRQ_MASK_PPON2   0x80000000ul

NFC 5 PPON2 Field on waiting Timer interrupt.

◆ NFC5_IRQ_MASK_RFU

#define NFC5_IRQ_MASK_RFU   0x00000001ul

NFC 5 RFU interrupt.

◆ NFC5_IRQ_MASK_RFU2

#define NFC5_IRQ_MASK_RFU2   0x04000000ul

NFC 5 RFU2 interrupt.

◆ NFC5_IRQ_MASK_RX_REST

#define NFC5_IRQ_MASK_RX_REST   0x00000002ul

NFC 5 automatic reception restart interrupt.

◆ NFC5_IRQ_MASK_RXE

#define NFC5_IRQ_MASK_RXE   0x00000010ul

NFC 5 end of receive interrupt.

◆ NFC5_IRQ_MASK_RXE_PTA

#define NFC5_IRQ_MASK_RXE_PTA   0x10000000ul

NFC 5 RXE with an automatic response interrupt.

◆ NFC5_IRQ_MASK_RXS

#define NFC5_IRQ_MASK_RXS   0x00000020ul

NFC 5 start of receive interrupt.

◆ NFC5_IRQ_MASK_SL_WL

#define NFC5_IRQ_MASK_SL_WL   0x40000000ul

NFC 5 Passive target slot number water level interrupt.

◆ NFC5_IRQ_MASK_TXE

#define NFC5_IRQ_MASK_TXE   0x00000008ul

NFC 5 end of transmission interrupt.

◆ NFC5_IRQ_MASK_WAM

#define NFC5_IRQ_MASK_WAM   0x00040000ul

NFC 5 wake-up due to amplitude interrupt.

◆ NFC5_IRQ_MASK_WCAP

#define NFC5_IRQ_MASK_WCAP   0x00010000ul

NFC 5 wake-up due to capacitance measurement.

◆ NFC5_IRQ_MASK_WPH

#define NFC5_IRQ_MASK_WPH   0x00020000ul

NFC 5 wake-up due to phase interrupt.

◆ NFC5_IRQ_MASK_WT

#define NFC5_IRQ_MASK_WT   0x00080000ul

NFC 5 wake-up interrupt.

◆ NFC5_IRQ_MASK_WU_A

#define NFC5_IRQ_MASK_WU_A   0x01000000ul

NFC 5 106kb/s Passive target state interrupt: Active.

◆ NFC5_IRQ_MASK_WU_A_X

#define NFC5_IRQ_MASK_WU_A_X   0x02000000ul

NFC 5 106kb/s Passive target state interrupt: Active.

◆ NFC5_IRQ_MASK_WU_F

#define NFC5_IRQ_MASK_WU_F   0x08000000ul

NFC 5 212/424b/s Passive target interrupt: Active.

◆ NFC5_ISO14443A_NFC_ANTCL

#define NFC5_ISO14443A_NFC_ANTCL   ( 1u << 0 )

◆ NFC5_ISO14443A_NFC_NFC_F0

#define NFC5_ISO14443A_NFC_NFC_F0   ( 1u << 5 )

◆ NFC5_ISO14443A_NFC_NFC_F0_OFF

#define NFC5_ISO14443A_NFC_NFC_F0_OFF   ( 0u << 5 )

◆ NFC5_ISO14443A_NFC_NO_RX_PAR

#define NFC5_ISO14443A_NFC_NO_RX_PAR   ( 1u << 6 )

◆ NFC5_ISO14443A_NFC_NO_RX_PAR_OFF

#define NFC5_ISO14443A_NFC_NO_RX_PAR_OFF   ( 0u << 6 )

◆ NFC5_ISO14443A_NFC_NO_TX_PAR

#define NFC5_ISO14443A_NFC_NO_TX_PAR   ( 1u << 7 )

◆ NFC5_ISO14443A_NFC_NO_TX_PAR_OFF

#define NFC5_ISO14443A_NFC_NO_TX_PAR_OFF   ( 0u << 7 )

◆ NFC5_ISO14443A_NFC_P_LEN0

#define NFC5_ISO14443A_NFC_P_LEN0   ( 1u << 1 )

◆ NFC5_ISO14443A_NFC_P_LEN1

#define NFC5_ISO14443A_NFC_P_LEN1   ( 1u << 2 )

◆ NFC5_ISO14443A_NFC_P_LEN2

#define NFC5_ISO14443A_NFC_P_LEN2   ( 1u << 3 )

◆ NFC5_ISO14443A_NFC_P_LEN3

#define NFC5_ISO14443A_NFC_P_LEN3   ( 1u << 4 )

◆ NFC5_ISO14443A_NFC_P_LEN_MASK

#define NFC5_ISO14443A_NFC_P_LEN_MASK   ( 0xFu << 1 )

◆ NFC5_ISO14443A_NFC_P_LEN_SHIFT

#define NFC5_ISO14443A_NFC_P_LEN_SHIFT   ( 1u )

◆ NFC5_ISO14443A_SDD_RES_LEN

#define NFC5_ISO14443A_SDD_RES_LEN   5u

SDD_RES | Anticollision (UID CLn) length. Default TxRx flags: Tx CRC automatic, Rx CRC removed, NFCIP1 mode off, AGC On, Tx Parity automatic, Rx Parity removed

◆ NFC5_MODE_DIRECT_COMMAND

#define NFC5_MODE_DIRECT_COMMAND   0xC0

◆ NFC5_MODE_FIFO_LOAD

#define NFC5_MODE_FIFO_LOAD   0x80

◆ NFC5_MODE_FIFO_READ

#define NFC5_MODE_FIFO_READ   0x9F

◆ NFC5_MODE_NFC_AR0

#define NFC5_MODE_NFC_AR0   ( 1u << 0 )

◆ NFC5_MODE_NFC_AR1

#define NFC5_MODE_NFC_AR1   ( 1u << 1 )

◆ NFC5_MODE_NFC_AR_AUTO_RX

#define NFC5_MODE_NFC_AR_AUTO_RX   ( 1u << 0 )

◆ NFC5_MODE_NFC_AR_EOF

#define NFC5_MODE_NFC_AR_EOF   ( 2u << 0 )

◆ NFC5_MODE_NFC_AR_MASK

#define NFC5_MODE_NFC_AR_MASK   ( 3u << 0 )

◆ NFC5_MODE_NFC_AR_OFF

#define NFC5_MODE_NFC_AR_OFF   ( 0u << 0 )

◆ NFC5_MODE_NFC_AR_RFU

#define NFC5_MODE_NFC_AR_RFU   ( 3u << 0 )

◆ NFC5_MODE_NFC_AR_SHIFT

#define NFC5_MODE_NFC_AR_SHIFT   ( 0u )

◆ NFC5_MODE_OM0

#define NFC5_MODE_OM0   ( 1u << 3 )

◆ NFC5_MODE_OM1

#define NFC5_MODE_OM1   ( 1u << 4 )

◆ NFC5_MODE_OM2

#define NFC5_MODE_OM2   ( 1u << 5 )

◆ NFC5_MODE_OM3

#define NFC5_MODE_OM3   ( 1u << 6 )

◆ NFC5_MODE_OM_BPSK_STREAM

#define NFC5_MODE_OM_BPSK_STREAM   ( 0xFu << 3 )

◆ NFC5_MODE_OM_FELICA

#define NFC5_MODE_OM_FELICA   ( 0x3u << 3 )

◆ NFC5_MODE_OM_ISO14443A

#define NFC5_MODE_OM_ISO14443A   ( 0x1u << 3 )

◆ NFC5_MODE_OM_ISO14443B

#define NFC5_MODE_OM_ISO14443B   ( 0x2u << 3 )

◆ NFC5_MODE_OM_MASK

#define NFC5_MODE_OM_MASK   ( 0xFu << 3 )

◆ NFC5_MODE_OM_NFC

#define NFC5_MODE_OM_NFC   ( 0x0u << 3 )

◆ NFC5_MODE_OM_SHIFT

#define NFC5_MODE_OM_SHIFT   ( 3u )

◆ NFC5_MODE_OM_SUBCARRIER_STREAM

#define NFC5_MODE_OM_SUBCARRIER_STREAM   ( 0xEu << 3 )

◆ NFC5_MODE_OM_TARG_NFCA

#define NFC5_MODE_OM_TARG_NFCA   ( 0x1u << 3 )

◆ NFC5_MODE_OM_TARG_NFCB

#define NFC5_MODE_OM_TARG_NFCB   ( 0x2u << 3 )

◆ NFC5_MODE_OM_TARG_NFCF

#define NFC5_MODE_OM_TARG_NFCF   ( 0x4u << 3 )

◆ NFC5_MODE_OM_TARG_NFCIP

#define NFC5_MODE_OM_TARG_NFCIP   ( 0x7u << 3 )

◆ NFC5_MODE_OM_TOPAZ

#define NFC5_MODE_OM_TOPAZ   ( 0x4u << 3 )

◆ NFC5_MODE_PT_MEM_LOAD_A_CFG

#define NFC5_MODE_PT_MEM_LOAD_A_CFG   0xA0

◆ NFC5_MODE_PT_MEM_LOAD_F_CFG

#define NFC5_MODE_PT_MEM_LOAD_F_CFG   0xA8

◆ NFC5_MODE_PT_MEM_LOAD_TSN_DATA

#define NFC5_MODE_PT_MEM_LOAD_TSN_DATA   0xAC

◆ NFC5_MODE_PT_MEM_READ

#define NFC5_MODE_PT_MEM_READ   0xBF

◆ NFC5_MODE_REG_READ

#define NFC5_MODE_REG_READ   0x40

◆ NFC5_MODE_REG_WRITE

#define NFC5_MODE_REG_WRITE   0x00

NFC 5 Communication operation mode setting.

Specified setting for communication operation mode of NFC 5 Click driver.

◆ NFC5_MODE_TARG

#define NFC5_MODE_TARG   ( 1u << 7 )

◆ NFC5_MODE_TARG_INIT

#define NFC5_MODE_TARG_INIT   ( 0u << 7 )

◆ NFC5_MODE_TARG_TARG

#define NFC5_MODE_TARG_TARG   ( 1u << 7 )

◆ NFC5_MODE_TR_AM

#define NFC5_MODE_TR_AM   ( 1u << 2 )

◆ NFC5_MODE_TR_AM_AM

#define NFC5_MODE_TR_AM_AM   ( 1u << 2 )

◆ NFC5_MODE_TR_AM_OOK

#define NFC5_MODE_TR_AM_OOK   ( 0u << 2 )

◆ NFC5_MRT_MIN_1FC

#define NFC5_MRT_MIN_1FC   NFC5_RFAL_CONV_64FC_TO_1FC( 0x0004u )

NRT Disabled: All 0 No-response timer is not started, wait forever.

◆ NFC5_NFC_MAX_DEVICES

#define NFC5_NFC_MAX_DEVICES   5u

Max number of devices supported.

◆ NFC5_NFCA_BCC_LEN

#define NFC5_NFCA_BCC_LEN   1u

BCC length.

◆ NFC5_NFCA_CASCADE_1_UID_LEN

#define NFC5_NFCA_CASCADE_1_UID_LEN   4u

NFC 5 Click RFAL NFC macros.

Specified macros for RFAL NFC. UID length of cascade level 1 only tag.

◆ NFC5_NFCA_CASCADE_2_UID_LEN

#define NFC5_NFCA_CASCADE_2_UID_LEN   7u

UID length of cascade level 2 only tag.

◆ NFC5_NFCA_CASCADE_3_UID_LEN

#define NFC5_NFCA_CASCADE_3_UID_LEN   10u

UID length of cascade level 3 only tag.

◆ NFC5_NFCA_FDTMIN

#define NFC5_NFCA_FDTMIN   1620u

Calculates SEL_CMD with the given cascade level

◆ NFC5_NFCA_N_RETRANS

#define NFC5_NFCA_N_RETRANS   2u

Number of retries EMVCo 2.6 9.6.1.3.

◆ NFC5_NFCA_SDD_CT

#define NFC5_NFCA_SDD_CT   0x88u

Cascade Tag value Digital 1.1 6.7.2.

◆ NFC5_NFCA_SDD_CT_LEN

#define NFC5_NFCA_SDD_CT_LEN   1u

Cascade Tag length.

◆ NFC5_NFCA_SDD_REQ_LEN

#define NFC5_NFCA_SDD_REQ_LEN   ( NFC5_NFCA_SEL_CMD_LEN + NFC5_NFCA_SEL_PAR_LEN )

SDD_REQ length.

◆ NFC5_NFCA_SDD_RES_LEN

#define NFC5_NFCA_SDD_RES_LEN   ( NFC5_NFCA_CASCADE_1_UID_LEN + NFC5_NFCA_BCC_LEN )

SDD_RES length.

◆ NFC5_NFCA_SEL_CMD_LEN

#define NFC5_NFCA_SEL_CMD_LEN   1u

SEL_CMD length.

◆ NFC5_NFCA_SEL_PAR_LEN

#define NFC5_NFCA_SEL_PAR_LEN   1u

SEL_PAR length.

◆ NFC5_NFCA_SEL_SELPAR

#define NFC5_NFCA_SEL_SELPAR   NFC5_RFAL_NFCA_SEL_PAR( 7u, 0u )

SEL_PAR on Select is always with 4 data/nfcid.

◆ NFC5_NFCA_SLP_BYTE2

#define NFC5_NFCA_SLP_BYTE2   0x00u

SLP byte2 Digital 1.1 6.9.1 & Table 20.

◆ NFC5_NFCA_SLP_BYTE2_POS

#define NFC5_NFCA_SLP_BYTE2_POS   1u

SLP byte2 position Digital 1.1 6.9.1 & Table 20.

◆ NFC5_NFCA_SLP_CMD

#define NFC5_NFCA_SLP_CMD   0x50u

SLP cmd (byte1) Digital 1.1 6.9.1 & Table 20.

◆ NFC5_NFCA_SLP_CMD_POS

#define NFC5_NFCA_SLP_CMD_POS   0u

SLP cmd position Digital 1.1 6.9.1 & Table 20.

◆ NFC5_NFCA_SLP_FWT

#define NFC5_NFCA_SLP_FWT   NFC5_RFAL_CONV_MS_TO_1FC ( 1 )

Check 1ms for any modulation ISO14443-3 6.4.3.

◆ NFC5_NFCA_SLP_REQ_LEN

#define NFC5_NFCA_SLP_REQ_LEN   2u

SLP_REQ length.

◆ NFC5_NFCIP1_BIT_RATE_GPT_ON

#define NFC5_NFCIP1_BIT_RATE_GPT_ON   ( 1u << 2 )

◆ NFC5_NFCIP1_BIT_RATE_MRT_ON

#define NFC5_NFCIP1_BIT_RATE_MRT_ON   ( 1u << 0 )

◆ NFC5_NFCIP1_BIT_RATE_NFC_RATE0

#define NFC5_NFCIP1_BIT_RATE_NFC_RATE0   ( 1u << 4 )

◆ NFC5_NFCIP1_BIT_RATE_NFC_RATE1

#define NFC5_NFCIP1_BIT_RATE_NFC_RATE1   ( 1u << 5 )

◆ NFC5_NFCIP1_BIT_RATE_NFC_RATE_MASK

#define NFC5_NFCIP1_BIT_RATE_NFC_RATE_MASK   ( 0x3u << 4 )

◆ NFC5_NFCIP1_BIT_RATE_NFC_RATE_SHIFT

#define NFC5_NFCIP1_BIT_RATE_NFC_RATE_SHIFT   ( 4u )

◆ NFC5_NFCIP1_BIT_RATE_NFC_RFU0

#define NFC5_NFCIP1_BIT_RATE_NFC_RFU0   ( 1u << 6 )

◆ NFC5_NFCIP1_BIT_RATE_NFC_RFU1

#define NFC5_NFCIP1_BIT_RATE_NFC_RFU1   ( 1u << 7 )

◆ NFC5_NFCIP1_BIT_RATE_NRT_ON

#define NFC5_NFCIP1_BIT_RATE_NRT_ON   ( 1u << 1 )

◆ NFC5_NFCIP1_BIT_RATE_PPT2_ON

#define NFC5_NFCIP1_BIT_RATE_PPT2_ON   ( 1u << 3 )

◆ NFC5_NRT_DISABLED

#define NFC5_NRT_DISABLED   0u

Max Register value of NRT.

◆ NFC5_NRT_MAX

#define NFC5_NRT_MAX   0xFFFFu

Returns the number of bytes required to fit given the number of bits

◆ NFC5_NRT_MAX_1FC

#define NFC5_NRT_MAX_1FC   NFC5_RFAL_CONV_4096FC_TO_1FC( 0xFFFFu )

Min MRT steps in 1fc ( 0<=MRT<=4 ; 4 (64/FC) => 0x0004 * 4.72us = 18.88us ).

◆ NFC5_OP_CTRL_EN

#define NFC5_OP_CTRL_EN   ( 1u << 7 )

◆ NFC5_OP_CTRL_EN_FD_AUTO_EFD

#define NFC5_OP_CTRL_EN_FD_AUTO_EFD   ( 3u << 0 )

◆ NFC5_OP_CTRL_EN_FD_C0

#define NFC5_OP_CTRL_EN_FD_C0   ( 1u << 0 )

◆ NFC5_OP_CTRL_EN_FD_C1

#define NFC5_OP_CTRL_EN_FD_C1   ( 1u << 1 )

◆ NFC5_OP_CTRL_EN_FD_EFD_OFF

#define NFC5_OP_CTRL_EN_FD_EFD_OFF   ( 0u << 0 )

◆ NFC5_OP_CTRL_EN_FD_MANUAL_EFD_CA

#define NFC5_OP_CTRL_EN_FD_MANUAL_EFD_CA   ( 1u << 0 )

◆ NFC5_OP_CTRL_EN_FD_MANUAL_EFD_PDT

#define NFC5_OP_CTRL_EN_FD_MANUAL_EFD_PDT   ( 2u << 0 )

◆ NFC5_OP_CTRL_EN_FD_MASK

#define NFC5_OP_CTRL_EN_FD_MASK   ( 3u << 0 )

◆ NFC5_OP_CTRL_EN_FD_SHIFT

#define NFC5_OP_CTRL_EN_FD_SHIFT   ( 0u )

◆ NFC5_OP_CTRL_RX_CHN

#define NFC5_OP_CTRL_RX_CHN   ( 1u << 5 )

◆ NFC5_OP_CTRL_RX_EN

#define NFC5_OP_CTRL_RX_EN   ( 1u << 6 )

◆ NFC5_OP_CTRL_RX_MAN

#define NFC5_OP_CTRL_RX_MAN   ( 1u << 4 )

◆ NFC5_OP_CTRL_TX_EN

#define NFC5_OP_CTRL_TX_EN   ( 1u << 3 )

◆ NFC5_OP_CTRL_WU

#define NFC5_OP_CTRL_WU   ( 1u << 2 )

◆ NFC5_PASSIVE_TARGET_D_106_AC_A

#define NFC5_PASSIVE_TARGET_D_106_AC_A   ( 1u << 0 )

◆ NFC5_PASSIVE_TARGET_D_212_424_1R

#define NFC5_PASSIVE_TARGET_D_212_424_1R   ( 1u << 2 )

◆ NFC5_PASSIVE_TARGET_D_AC_AP2P

#define NFC5_PASSIVE_TARGET_D_AC_AP2P   ( 1u << 3 )

◆ NFC5_PASSIVE_TARGET_FDEL_0

#define NFC5_PASSIVE_TARGET_FDEL_0   ( 1u << 4 )

◆ NFC5_PASSIVE_TARGET_FDEL_1

#define NFC5_PASSIVE_TARGET_FDEL_1   ( 1u << 5 )

◆ NFC5_PASSIVE_TARGET_FDEL_2

#define NFC5_PASSIVE_TARGET_FDEL_2   ( 1u << 6 )

◆ NFC5_PASSIVE_TARGET_FDEL_3

#define NFC5_PASSIVE_TARGET_FDEL_3   ( 1u << 7 )

◆ NFC5_PASSIVE_TARGET_FDEL_MASK

#define NFC5_PASSIVE_TARGET_FDEL_MASK   ( 0xFu << 4 )

◆ NFC5_PASSIVE_TARGET_FDEL_SHIFT

#define NFC5_PASSIVE_TARGET_FDEL_SHIFT   ( 4u )

◆ NFC5_PASSIVE_TARGET_RFU

#define NFC5_PASSIVE_TARGET_RFU   ( 1u << 1 )

◆ NFC5_PT_MOD_PT_RES0

#define NFC5_PT_MOD_PT_RES0   ( 1u << 0 )

◆ NFC5_PT_MOD_PT_RES1

#define NFC5_PT_MOD_PT_RES1   ( 1u << 1 )

◆ NFC5_PT_MOD_PT_RES2

#define NFC5_PT_MOD_PT_RES2   ( 1u << 2 )

◆ NFC5_PT_MOD_PT_RES3

#define NFC5_PT_MOD_PT_RES3   ( 1u << 3 )

◆ NFC5_PT_MOD_PT_RES_MASK

#define NFC5_PT_MOD_PT_RES_MASK   ( 0xFu << 0 )

◆ NFC5_PT_MOD_PT_RES_SHIFT

#define NFC5_PT_MOD_PT_RES_SHIFT   ( 0u )

◆ NFC5_PT_MOD_PTM_RES0

#define NFC5_PT_MOD_PTM_RES0   ( 1u << 4 )

◆ NFC5_PT_MOD_PTM_RES1

#define NFC5_PT_MOD_PTM_RES1   ( 1u << 5 )

◆ NFC5_PT_MOD_PTM_RES2

#define NFC5_PT_MOD_PTM_RES2   ( 1u << 6 )

◆ NFC5_PT_MOD_PTM_RES3

#define NFC5_PT_MOD_PTM_RES3   ( 1u << 7 )

◆ NFC5_PT_MOD_PTM_RES_MASK

#define NFC5_PT_MOD_PTM_RES_MASK   ( 0xFu << 4 )

◆ NFC5_PT_MOD_PTM_RES_SHIFT

#define NFC5_PT_MOD_PTM_RES_SHIFT   ( 4u )

◆ NFC5_REGULATOR_CTRL_MPSV0

#define NFC5_REGULATOR_CTRL_MPSV0   ( 1u << 0 )

◆ NFC5_REGULATOR_CTRL_MPSV1

#define NFC5_REGULATOR_CTRL_MPSV1   ( 1u << 1 )

◆ NFC5_REGULATOR_CTRL_MPSV2

#define NFC5_REGULATOR_CTRL_MPSV2   ( 2u << 2 )

◆ NFC5_REGULATOR_CTRL_MPSV_MASK

#define NFC5_REGULATOR_CTRL_MPSV_MASK   ( 7u )

◆ NFC5_REGULATOR_CTRL_MPSV_SHIFT

#define NFC5_REGULATOR_CTRL_MPSV_SHIFT   ( 0u )

◆ NFC5_REGULATOR_CTRL_MPSV_VDD

#define NFC5_REGULATOR_CTRL_MPSV_VDD   ( 0u )

◆ NFC5_REGULATOR_CTRL_MPSV_VDD_A

#define NFC5_REGULATOR_CTRL_MPSV_VDD_A   ( 1u )

◆ NFC5_REGULATOR_CTRL_MPSV_VDD_AM

#define NFC5_REGULATOR_CTRL_MPSV_VDD_AM   ( 4u )

◆ NFC5_REGULATOR_CTRL_MPSV_VDD_D

#define NFC5_REGULATOR_CTRL_MPSV_VDD_D   ( 2u )

◆ NFC5_REGULATOR_CTRL_MPSV_VDD_RF

#define NFC5_REGULATOR_CTRL_MPSV_VDD_RF   ( 3u )

◆ NFC5_REGULATOR_CTRL_REG_S

#define NFC5_REGULATOR_CTRL_REG_S   ( 1u << 7 )

◆ NFC5_REGULATOR_CTRL_REGE_0

#define NFC5_REGULATOR_CTRL_REGE_0   ( 1u << 3 )

◆ NFC5_REGULATOR_CTRL_REGE_1

#define NFC5_REGULATOR_CTRL_REGE_1   ( 1u << 4 )

◆ NFC5_REGULATOR_CTRL_REGE_2

#define NFC5_REGULATOR_CTRL_REGE_2   ( 1u << 5 )

◆ NFC5_REGULATOR_CTRL_REGE_3

#define NFC5_REGULATOR_CTRL_REGE_3   ( 1u << 6 )

◆ NFC5_REGULATOR_CTRL_REGE_MASK

#define NFC5_REGULATOR_CTRL_REGE_MASK   ( 0xFu << 3 )

◆ NFC5_REGULATOR_CTRL_REGE_SHIFT

#define NFC5_REGULATOR_CTRL_REGE_SHIFT   ( 3u )

◆ NFC5_REGULATOR_CTRL_RFU

#define NFC5_REGULATOR_CTRL_RFU   ( 5u )

◆ NFC5_REGULATOR_CTRL_RFU1

#define NFC5_REGULATOR_CTRL_RFU1   ( 6u )

◆ NFC5_REGULATOR_CTRL_RFU2

#define NFC5_REGULATOR_CTRL_RFU2   ( 7u )

◆ NFC5_RFAL_CALC_NUM_BYTES

#define NFC5_RFAL_CALC_NUM_BYTES (   NBITS)    ( ( ( uint32_t )( NBITS ) + 7u ) / 8u )

◆ NFC5_RFAL_CONV_1FC_TO_4096FC

#define NFC5_RFAL_CONV_1FC_TO_4096FC (   T)    ( uint32_t ) ( ( uint32_t) ( T ) / NFC5_1FC_IN_4096FC )

Converts the given t from 4096/fc to 1/fc.

◆ NFC5_RFAL_CONV_1FC_TO_64FC

#define NFC5_RFAL_CONV_1FC_TO_64FC (   T)    ( uint32_t ) ( ( uint32_t ) ( T ) / NFC5_1FC_IN_64FC )

Converts the given t from 64/fc to 1/fc.

◆ NFC5_RFAL_CONV_1FC_TO_MS

#define NFC5_RFAL_CONV_1FC_TO_MS (   T)    ( uint32_t ) ( ( uint32_t) ( T ) / NFC5_1MS_IN_1FC )

Converts the given t from ms to 1/fc.

◆ NFC5_RFAL_CONV_4096FC_TO_1FC

#define NFC5_RFAL_CONV_4096FC_TO_1FC (   T)    ( uint32_t ) ( ( uint32_t) ( T ) * NFC5_1FC_IN_4096FC )

Converts the given t from 1/fc to ms.

◆ NFC5_RFAL_CONV_64FC_TO_1FC

#define NFC5_RFAL_CONV_64FC_TO_1FC (   T)    ( uint32_t ) ( ( uint32_t ) ( T ) * NFC5_1FC_IN_64FC )

Converts the given n from bits to bytes.

◆ NFC5_RFAL_CONV_BITS_TO_BYTES

#define NFC5_RFAL_CONV_BITS_TO_BYTES (   N)
Value:
( uint16_t ) ( ( ( uint16_t ) ( N )+ ( NFC5_BITS_IN_BYTE-1u ) ) \

Converts the given n from bytes to bits.

◆ NFC5_RFAL_CONV_BYTES_TO_BITS

#define NFC5_RFAL_CONV_BYTES_TO_BITS (   N)    ( uint32_t ) ( ( uint32_t) ( N ) * ( NFC5_BITS_IN_BYTE ) )

Converts the given t from 1/fc to 4096/fc.

◆ NFC5_RFAL_CONV_MS_TO_1FC

#define NFC5_RFAL_CONV_MS_TO_1FC (   T)    ( uint32_t ) ( ( uint32_t) ( T ) * NFC5_1MS_IN_1FC )

Disabled FWT: Wait forever for a response.

◆ NFC5_RFAL_CREATE_BYTE_FLAGS_TX_RX_CONTEXT

#define NFC5_RFAL_CREATE_BYTE_FLAGS_TX_RX_CONTEXT (   CTX,
  TB,
  TBL,
  RB,
  RBL,
  RDL,
  FL,
 
)
Value:
( CTX ).tx_buf = ( uint8_t* ) ( TB ); \
( CTX ).tx_buf_len = ( uint16_t) NFC5_RFAL_CONV_BYTES_TO_BITS ( TBL ); \
( CTX ).rx_buf = ( uint8_t* ) ( RB ); \
( CTX ).rx_buf_len = ( uint16_t ) NFC5_RFAL_CONV_BYTES_TO_BITS ( RBL ); \
( CTX ).rx_rcvd_len = ( uint16_t* ) ( RDL ); \
( CTX ).flags = ( uint32_t ) ( FL ); \
( CTX ).fwt = ( uint32_t ) ( T );

NFC 5 Click rfal create byte flags tx rx context macro.

Computes a Transceive context CTX using lengths in bytes with the given flags and arguments CTX : Transceive context to be assigned
TB : tx_buf the pointer to the buffer to be sent TBL : tx_buf length in bytes RB : rx_buf the pointer to the buffer to place the received frame RBL : rx_buf length in bytes RDL : rx_rcvd_buf length in bytes FL : transceive flags indication T : FWT to be used on this transceive in 1/fc

◆ NFC5_RFAL_NFCA_CLN2_SEL_CMD

#define NFC5_RFAL_NFCA_CLN2_SEL_CMD (   CL)    ( uint8_t )( ( uint8_t )( NFC5_NFCA_CMD_SEL_CL1 ) + ( 2u * ( CL ) ) )

Calculates SEL_PAR with the bytes/bits to be sent

◆ NFC5_RFAL_NFCA_NFC_ID_LEN_2CL

#define NFC5_RFAL_NFCA_NFC_ID_LEN_2CL (   LEN)    ( ( LEN ) / 5u )

Calculates cascade level by the NFCID length.

◆ NFC5_RFAL_NFCA_SEL_PAR

#define NFC5_RFAL_NFCA_SEL_PAR (   NBY,
  NBI 
)    ( uint8_t )( ( ( ( NBY ) << 4u ) & 0xF0u ) | ( ( NBI ) &0x0Fu ) )

◆ NFC5_RX_CFG_2_AGC6_3

#define NFC5_RX_CFG_2_AGC6_3   ( 1u << 0 )

◆ NFC5_RX_CFG_2_AGC_ALG

#define NFC5_RX_CFG_2_AGC_ALG   ( 1u << 1 )

◆ NFC5_RX_CFG_2_AGC_EN

#define NFC5_RX_CFG_2_AGC_EN   ( 1u << 3 )

◆ NFC5_RX_CFG_2_AGC_M

#define NFC5_RX_CFG_2_AGC_M   ( 1u << 2 )

◆ NFC5_RX_CFG_2_AMD_SEL

#define NFC5_RX_CFG_2_AMD_SEL   ( 1u << 6 )

◆ NFC5_RX_CFG_2_AMD_SEL_MIXER

#define NFC5_RX_CFG_2_AMD_SEL_MIXER   ( 1u << 6 )

◆ NFC5_RX_CFG_2_AMD_SEL_PEAK

#define NFC5_RX_CFG_2_AMD_SEL_PEAK   ( 0u << 6 )

◆ NFC5_RX_CFG_2_DEMOD_MODE

#define NFC5_RX_CFG_2_DEMOD_MODE   ( 1u << 7 )

◆ NFC5_RX_CFG_2_PULZ_61

#define NFC5_RX_CFG_2_PULZ_61   ( 1u << 4 )

◆ NFC5_RX_CFG_2_SQM_DYN

#define NFC5_RX_CFG_2_SQM_DYN   ( 1u << 5 )

◆ NFC5_SET_DATA_SAMPLE_EDGE

#define NFC5_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note
Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with nfc5_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ NFC5_SET_DATA_SAMPLE_MIDDLE

#define NFC5_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

◆ NFC5_TEST_REG_INDICATOR

#define NFC5_TEST_REG_INDICATOR   0x0080

NFC 5 Click analog config values.

Specified values for the chip analog configuration. Test Register indicator.

◆ NFC5_THLD_DO_NOT_SET

#define NFC5_THLD_DO_NOT_SET   0xFFu

Indicates not to change this Threshold. NFC-A minimum FDT( listen ) = ( ( n * 128 + ( 84 ) ) / fc ) with n_min = 9 Digital 1.1 6.10.1 = ( 1236 ) / fc Relax with 3etu: ( 3 * 128 ) / fc as with multiple NFC-A cards, response may take longer ( JCOP cards ) = ( 1236 + 384 )/ fc = 1620 / fc

◆ NFC5_TIMER_EMV_CONTROL_GPTC0

#define NFC5_TIMER_EMV_CONTROL_GPTC0   ( 1u << 5 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC1

#define NFC5_TIMER_EMV_CONTROL_GPTC1   ( 1u << 6 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC2

#define NFC5_TIMER_EMV_CONTROL_GPTC2   ( 1u << 7 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC_ERX

#define NFC5_TIMER_EMV_CONTROL_GPTC_ERX   ( 1u << 5 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC_ETX_NFC

#define NFC5_TIMER_EMV_CONTROL_GPTC_ETX_NFC   ( 3u << 5 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC_MASK

#define NFC5_TIMER_EMV_CONTROL_GPTC_MASK   ( 7u << 5 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC_NO_TRIGGER

#define NFC5_TIMER_EMV_CONTROL_GPTC_NO_TRIGGER   ( 0u << 5 )

◆ NFC5_TIMER_EMV_CONTROL_GPTC_SHIFT

#define NFC5_TIMER_EMV_CONTROL_GPTC_SHIFT   ( 5u )

◆ NFC5_TIMER_EMV_CONTROL_GPTC_SRX

#define NFC5_TIMER_EMV_CONTROL_GPTC_SRX   ( 2u << 5 )

◆ NFC5_TIMER_EMV_CONTROL_MRT_STEP

#define NFC5_TIMER_EMV_CONTROL_MRT_STEP   ( 1u << 3 )

◆ NFC5_TIMER_EMV_CONTROL_MRT_STEP_512

#define NFC5_TIMER_EMV_CONTROL_MRT_STEP_512   ( 1u << 3 )

◆ NFC5_TIMER_EMV_CONTROL_MRT_STEP_64

#define NFC5_TIMER_EMV_CONTROL_MRT_STEP_64   ( 0u << 3 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_EMV

#define NFC5_TIMER_EMV_CONTROL_NRT_EMV   ( 1u << 1 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_EMV_OFF

#define NFC5_TIMER_EMV_CONTROL_NRT_EMV_OFF   ( 0u << 1 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_EMV_ON

#define NFC5_TIMER_EMV_CONTROL_NRT_EMV_ON   ( 1u << 1 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_NFC

#define NFC5_TIMER_EMV_CONTROL_NRT_NFC   ( 1u << 2 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_NFC_OFF

#define NFC5_TIMER_EMV_CONTROL_NRT_NFC_OFF   ( 0u << 2 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_NFC_ON

#define NFC5_TIMER_EMV_CONTROL_NRT_NFC_ON   ( 1u << 2 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_STEP

#define NFC5_TIMER_EMV_CONTROL_NRT_STEP   ( 1u << 0 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_STEP_4096_FC

#define NFC5_TIMER_EMV_CONTROL_NRT_STEP_4096_FC   ( 1u << 0 )

◆ NFC5_TIMER_EMV_CONTROL_NRT_STEP_64FC

#define NFC5_TIMER_EMV_CONTROL_NRT_STEP_64FC   ( 0u << 0 )

◆ NFC5_TIMER_EMV_CONTROL_RFU

#define NFC5_TIMER_EMV_CONTROL_RFU   ( 1u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD0

#define NFC5_TX_DRIVER_AM_MOD0   ( 1u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD1

#define NFC5_TX_DRIVER_AM_MOD1   ( 1u << 5 )

◆ NFC5_TX_DRIVER_AM_MOD2

#define NFC5_TX_DRIVER_AM_MOD2   ( 1u << 6 )

◆ NFC5_TX_DRIVER_AM_MOD3

#define NFC5_TX_DRIVER_AM_MOD3   ( 1u << 7 )

◆ NFC5_TX_DRIVER_AM_MOD_10PERCENT

#define NFC5_TX_DRIVER_AM_MOD_10PERCENT   ( 0x5u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_11PERCENT

#define NFC5_TX_DRIVER_AM_MOD_11PERCENT   ( 0x6u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_12PERCENT

#define NFC5_TX_DRIVER_AM_MOD_12PERCENT   ( 0x7u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_13PERCENT

#define NFC5_TX_DRIVER_AM_MOD_13PERCENT   ( 0x8u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_14PERCENT

#define NFC5_TX_DRIVER_AM_MOD_14PERCENT   ( 0x9u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_15PERCENT

#define NFC5_TX_DRIVER_AM_MOD_15PERCENT   ( 0xAu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_17PERCENT

#define NFC5_TX_DRIVER_AM_MOD_17PERCENT   ( 0xBu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_19PERCENT

#define NFC5_TX_DRIVER_AM_MOD_19PERCENT   ( 0xCu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_22PERCENT

#define NFC5_TX_DRIVER_AM_MOD_22PERCENT   ( 0xDu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_26PERCENT

#define NFC5_TX_DRIVER_AM_MOD_26PERCENT   ( 0xEu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_40PERCENT

#define NFC5_TX_DRIVER_AM_MOD_40PERCENT   ( 0xFu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_5PERCENT

#define NFC5_TX_DRIVER_AM_MOD_5PERCENT   ( 0x0u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_6PERCENT

#define NFC5_TX_DRIVER_AM_MOD_6PERCENT   ( 0x1u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_7PERCENT

#define NFC5_TX_DRIVER_AM_MOD_7PERCENT   ( 0x2u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_8PERCENT

#define NFC5_TX_DRIVER_AM_MOD_8PERCENT   ( 0x3u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_9PERCENT

#define NFC5_TX_DRIVER_AM_MOD_9PERCENT   ( 0x4u << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_MASK

#define NFC5_TX_DRIVER_AM_MOD_MASK   ( 0xFu << 4 )

◆ NFC5_TX_DRIVER_AM_MOD_SHIFT

#define NFC5_TX_DRIVER_AM_MOD_SHIFT   ( 4u )

◆ NFC5_TX_DRIVER_D_RES0

#define NFC5_TX_DRIVER_D_RES0   ( 1u << 0 )

◆ NFC5_TX_DRIVER_D_RES1

#define NFC5_TX_DRIVER_D_RES1   ( 1u << 1 )

◆ NFC5_TX_DRIVER_D_RES2

#define NFC5_TX_DRIVER_D_RES2   ( 1u << 2 )

◆ NFC5_TX_DRIVER_D_RES3

#define NFC5_TX_DRIVER_D_RES3   ( 1u << 3 )

◆ NFC5_TX_DRIVER_D_RES_MASK

#define NFC5_TX_DRIVER_D_RES_MASK   ( 0xFu << 0 )

◆ NFC5_TX_DRIVER_D_RES_SHIFT

#define NFC5_TX_DRIVER_D_RES_SHIFT   ( 0u )

◆ NFC5_TXRX_FLAGS_DEFAULT

#define NFC5_TXRX_FLAGS_DEFAULT
Value:

◆ NFC5_US_IN_MS

#define NFC5_US_IN_MS   1000u

Number of us in one ms.

NFC5_TXRX_FLAGS_CRC_RX_REMV
@ NFC5_TXRX_FLAGS_CRC_RX_REMV
Definition: nfc5.h:1236
NFC5_RFAL_CONV_BYTES_TO_BITS
#define NFC5_RFAL_CONV_BYTES_TO_BITS(N)
Definition: nfc5.h:320
NFC5_TXRX_FLAGS_PAR_TX_AUTO
@ NFC5_TXRX_FLAGS_PAR_TX_AUTO
Definition: nfc5.h:1251
NFC5_TXRX_FLAGS_PAR_RX_REMV
@ NFC5_TXRX_FLAGS_PAR_RX_REMV
Definition: nfc5.h:1247
NFC5_TXRX_FLAGS_NFCV_FLAG_AUTO
@ NFC5_TXRX_FLAGS_NFCV_FLAG_AUTO
Definition: nfc5.h:1254
NFC5_TXRX_FLAGS_CRC_TX_AUTO
@ NFC5_TXRX_FLAGS_CRC_TX_AUTO
Definition: nfc5.h:1232
NFC5_BITS_IN_BYTE
#define NFC5_BITS_IN_BYTE
Definition: nfc5.h:306
NFC5_TXRX_FLAGS_NFCIP1_OFF
@ NFC5_TXRX_FLAGS_NFCIP1_OFF
Definition: nfc5.h:1239
NFC5_TXRX_FLAGS_AGC_ON
@ NFC5_TXRX_FLAGS_AGC_ON
Definition: nfc5.h:1243