c3dhall5 2.0.0.0
c3dhall5.h
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1/*
2 * MikroSDK - MikroE Software Development Kit
3 * Copyright© 2020 MikroElektronika d.o.o.
4 *
5 * Permission is hereby granted, free of charge, to any person
6 * obtaining a copy of this software and associated documentation
7 * files (the "Software"), to deal in the Software without restriction,
8 * including without limitation the rights to use, copy, modify, merge,
9 * publish, distribute, sublicense, and/or sell copies of the Software,
10 * and to permit persons to whom the Software is furnished to do so,
11 * subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22 * OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
33// ----------------------------------------------------------------------------
34
35#ifndef C3DHALL5_H
36#define C3DHALL5_H
37
38#include "drv_digital_out.h"
39#include "drv_digital_in.h"
40#include "drv_i2c_master.h"
41#include "drv_spi_master.h"
42
43// -------------------------------------------------------------- PUBLIC MACROS
54#define C3DHALL5_MAP_MIKROBUS( cfg, mikrobus ) \
55 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
56 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
57 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
58 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
59 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
60 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
61 cfg.css = MIKROBUS( mikrobus, MIKROBUS_RST ); \
62 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
69#define C3DHALL5_MASTER_I2C 0
70#define C3DHALL5_MASTER_SPI 1
77#define C3DHALL5_RETVAL uint8_t
78
79#define C3DHALL5_OK 0x00
80#define C3DHALL5_INIT_ERROR 0xFF
87#define C3DHALL5_I_AM 0x40;
94#define C3DHALL5_AXIS_X 0x68
95#define C3DHALL5_AXIS_Y 0x6A
96#define C3DHALL5_AXIS_Z 0x6C
103#define C3DHALL5_OFFSET_AXIS_X 0x45
104#define C3DHALL5_OFFSET_AXIS_Y 0x47
105#define C3DHALL5_OFFSET_AXIS_Z 0x49
112#define C3DHALL5_REG_OFFSET_X_LSB 0x45
113#define C3DHALL5_REG_OFFSET_X_MSB 0x46
114#define C3DHALL5_REG_OFFSET_Y_LSB 0x47
115#define C3DHALL5_REG_OFFSET_Y_MSB 0x48
116#define C3DHALL5_REG_OFFSET_Z_LSB 0x49
117#define C3DHALL5_REG_OFFSET_Z_MSB 0x4A
118#define C3DHALL5_REG_WHO_AM_I 0x4F
119#define C3DHALL5_REG_CONFIG_A 0x60
120#define C3DHALL5_REG_CONFIG_B 0x61
121#define C3DHALL5_REG_CONFIG_C 0x62
122#define C3DHALL5_REG_INT_CTRL 0x63
123#define C3DHALL5_REG_INT_SOURCE 0x64
124#define C3DHALL5_REG_INT_THS_LSB 0x65
125#define C3DHALL5_REG_INT_THS_MSB 0x66
126#define C3DHALL5_REG_STATUS 0x67
127#define C3DHALL5_REG_X_AXIS_LSB 0x68
128#define C3DHALL5_REG_X_AXIS_MSB 0x69
129#define C3DHALL5_REG_Y_AXIS_LSB 0x6A
130#define C3DHALL5_REG_Y_AXIS_MSB 0x6B
131#define C3DHALL5_REG_Z_AXIS_LSB 0x6C
132#define C3DHALL5_REG_Z_AXIS_MSB 0x6D
133#define C3DHALL5_REG_TEMP_LSB 0x6E
134#define C3DHALL5_REG_TEMP_MSB 0x6F
141#define C3DHALL5_CFG_A_COMP_TEMP_ENABLE 0x80
142#define C3DHALL5_CFG_A_COMP_TEMP_DISABLE 0x00
143#define C3DHALL5_CFG_A_REBOOT_MEM_CONTENT 0x40
144#define C3DHALL5_CFG_A_NORMAL_MODE 0x00
145#define C3DHALL5_CFG_A_SOFTRESET 0x20
146#define C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE 0x00
147#define C3DHALL5_CFG_A_LOW_POWER_MODE 0x10
148#define C3DHALL5_CFG_A_ODR_10Hz 0x00
149#define C3DHALL5_CFG_A_ODR_20Hz 0x04
150#define C3DHALL5_CFG_A_ODR_50Hz 0x08
151#define C3DHALL5_CFG_A_ODR_100Hz 0x0C
152#define C3DHALL5_CFG_A_MODE_CONTINUOUS 0x00
153#define C3DHALL5_CFG_A_MODE_SINGLE 0x01
154#define C3DHALL5_CFG_A_MODE_IDLE 0x02
161#define C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_ENABLE 0x10
162#define C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_DISABLE 0x00
163#define C3DHALL5_CFG_B_INT_ON_DATA_OFF 0x08
164#define C3DHALL5_CFG_B_SET_PULSE_63_ODR 0x00
165#define C3DHALL5_CFG_B_SET_PULSE_PD_CONDITION 0x04
166#define C3DHALL5_CFG_B_OFFSET_ENABLE 0x02
167#define C3DHALL5_CFG_B_OFFSET_DISABLE 0x00
168#define C3DHALL5_CFG_B_LPF_DISABLE_ODR_2 0x00
169#define C3DHALL5_CFG_B_LPF_ENABLE_ODR_4 0x01
176#define C3DHALL5_CFG_C_INT_ON_PIN 0x40
177#define C3DHALL5_CFG_C_INT_ON_PIN_DISABLE 0x00
178#define C3DHALL5_CFG_C_I2C_DISABLE 0x20
179#define C3DHALL5_CFG_C_BLE_ENABLE 0x08
180#define C3DHALL5_CFG_C_SELF_TEST 0x02
181#define C3DHALL5_CFG_C_DRDY_ON_PIN 0x01
188#define C3DHALL5_INT_CTRL_X_AXIS_ENABLE 0x80
189#define C3DHALL5_INT_CTRL_Y_AXIS_ENABLE 0x40
190#define C3DHALL5_INT_CTRL_Z_AXIS_ENABLE 0x20
191#define C3DHALL5_INT_CTRL_IEA_0_SIGNALS_AN_INT 0x00
192#define C3DHALL5_INT_CTRL_IEA_1_SIGNALS_AN_INT 0x04
193#define C3DHALL5_INT_CTRL_IEL_INT_IS_PILSED 0x00
194#define C3DHALL5_INT_CTRL_IEL_INT_IS_LATCHED 0x02
195#define C3DHALL5_INT_CTRL_IEN_INT_ENABLE 0x01
196#define C3DHALL5_INT_CTRL_IEN_INT_DISABLE 0x00
203#define C3DHALL5_INT_SOURCE_POS_TH_X 0x80
204#define C3DHALL5_INT_SOURCE_POS_TH_Y 0x40
205#define C3DHALL5_INT_SOURCE_POS_TH_Z 0x20
206#define C3DHALL5_INT_SOURCE_NEG_TH_X 0x10
207#define C3DHALL5_INT_SOURCE_NEG_TH_Y 0x08
208#define C3DHALL5_INT_SOURCE_NEG_TH_N 0x04
215#define C3DHALL5_STATUS_XYZ_DATA_OVERRUN 0x80
216#define C3DHALL5_STATUS_Z_DATA_OVERRUN 0x40
217#define C3DHALL5_STATUS_Y_DATA_OVERRUN 0x20
218#define C3DHALL5_STATUS_X_DATA_OVERRUN 0x10
219#define C3DHALL5_STATUS_XYZ_NEW_DATA 0x08
220#define C3DHALL5_STATUS_Z_NEW_DATA 0x04
221#define C3DHALL5_STATUS_Y_NEW_DATA 0x02
222#define C3DHALL5_STATUS_X_NEW_DATA 0x01 // End group macro
226// --------------------------------------------------------------- PUBLIC TYPES
235typedef uint8_t c3dhall5_select_t;
236
240typedef void ( *c3dhall5_master_io_t )( struct c3dhall5_s*, uint8_t, uint8_t*, uint8_t );
241
245typedef struct c3dhall5_s
246{
247 // Output pins
248 digital_out_t css;
249
250 // Input pins
251
252 digital_in_t int_pin;
253
254 // Modules
255
256 i2c_master_t i2c;
257 spi_master_t spi;
258
259 // ctx variable
260
262 pin_name_t chip_select;
266
268
272typedef struct
273{
274 // Communication gpio pins
275
276 pin_name_t scl;
277 pin_name_t sda;
278 pin_name_t miso;
279 pin_name_t mosi;
280 pin_name_t sck;
281 pin_name_t cs;
282
283 // Additional gpio pins
284
285 pin_name_t css;
286 pin_name_t int_pin;
287
288 // static variable
289
290 uint32_t i2c_speed;
291 uint8_t i2c_address;
292
293 uint32_t spi_speed;
294 spi_master_mode_t spi_mode;
295 spi_master_chip_select_polarity_t cs_polarity;
296
298
300 // End types group
302// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
308#ifdef __cplusplus
309extern "C"{
310#endif
311
321
330
346
357void c3dhall5_generic_write ( c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
358
369void c3dhall5_generic_read ( c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
370
380
390
398
406void c3dhall5_set_offset ( c3dhall5_t *ctx, uint8_t offset_axis, int16_t offset );
407
415int16_t c3dhall5_get_axis_data ( c3dhall5_t *ctx, uint8_t axis );
416
417#ifdef __cplusplus
418}
419#endif
420#endif // _C3DHALL5_H_
421 // End public_function group
424
425// ------------------------------------------------------------------------- END
#define C3DHALL5_RETVAL
Definition: c3dhall5.h:77
void c3dhall5_cfg_setup(c3dhall5_cfg_t *cfg)
Config Object Initialization function.
uint8_t c3dhall5_get_interrupt_state(c3dhall5_t *ctx)
Interrupt state.
float c3dhall5_get_temperature_data(c3dhall5_t *ctx)
Temperature data.
uint8_t c3dhall5_get_device_id(c3dhall5_t *ctx)
Device ID.
void c3dhall5_set_offset(c3dhall5_t *ctx, uint8_t offset_axis, int16_t offset)
Set offest.
void c3dhall5_generic_write(c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
C3DHALL5_RETVAL c3dhall5_init(c3dhall5_t *ctx, c3dhall5_cfg_t *cfg)
Initialization function.
int16_t c3dhall5_get_axis_data(c3dhall5_t *ctx, uint8_t axis)
Axis data.
void c3dhall5_default_cfg(c3dhall5_t *ctx)
Click Default Configuration function.
void c3dhall5_generic_read(c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
uint8_t c3dhall5_select_t
Communication type.
Definition: c3dhall5.h:235
struct c3dhall5_s c3dhall5_t
Click ctx object definition.
void(* c3dhall5_master_io_t)(struct c3dhall5_s *, uint8_t, uint8_t *, uint8_t)
Master Input/Output type.
Definition: c3dhall5.h:240
Click configuration structure definition.
Definition: c3dhall5.h:273
uint32_t i2c_speed
Definition: c3dhall5.h:290
c3dhall5_select_t sel
Definition: c3dhall5.h:297
spi_master_chip_select_polarity_t cs_polarity
Definition: c3dhall5.h:295
pin_name_t sck
Definition: c3dhall5.h:280
spi_master_mode_t spi_mode
Definition: c3dhall5.h:294
pin_name_t mosi
Definition: c3dhall5.h:279
uint32_t spi_speed
Definition: c3dhall5.h:293
pin_name_t scl
Definition: c3dhall5.h:276
pin_name_t int_pin
Definition: c3dhall5.h:286
pin_name_t css
Definition: c3dhall5.h:285
pin_name_t miso
Definition: c3dhall5.h:278
pin_name_t sda
Definition: c3dhall5.h:277
pin_name_t cs
Definition: c3dhall5.h:281
uint8_t i2c_address
Definition: c3dhall5.h:291
Click ctx object definition.
Definition: c3dhall5.h:246
c3dhall5_master_io_t read_f
Definition: c3dhall5.h:264
spi_master_t spi
Definition: c3dhall5.h:257
c3dhall5_master_io_t write_f
Definition: c3dhall5.h:263
digital_in_t int_pin
Definition: c3dhall5.h:252
i2c_master_t i2c
Definition: c3dhall5.h:256
digital_out_t css
Definition: c3dhall5.h:248
uint8_t slave_address
Definition: c3dhall5.h:261
c3dhall5_select_t master_sel
Definition: c3dhall5.h:265
pin_name_t chip_select
Definition: c3dhall5.h:262