c3dhall5  2.0.0.0
c3dhall5.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef C3DHALL5_H
36 #define C3DHALL5_H
37 
38 #include "mikrosdk_version.h"
39 
40 #ifdef __GNUC__
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
43 #else
44 #include "delays.h"
45 #endif
46 #endif
47 
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_i2c_master.h"
51 #include "drv_spi_master.h"
52 
53 // -------------------------------------------------------------- PUBLIC MACROS
64 #define C3DHALL5_MAP_MIKROBUS( cfg, mikrobus ) \
65  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
66  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
67  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
68  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
69  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
70  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
71  cfg.css = MIKROBUS( mikrobus, MIKROBUS_RST ); \
72  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
73 
79 #define C3DHALL5_MASTER_I2C 0
80 #define C3DHALL5_MASTER_SPI 1
81 
87 #define C3DHALL5_RETVAL uint8_t
88 
89 #define C3DHALL5_OK 0x00
90 #define C3DHALL5_INIT_ERROR 0xFF
91 
97 #define C3DHALL5_I_AM 0x40;
98 
104 #define C3DHALL5_AXIS_X 0x68
105 #define C3DHALL5_AXIS_Y 0x6A
106 #define C3DHALL5_AXIS_Z 0x6C
107 
113 #define C3DHALL5_OFFSET_AXIS_X 0x45
114 #define C3DHALL5_OFFSET_AXIS_Y 0x47
115 #define C3DHALL5_OFFSET_AXIS_Z 0x49
116 
122 #define C3DHALL5_REG_OFFSET_X_LSB 0x45
123 #define C3DHALL5_REG_OFFSET_X_MSB 0x46
124 #define C3DHALL5_REG_OFFSET_Y_LSB 0x47
125 #define C3DHALL5_REG_OFFSET_Y_MSB 0x48
126 #define C3DHALL5_REG_OFFSET_Z_LSB 0x49
127 #define C3DHALL5_REG_OFFSET_Z_MSB 0x4A
128 #define C3DHALL5_REG_WHO_AM_I 0x4F
129 #define C3DHALL5_REG_CONFIG_A 0x60
130 #define C3DHALL5_REG_CONFIG_B 0x61
131 #define C3DHALL5_REG_CONFIG_C 0x62
132 #define C3DHALL5_REG_INT_CTRL 0x63
133 #define C3DHALL5_REG_INT_SOURCE 0x64
134 #define C3DHALL5_REG_INT_THS_LSB 0x65
135 #define C3DHALL5_REG_INT_THS_MSB 0x66
136 #define C3DHALL5_REG_STATUS 0x67
137 #define C3DHALL5_REG_X_AXIS_LSB 0x68
138 #define C3DHALL5_REG_X_AXIS_MSB 0x69
139 #define C3DHALL5_REG_Y_AXIS_LSB 0x6A
140 #define C3DHALL5_REG_Y_AXIS_MSB 0x6B
141 #define C3DHALL5_REG_Z_AXIS_LSB 0x6C
142 #define C3DHALL5_REG_Z_AXIS_MSB 0x6D
143 #define C3DHALL5_REG_TEMP_LSB 0x6E
144 #define C3DHALL5_REG_TEMP_MSB 0x6F
145 
151 #define C3DHALL5_CFG_A_COMP_TEMP_ENABLE 0x80
152 #define C3DHALL5_CFG_A_COMP_TEMP_DISABLE 0x00
153 #define C3DHALL5_CFG_A_REBOOT_MEM_CONTENT 0x40
154 #define C3DHALL5_CFG_A_NORMAL_MODE 0x00
155 #define C3DHALL5_CFG_A_SOFTRESET 0x20
156 #define C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE 0x00
157 #define C3DHALL5_CFG_A_LOW_POWER_MODE 0x10
158 #define C3DHALL5_CFG_A_ODR_10Hz 0x00
159 #define C3DHALL5_CFG_A_ODR_20Hz 0x04
160 #define C3DHALL5_CFG_A_ODR_50Hz 0x08
161 #define C3DHALL5_CFG_A_ODR_100Hz 0x0C
162 #define C3DHALL5_CFG_A_MODE_CONTINUOUS 0x00
163 #define C3DHALL5_CFG_A_MODE_SINGLE 0x01
164 #define C3DHALL5_CFG_A_MODE_IDLE 0x02
165 
171 #define C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_ENABLE 0x10
172 #define C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_DISABLE 0x00
173 #define C3DHALL5_CFG_B_INT_ON_DATA_OFF 0x08
174 #define C3DHALL5_CFG_B_SET_PULSE_63_ODR 0x00
175 #define C3DHALL5_CFG_B_SET_PULSE_PD_CONDITION 0x04
176 #define C3DHALL5_CFG_B_OFFSET_ENABLE 0x02
177 #define C3DHALL5_CFG_B_OFFSET_DISABLE 0x00
178 #define C3DHALL5_CFG_B_LPF_DISABLE_ODR_2 0x00
179 #define C3DHALL5_CFG_B_LPF_ENABLE_ODR_4 0x01
180 
186 #define C3DHALL5_CFG_C_INT_ON_PIN 0x40
187 #define C3DHALL5_CFG_C_INT_ON_PIN_DISABLE 0x00
188 #define C3DHALL5_CFG_C_I2C_DISABLE 0x20
189 #define C3DHALL5_CFG_C_BLE_ENABLE 0x08
190 #define C3DHALL5_CFG_C_SELF_TEST 0x02
191 #define C3DHALL5_CFG_C_DRDY_ON_PIN 0x01
192 
198 #define C3DHALL5_INT_CTRL_X_AXIS_ENABLE 0x80
199 #define C3DHALL5_INT_CTRL_Y_AXIS_ENABLE 0x40
200 #define C3DHALL5_INT_CTRL_Z_AXIS_ENABLE 0x20
201 #define C3DHALL5_INT_CTRL_IEA_0_SIGNALS_AN_INT 0x00
202 #define C3DHALL5_INT_CTRL_IEA_1_SIGNALS_AN_INT 0x04
203 #define C3DHALL5_INT_CTRL_IEL_INT_IS_PILSED 0x00
204 #define C3DHALL5_INT_CTRL_IEL_INT_IS_LATCHED 0x02
205 #define C3DHALL5_INT_CTRL_IEN_INT_ENABLE 0x01
206 #define C3DHALL5_INT_CTRL_IEN_INT_DISABLE 0x00
207 
213 #define C3DHALL5_INT_SOURCE_POS_TH_X 0x80
214 #define C3DHALL5_INT_SOURCE_POS_TH_Y 0x40
215 #define C3DHALL5_INT_SOURCE_POS_TH_Z 0x20
216 #define C3DHALL5_INT_SOURCE_NEG_TH_X 0x10
217 #define C3DHALL5_INT_SOURCE_NEG_TH_Y 0x08
218 #define C3DHALL5_INT_SOURCE_NEG_TH_N 0x04
219 
225 #define C3DHALL5_STATUS_XYZ_DATA_OVERRUN 0x80
226 #define C3DHALL5_STATUS_Z_DATA_OVERRUN 0x40
227 #define C3DHALL5_STATUS_Y_DATA_OVERRUN 0x20
228 #define C3DHALL5_STATUS_X_DATA_OVERRUN 0x10
229 #define C3DHALL5_STATUS_XYZ_NEW_DATA 0x08
230 #define C3DHALL5_STATUS_Z_NEW_DATA 0x04
231 #define C3DHALL5_STATUS_Y_NEW_DATA 0x02
232 #define C3DHALL5_STATUS_X_NEW_DATA 0x01
233  // End group macro
236 // --------------------------------------------------------------- PUBLIC TYPES
245 typedef uint8_t c3dhall5_select_t;
246 
250 typedef void ( *c3dhall5_master_io_t )( struct c3dhall5_s*, uint8_t, uint8_t*, uint8_t );
251 
255 typedef struct c3dhall5_s
256 {
257  // Output pins
258  digital_out_t css;
259 
260  // Input pins
261 
262  digital_in_t int_pin;
263 
264  // Modules
265 
266  i2c_master_t i2c;
267  spi_master_t spi;
268 
269  // ctx variable
270 
271  uint8_t slave_address;
272  pin_name_t chip_select;
276 
278 
282 typedef struct
283 {
284  // Communication gpio pins
285 
286  pin_name_t scl;
287  pin_name_t sda;
288  pin_name_t miso;
289  pin_name_t mosi;
290  pin_name_t sck;
291  pin_name_t cs;
292 
293  // Additional gpio pins
294 
295  pin_name_t css;
296  pin_name_t int_pin;
297 
298  // static variable
299 
300  uint32_t i2c_speed;
301  uint8_t i2c_address;
302 
303  uint32_t spi_speed;
304  spi_master_mode_t spi_mode;
305  spi_master_chip_select_polarity_t cs_polarity;
306 
308 
310  // End types group
312 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
318 #ifdef __cplusplus
319 extern "C"{
320 #endif
321 
331 
340 
356 
367 void c3dhall5_generic_write ( c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
368 
379 void c3dhall5_generic_read ( c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
380 
390 
400 
408 
416 void c3dhall5_set_offset ( c3dhall5_t *ctx, uint8_t offset_axis, int16_t offset );
417 
425 int16_t c3dhall5_get_axis_data ( c3dhall5_t *ctx, uint8_t axis );
426 
427 #ifdef __cplusplus
428 }
429 #endif
430 #endif // _C3DHALL5_H_
431  // End public_function group
434 
435 // ------------------------------------------------------------------------- END
c3dhall5_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: c3dhall5.h:305
c3dhall5_cfg_t::sda
pin_name_t sda
Definition: c3dhall5.h:287
c3dhall5_s::master_sel
c3dhall5_select_t master_sel
Definition: c3dhall5.h:275
c3dhall5_s::chip_select
pin_name_t chip_select
Definition: c3dhall5.h:272
c3dhall5_cfg_t::scl
pin_name_t scl
Definition: c3dhall5.h:286
c3dhall5_generic_write
void c3dhall5_generic_write(c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
c3dhall5_s::slave_address
uint8_t slave_address
Definition: c3dhall5.h:271
c3dhall5_master_io_t
void(* c3dhall5_master_io_t)(struct c3dhall5_s *, uint8_t, uint8_t *, uint8_t)
Master Input/Output type.
Definition: c3dhall5.h:250
c3dhall5_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: c3dhall5.h:304
c3dhall5_get_axis_data
int16_t c3dhall5_get_axis_data(c3dhall5_t *ctx, uint8_t axis)
Axis data.
c3dhall5_select_t
uint8_t c3dhall5_select_t
Communication type.
Definition: c3dhall5.h:245
c3dhall5_cfg_t::miso
pin_name_t miso
Definition: c3dhall5.h:288
c3dhall5_get_temperature_data
float c3dhall5_get_temperature_data(c3dhall5_t *ctx)
Temperature data.
c3dhall5_get_device_id
uint8_t c3dhall5_get_device_id(c3dhall5_t *ctx)
Device ID.
c3dhall5_s::spi
spi_master_t spi
Definition: c3dhall5.h:267
c3dhall5_cfg_t::mosi
pin_name_t mosi
Definition: c3dhall5.h:289
c3dhall5_s
Click ctx object definition.
Definition: c3dhall5.h:256
c3dhall5_s::write_f
c3dhall5_master_io_t write_f
Definition: c3dhall5.h:273
c3dhall5_s::css
digital_out_t css
Definition: c3dhall5.h:258
c3dhall5_set_offset
void c3dhall5_set_offset(c3dhall5_t *ctx, uint8_t offset_axis, int16_t offset)
Set offest.
c3dhall5_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: c3dhall5.h:300
c3dhall5_cfg_t::spi_speed
uint32_t spi_speed
Definition: c3dhall5.h:303
c3dhall5_s::i2c
i2c_master_t i2c
Definition: c3dhall5.h:266
c3dhall5_cfg_t::cs
pin_name_t cs
Definition: c3dhall5.h:291
c3dhall5_s::int_pin
digital_in_t int_pin
Definition: c3dhall5.h:262
c3dhall5_init
C3DHALL5_RETVAL c3dhall5_init(c3dhall5_t *ctx, c3dhall5_cfg_t *cfg)
Initialization function.
c3dhall5_cfg_t::int_pin
pin_name_t int_pin
Definition: c3dhall5.h:296
c3dhall5_get_interrupt_state
uint8_t c3dhall5_get_interrupt_state(c3dhall5_t *ctx)
Interrupt state.
c3dhall5_default_cfg
void c3dhall5_default_cfg(c3dhall5_t *ctx)
Click Default Configuration function.
c3dhall5_cfg_t
Click configuration structure definition.
Definition: c3dhall5.h:283
c3dhall5_cfg_t::sck
pin_name_t sck
Definition: c3dhall5.h:290
c3dhall5_t
struct c3dhall5_s c3dhall5_t
Click ctx object definition.
C3DHALL5_RETVAL
#define C3DHALL5_RETVAL
Definition: c3dhall5.h:87
c3dhall5_cfg_t::css
pin_name_t css
Definition: c3dhall5.h:295
c3dhall5_generic_read
void c3dhall5_generic_read(c3dhall5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
c3dhall5_cfg_setup
void c3dhall5_cfg_setup(c3dhall5_cfg_t *cfg)
Config Object Initialization function.
c3dhall5_cfg_t::sel
c3dhall5_select_t sel
Definition: c3dhall5.h:307
c3dhall5_cfg_t::i2c_address
uint8_t i2c_address
Definition: c3dhall5.h:301
c3dhall5_s::read_f
c3dhall5_master_io_t read_f
Definition: c3dhall5.h:274