mram  2.0.0.0
mram.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef MRAM_H
36 #define MRAM_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_spi_master.h"
41 
42 
43 // -------------------------------------------------------------- PUBLIC MACROS
54 #define MRAM_MAP_MIKROBUS( cfg, mikrobus ) \
55  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
56  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
57  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
58  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
59  cfg.wp = MIKROBUS( mikrobus, MIKROBUS_RST ); \
60  cfg.hld = MIKROBUS( mikrobus, MIKROBUS_INT )
61 
67 #define MRAM_RETVAL uint8_t
68 #define MRAM_OK 0x00
69 #define MRAM_INIT_ERROR 0xFF
70 
76 #define MRAM_WRITE_ENABLE_BIT 0x02
77 #define MRAM_MEMORY_BLOCK_BIT0 0x04
78 #define MRAM_MEMORY_BLOCK_BIT1 0x08
79 #define MRAM_STATUS_WRITE_DISABLE_BIT 0x80
80 #define MRAM_FIRST_ADDRESS_LOCATION 0x0000
81 #define MRAM_ADDRESS_LOCATION_0 0x000F
82 #define MRAM_ADDRESS_LOCATION_1 0x00FF
83 #define MRAM_ADDRESS_LOCATION_2 0x0FFF
84 #define MRAM_LAST_ADDRESS_LOCATION 0x7FFF
85 #define MRAM_LOGIC_HIGH 0x01
86 #define MRAM_LOGIC_LOW 0x00
87 #define MRAM_NONE_PROTECTED_MEMORY 0x82
88 #define MRAM_UPPER_QUARTER_PROTECTED_MEMORY 0x86
89 #define MRAM_UPPER_HALF_PROTECTED_MEMORY 0x8A
90 #define MRAM_ALL_PROTECTED_MEMORY 0x8E
91  // End group macro
94 // --------------------------------------------------------------- PUBLIC TYPES
103 typedef struct
104 {
105  // Output pins
106 
107  digital_out_t wp;
108  digital_out_t hld;
109  digital_out_t cs;
110 
111  // Modules
112  spi_master_t spi;
113  pin_name_t chip_select;
114 
115 } mram_t;
116 
120 typedef struct
121 {
122  // Communication gpio pins
123 
124  pin_name_t miso;
125  pin_name_t mosi;
126  pin_name_t sck;
127  pin_name_t cs;
128 
129  // Additional gpio pins
130 
131  pin_name_t wp;
132  pin_name_t hld;
133 
134  // static variable
135 
136  uint32_t spi_speed;
137  uint8_t spi_mode;
138  spi_master_chip_select_polarity_t cs_polarity;
139 
140 } mram_cfg_t;
141  // End types group
143 
144 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
145 
150 #ifdef __cplusplus
151 extern "C"{
152 #endif
153 
162 void mram_cfg_setup ( mram_cfg_t *cfg );
163 
171 MRAM_RETVAL mram_init ( mram_t *ctx, mram_cfg_t *cfg );
172 
180 void mram_default_cfg ( mram_t *ctx );
181 
194 (
195  mram_t *ctx,
196  uint8_t *wr_buf,
197  uint16_t wr_len,
198  uint8_t *rd_buf,
199  uint16_t rd_len
200 );
201 
211 uint8_t mram_read_status_reg ( mram_t *ctx );
212 
223 uint8_t mram_check_status_bit (mram_t *ctx, uint8_t status_bit );
224 
234 uint8_t mram_enable_write (mram_t *ctx );
235 
245 uint8_t mram_disable_write ( mram_t *ctx );
246 
256 void mram_write_status_reg ( mram_t *ctx, uint8_t transfer_data);
257 
269 void mram_read_data_bytes ( mram_t *ctx, const uint16_t address, uint8_t *buffer, const uint16_t n_bytes );
270 
282 void mram_write_data_bytes ( mram_t *ctx, const uint16_t address, uint8_t *buffer, const uint16_t n_bytes );
283 
292 void mram_enter_sleep_mode ( mram_t *ctx );
293 
302 void mram_wake_up_mode ( mram_t *ctx );
303 
313 void mram_enable_write_protect ( mram_t *ctx, uint8_t state);
314 
324 void mram_enable_hold_mode ( mram_t *ctx, uint8_t state);
325 
326 #ifdef __cplusplus
327 }
328 #endif
329 #endif // _MRAM_H_
330  // End public_function group
333 
334 // ------------------------------------------------------------------------- END
mram_disable_write
uint8_t mram_disable_write(mram_t *ctx)
Disable write.
mram_read_data_bytes
void mram_read_data_bytes(mram_t *ctx, const uint16_t address, uint8_t *buffer, const uint16_t n_bytes)
Read n byte data.
mram_cfg_t::spi_mode
uint8_t spi_mode
Definition: mram.h:137
mram_t::hld
digital_out_t hld
Definition: mram.h:108
mram_cfg_t::cs
pin_name_t cs
Definition: mram.h:127
mram_cfg_t::mosi
pin_name_t mosi
Definition: mram.h:125
mram_t::spi
spi_master_t spi
Definition: mram.h:112
mram_t::cs
digital_out_t cs
Definition: mram.h:109
mram_cfg_t::wp
pin_name_t wp
Definition: mram.h:131
mram_generic_transfer
void mram_generic_transfer(mram_t *ctx, uint8_t *wr_buf, uint16_t wr_len, uint8_t *rd_buf, uint16_t rd_len)
Generic transfer function.
mram_enable_hold_mode
void mram_enable_hold_mode(mram_t *ctx, uint8_t state)
Enable hold mode.
mram_t
Click ctx object definition.
Definition: mram.h:103
mram_init
MRAM_RETVAL mram_init(mram_t *ctx, mram_cfg_t *cfg)
Initialization function.
mram_t::chip_select
pin_name_t chip_select
Definition: mram.h:113
mram_cfg_t
Click configuration structure definition.
Definition: mram.h:120
mram_wake_up_mode
void mram_wake_up_mode(mram_t *ctx)
Wake up.
mram_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: mram.h:138
mram_write_status_reg
void mram_write_status_reg(mram_t *ctx, uint8_t transfer_data)
Write status reg.
mram_cfg_t::sck
pin_name_t sck
Definition: mram.h:126
mram_enable_write
uint8_t mram_enable_write(mram_t *ctx)
Enable write.
mram_cfg_setup
void mram_cfg_setup(mram_cfg_t *cfg)
Config Object Initialization function.
mram_cfg_t::miso
pin_name_t miso
Definition: mram.h:124
mram_enter_sleep_mode
void mram_enter_sleep_mode(mram_t *ctx)
Sleep mode.
MRAM_RETVAL
#define MRAM_RETVAL
Definition: mram.h:67
mram_write_data_bytes
void mram_write_data_bytes(mram_t *ctx, const uint16_t address, uint8_t *buffer, const uint16_t n_bytes)
Write n byte data.
mram_cfg_t::hld
pin_name_t hld
Definition: mram.h:132
mram_t::wp
digital_out_t wp
Definition: mram.h:107
mram_default_cfg
void mram_default_cfg(mram_t *ctx)
Click Default Configuration function.
mram_cfg_t::spi_speed
uint32_t spi_speed
Definition: mram.h:136
mram_read_status_reg
uint8_t mram_read_status_reg(mram_t *ctx)
Read status reg.
mram_check_status_bit
uint8_t mram_check_status_bit(mram_t *ctx, uint8_t status_bit)
Check status bit.
mram_enable_write_protect
void mram_enable_write_protect(mram_t *ctx, uint8_t state)
Enable write protection.