balancer5 2.0.0.0
balancer5.h
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1/*
2 * MikroSDK - MikroE Software Development Kit
3 * Copyright© 2020 MikroElektronika d.o.o.
4 *
5 * Permission is hereby granted, free of charge, to any person
6 * obtaining a copy of this software and associated documentation
7 * files (the "Software"), to deal in the Software without restriction,
8 * including without limitation the rights to use, copy, modify, merge,
9 * publish, distribute, sublicense, and/or sell copies of the Software,
10 * and to permit persons to whom the Software is furnished to do so,
11 * subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22 * OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
33// ----------------------------------------------------------------------------
34
35#ifndef BALANCER5_H
36#define BALANCER5_H
37
38#include "drv_digital_out.h"
39#include "drv_digital_in.h"
40#include "drv_i2c_master.h"
41
42
43// -------------------------------------------------------------- PUBLIC MACROS
53#define BALANCER5_MAP_MIKROBUS( cfg, mikrobus ) \
54 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
55 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
56 cfg.pg = MIKROBUS( mikrobus, MIKROBUS_AN ); \
57 cfg.pss = MIKROBUS( mikrobus, MIKROBUS_RST ); \
58 cfg.cd = MIKROBUS( mikrobus, MIKROBUS_CS ); \
59 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
66#define BALANCER5_RETVAL uint8_t
67
68#define BALANCER5_OK 0x00
69#define BALANCER5_INIT_ERROR 0xFF
76#define BALANCER5_REG_CELL_V_LIMIT 0x00
77#define BALANCER5_REG_CHARGE_CURR_LIMIT 0x01
78#define BALANCER5_REG_INPUT_V_LIMIT 0x02
79#define BALANCER5_REG_INPUT_CURR_LIMIT 0x03
80#define BALANCER5_REG_PRECHARGE_N_TERMINATION_CTRL 0x04
81#define BALANCER5_REG_CHARGER_CTRL_1 0x05
82#define BALANCER5_REG_CHARGER_CTRL_2 0x06
83#define BALANCER5_REG_CHARGER_CTRL_3 0x07
84#define BALANCER5_REG_CHARGER_CTRL_4 0x08
85#define BALANCER5_REG_ICO_CURR_LIMIT 0x0A
86#define BALANCER5_REG_CHARGER_STATUS_1 0x0B
87#define BALANCER5_REG_CHARGER_STATUS_2 0x0C
88#define BALANCER5_REG_NTC_STATUS 0x0D
89#define BALANCER5_REG_FAULT_STATUS 0x0E
90#define BALANCER5_REG_CHARGER_FLAG_1 0x0F
91#define BALANCER5_REG_CHARGER_FLAG_2 0x10
92#define BALANCER5_REG_FAULT_FLAG 0x11
93#define BALANCER5_REG_CHARGER_MASK_1 0x12
94#define BALANCER5_REG_CHARGER_MASK_2 0x13
95#define BALANCER5_REG_FAULT_MASK 0x14
96#define BALANCER5_REG_ADC_CTRL 0x15
97#define BALANCER5_REG_ADC_FUNCTION_DISABLE 0x16
98#define BALANCER5_REG_IBUS_ADC1 0x17
99#define BALANCER5_REG_IBUS_ADC0 0x18
100#define BALANCER5_REG_ICHG_ADC1 0x19
101#define BALANCER5_REG_ICHG_ADC0 0x1A
102#define BALANCER5_REG_VBUS_ADC1 0x1B
103#define BALANCER5_REG_VBUS_ADC0 0x1C
104#define BALANCER5_REG_VBAT_ADC1 0x1D
105#define BALANCER5_REG_VBAT_ADC0 0x1E
106#define BALANCER5_REG_VCELLTOP_ADC1 0x1F
107#define BALANCER5_REG_VCELLTOP_ADC0 0x20
108#define BALANCER5_REG_TS_ADC1 0x21
109#define BALANCER5_REG_TS_ADC0 0x22
110#define BALANCER5_REG_TDIE_ADC1 0x23
111#define BALANCER5_REG_TDIE_ADC0 0x24
112#define BALANCER5_REG_PART_INFO 0x25
113#define BALANCER5_REG_VCELLBOT_ADC1 0x26
114#define BALANCER5_REG_VCELLBOT_ADC0 0x27
115#define BALANCER5_REG_CELL_BALANCING_CTRL1 0x28
116#define BALANCER5_REG_CELL_BALANCING_CTRL2 0x29
117#define BALANCER5_REG_CELL_BALANCING_STATUS_N_CNTRL 0x2A
118#define BALANCER5_REG_CELL_BALANCING_FLAG 0x2B
119#define BALANCER5_REG_CELL_BALANCING_MASK 0x2C
126#define BALANCER5_ERROR_ID 0xAA
127#define BALANCER5_SUCCESSFUL 0xFF
134#define BALANCER5_DEVICE_ID 0x29
140#define BALANCER5_PIN_STATUS_HIGH 1
141#define BALANCER5_PIN_STATUS_LOW 0
147#define BALANCER5_CHARGE_OFF 1
148#define BALANCER5_CHARGE_ON 0
154#define BALANCER5_ADC_CTRL_ENABLE 0x80
155#define BALANCER5_ADC_CTRL_DISABLE 0x00
156#define BALANCER5_ADC_CTRL_CONT_CONV 0x00
157#define BALANCER5_ADC_CTRL_ONE_SHOT_CONV 0x40
158#define BALANCER5_ADC_CTRL_15BIT_RES 0x00
159#define BALANCER5_ADC_CTRL_14BIT_RES 0x10
160#define BALANCER5_ADC_CTRL_13BIT_RES 0x20
161#define BALANCER5_ADC_CTRL_12BIT_RES 0x30
167#define BALANCER5_CS1_IINDPM_NORMAL 0x00
168#define BALANCER5_CS1_IINDPM_IN_REGULATION 0x40
169#define BALANCER5_CS1_VINDPM_NORMAL 0x00
170#define BALANCER5_CS1_VINDPM_IN_REGULATION 0x20
171#define BALANCER5_CS1_IC_NORMAL 0x00
172#define BALANCER5_CS1_IC_IN_THERMAL_REGULATION 0x10
173#define BALANCER5_CS1_WD_NORMAL 0x00
174#define BALANCER5_CS1_WD_TIMER_EXPIRED 0x08
175#define BALANCER5_CS1_NOT_CHARGING 0x00
176#define BALANCER5_CS1_TRICKLE_CHARGE 0x01
177#define BALANCER5_CS1_PRE_CHARGE 0x02
178#define BALANCER5_CS1_FAST_CHARGE 0x03
179#define BALANCER5_CS1_TAPER_CHARGE 0x04
180#define BALANCER5_CS1_TOP_OFF_TIMER_CHARGE 0x05
181#define BALANCER5_CS1_CHARGE_TERMINATION 0x06
187#define BALANCER5_CS2_POWER_GOOD 0x80
188#define BALANCER5_CS2_POWER_NOT_GOOD 0x00
189#define BALANCER5_CS2_NO_INPUT 0x00
190#define BALANCER5_CS2_USB_HOST_SDP 0x10
191#define BALANCER5_CS2_USB_CDP 0x20
192#define BALANCER5_CS2_ADAPTER 0x30
193#define BALANCER5_CS2_POORSRC 0x40
194#define BALANCER5_CS2_UNKNOWN_ADAPTER 0x50
195#define BALANCER5_CS2_NON_STANDARD_ADAPTER 0x60
196#define BALANCER5_CS2_ICO_DISABLED 0x00
197#define BALANCER5_CS2_ICO_OPTIMIZATION_IN_PROGRESS 0x02
198#define BALANCER5_CS2_MAX_INPUT 0x04
204#define BALANCER5_SLAVE_ADDRESS 0x6A // End group macro
209// --------------------------------------------------------------- PUBLIC TYPES
218typedef struct
219{
220 // Output pins
221
222 digital_out_t cd;
223
224
225 // Input pins
226
227 digital_in_t pg;
228 digital_in_t pss;
229 digital_in_t int_pin;
230
231 // Modules
232
233 i2c_master_t i2c;
234
235 // ctx variable
236
238
240
244typedef struct
245{
246 // Communication gpio pins
247
248 pin_name_t scl;
249 pin_name_t sda;
250
251 // Additional gpio pins
252
253 pin_name_t pg;
254 pin_name_t pss;
255 pin_name_t cd;
256 pin_name_t int_pin;
257
258 // static variable
259
260 uint32_t i2c_speed;
261 uint8_t i2c_address;
262
264 // End types group
266
267// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
268
274#ifdef __cplusplus
275extern "C"{
276#endif
277
287
296
310
321void balancer5_generic_write ( balancer5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
322
334void balancer5_generic_read ( balancer5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
335
346uint8_t balancer5_read_data( balancer5_t *ctx, uint8_t reg_addr );
347
348
358void balancer5_write_data ( balancer5_t *ctx, uint8_t reg_addr, uint8_t write_data );
359
368void balancer5_charge ( balancer5_t *ctx, uint8_t state );
369
380
391
402
413
414
415#ifdef __cplusplus
416}
417#endif
418#endif // _BALANCER5_H_
419 // End public_function group
422
423// ------------------------------------------------------------------------- END
#define BALANCER5_RETVAL
Definition: balancer5.h:66
BALANCER5_RETVAL balancer5_init(balancer5_t *ctx, balancer5_cfg_t *cfg)
Initialization function.
void balancer5_write_data(balancer5_t *ctx, uint8_t reg_addr, uint8_t write_data)
Generic function for writing one Byte data to registar.
void balancer5_cfg_setup(balancer5_cfg_t *cfg)
Config Object Initialization function.
void balancer5_default_cfg(balancer5_t *ctx)
Click Default Configuration function.
void balancer5_charge(balancer5_t *ctx, uint8_t state)
Function for setting charging status.
uint8_t balancer5_get_power_source_status(balancer5_t *ctx)
Gets state of the psel pin on rst.
void balancer5_generic_read(balancer5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
uint8_t balancer5_read_data(balancer5_t *ctx, uint8_t reg_addr)
Generic function for reading one Byte data from registar.
uint8_t balancer5_get_int_status(balancer5_t *ctx)
Gets state of the int pin.
uint8_t balancer5_get_power_good_status(balancer5_t *ctx)
Gets state of the pg pin on an.
void balancer5_generic_write(balancer5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
uint8_t balancer5_check_id(balancer5_t *ctx)
Checks if device ID is good.
Click configuration structure definition.
Definition: balancer5.h:245
pin_name_t pss
Definition: balancer5.h:254
uint32_t i2c_speed
Definition: balancer5.h:260
pin_name_t cd
Definition: balancer5.h:255
pin_name_t scl
Definition: balancer5.h:248
pin_name_t int_pin
Definition: balancer5.h:256
pin_name_t sda
Definition: balancer5.h:249
pin_name_t pg
Definition: balancer5.h:253
uint8_t i2c_address
Definition: balancer5.h:261
Click ctx object definition.
Definition: balancer5.h:219
digital_in_t pss
Definition: balancer5.h:228
digital_out_t cd
Definition: balancer5.h:222
digital_in_t int_pin
Definition: balancer5.h:229
i2c_master_t i2c
Definition: balancer5.h:233
uint8_t slave_address
Definition: balancer5.h:237
digital_in_t pg
Definition: balancer5.h:227