ecg3  2.0.0.0
ecg3.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ECG3_H
36 #define ECG3_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_spi_master.h"
41 
42 // -------------------------------------------------------------- PUBLIC MACROS
53 #define ECG3_MAP_MIKROBUS( cfg, mikrobus ) \
54  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
55  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
56  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
57  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
58  cfg.clk = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
59  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
60 
66 #define ECG3_RETVAL uint8_t
67 
68 #define ECG3_OK 0x00
69 #define ECG3_INIT_ERROR 0xFF
70 
77 #define ECG3_NO_OP_REG 0x00
78 #define ECG3_STAT_REG 0x01
79 #define ECG3_EN_INT_REG 0x02
80 #define ECG3_EN_INT2_REG 0x03
81 #define ECG3_MNGR_INT_REG 0x04
82 #define ECG3_MNGR_DYN_REG 0x05
83 #define ECG3_SW_RST_REG 0x08
84 #define ECG3_SYNC_REG 0x09
85 #define ECG3_FIFO_RST_REG 0x0A
86 #define ECG3_INFO_REG 0x0F
87 #define ECG3_CNFG_GEN_REG 0x10
88 #define ECG3_CNFG_CAL_REG 0x12
89 #define ECG3_CNFG_EMUX_REG 0x14
90 #define ECG3_CNFG_ECG_REG 0x15
91 #define ECG3_CNFG_RTOR1_REG 0x1D
92 #define ECG3_CNFG_RTOR2_REG 0x1E
93 #define ECG3_ECG_FIFO_BURST_REG 0x20
94 #define ECG3_ECG_FIFO_REG 0x21
95 #define ECG3_RTOR_REG 0x25
96 #define ECG3_NO_OP2_REG 0x7F
97 
103 #define ECG3_EINT_MASK 0x800000
104 #define ECG3_EOVF_MASK 0x400000
105 #define ECG3_FSTINT_MASK 0x200000
106 #define ECG3_DCLOFF_INT_MASK 0x100000
107 #define ECG3_LONINT_MASK 0x000800
108 #define ECG3_RRINT_MASK 0x000400
109 #define ECG3_SAMP_INT_MASK 0x000200
110 #define ECG3_PLLINT_MASK 0x000100
111 #define ECG3_LDOFF_PH_INT_MASK 0x000008
112 #define ECG3_LDOFF_PL_INT_MASK 0x000004
113 #define ECG3_LDOFF_NH_INT_MASK 0x000002
114 #define ECG3_LDOFF_NL_INT_MASK 0x000001
115 
121 #define ECG3_INTB_DIS 0x000000
122 #define ECG3_INTB_CMOS 0x000001
123 #define ECG3_INTB_OD_NMOS 0x000002
124 #define ECG3_INTB_OD_NMOS_INTER_PULLUP 0x000003
125 
131 #define ECG3_FSINT_CLR_DISENGAGED 0x000000
132 #define ECG3_FSINT_CLR_STAT 0x000040
133 #define ECG3_RRINT_CLR_STAT 0x000000
134 #define ECG3_RRINT_CLR_RTOR 0x000010
135 #define ECG3_RRINT_SELF_CLR 0x000020
136 #define ECG3_SAMP_CLR_STAT 0x000000
137 #define ECG3_SAMP_SELF_CLR 0x000004
138 #define ECG3_SAMP_FREQ_1_SAMP 0x000000
139 #define ECG3_SAMP_FREQ_2_SAMP 0x000001
140 #define ECG3_SAMP_FREQ_4_SAMP 0x000002
141 #define ECG3_SAMP_FREQ_16_SAMP 0x000003
142 
148 #define ECG3_NORMAL_MODE 0x000000
149 #define ECG3_MANUAL_FAST_MODE 0x400000
150 #define ECG3_AUTO_FAST_MODE 0x800000
151 
157 #define ECG3_SW_RST_CMD 0x000000
158 #define ECG3_FIFO_RST_CMD 0x000000
159 #define ECG3_SYNCH_CMD 0x000000
160 
166 #define ECG3_ULP_LON_EN 0x400000
167 #define ECG3_FMSTR_32768HZ_ECG_512HZ 0x000000
168 #define ECG3_FMSTR_32000HZ_ECG_500HZ 0x100000
169 #define ECG3_FMSTR_32000HZ_ECG_200HZ 0x200000
170 #define ECG3_FMSTR_31968HZ_ECG_199HZ 0x300000
171 #define ECG3_ECG_CHANN_EN 0x080000
172 #define ECG3_DCLOFF_EN 0x001000
173 #define ECG3_ECGP_PULLUP 0x000000
174 #define ECG3_ECGP_PULLDOWN 0x000800
175 #define ECG3_DCLOFF_IMAG_0NA 0x000000
176 #define ECG3_DCLOFF_IMAG_5NA 0x000100
177 #define ECG3_DCLOFF_IMAG_10NA 0x000200
178 #define ECG3_DCLOFF_IMAG_20NA 0x000300
179 #define ECG3_DCLOFF_IMAG_50NA 0x000400
180 #define ECG3_DCLOFF_IMAG_100NA 0x000500
181 #define ECG3_DCLOFF_VTH_300MV 0x000000
182 #define ECG3_DCLOFF_VTH_400MV 0x000040
183 #define ECG3_DCLOFF_VTH_450MV 0x000080
184 #define ECG3_DCLOFF_VTH_500MV 0x0000C0
185 #define ECG3_RBIAS_EN 0x000010
186 #define ECG3_RBIAS_50M_OHM 0x000000
187 #define ECG3_RBIAS_100M_OHM 0x000004
188 #define ECG3_RBIAS_200M_OHM 0x000008
189 #define ECG3_RBIASP_EN 0x000002
190 #define ECG3_RBIASN_EN 0x000001
191 
197 #define ECG3_VCAL_EN 0x400000
198 #define ECG3_VMODE_UNIPOL 0x000000
199 #define ECG3_VMODE_BIPOL 0x200000
200 #define ECG3_VMAG_250MICROV 0x000000
201 #define ECG3_VMAG_500MICROV 0x100000
202 #define ECG3_FCAL_256HZ 0x000000
203 #define ECG3_FCAL_64HZ 0x001000
204 #define ECG3_FCAL_16HZ 0x002000
205 #define ECG3_FCAL_4HZ 0x003000
206 #define ECG3_FCAL_1HZ 0x004000
207 #define ECG3_FCAL_1PER4HZ 0x005000
208 #define ECG3_FCAL_1PER16HZ 0x006000
209 #define ECG3_FCAL_1PER64HZ 0x007000
210 #define ECG3_FIFTY_CAL_THIGH 0x000000
211 #define ECG3_FIFTY_50PERCENTS 0x000800
212 
218 #define ECG3_INPUT_NON_INV 0x000000
219 #define ECG3_INPUT_INV 0x800000
220 #define ECG3_ECGP_EN 0x000000
221 #define ECG3_ECGP_DIS 0x200000
222 #define ECG3_ECGN_EN 0x000000
223 #define ECG3_ECGN_DIS 0x100000
224 #define ECG3_ECGP_NO_CAL 0x000000
225 #define ECG3_ECGP_CAL_VMID 0x040000
226 #define ECG3_ECGP_CAL_VCALP 0x080000
227 #define ECG3_ECGP_CAL_VCALN 0x0C0000
228 #define ECG3_ECGN_NO_CAL 0x000000
229 #define ECG3_ECGN_CAL_VMID 0x010000
230 #define ECG3_ECGN_CAL_VCALP 0x020000
231 #define ECG3_ECGN_CAL_VCALN 0x030000
232 
238 #define ECG3_GAIN_20VPERV 0x000000
239 #define ECG3_GAIN_40VPERV 0x010000
240 #define ECG3_GAIN_80VPERV 0x020000
241 #define ECG3_GAIN_160VPERV 0x030000
242 #define ECG3_DHPF_BYPASS_DC 0x000000
243 #define ECG3_DHPF_500MILIHZ 0x004000
244 #define ECG3_DLPF_BYPASS 0x000000
245 #define ECG3_DLPF_40HZ 0x001000
246 #define ECG3_DLPF_100HZ 0x002000
247 #define ECG3_DLPF_150HZ 0x003000
248 
254 #define ECG3_WNDW_6 0x000000
255 #define ECG3_WNDW_8 0x100000
256 #define ECG3_WNDW_10 0x200000
257 #define ECG3_WNDW_12 0x300000
258 #define ECG3_WNDW_14 0x400000
259 #define ECG3_WNDW_16 0x500000
260 #define ECG3_WNDW_18 0x600000
261 #define ECG3_WNDW_20 0x700000
262 #define ECG3_WNDW_22 0x800000
263 #define ECG3_WNDW_24 0x900000
264 #define ECG3_WNDW_26 0xA00000
265 #define ECG3_WNDW_28 0xB00000
266 #define ECG3_RRGAIN_1 0x000000
267 #define ECG3_RRGAIN_2 0x010000
268 #define ECG3_RRGAIN_4 0x020000
269 #define ECG3_RRGAIN_8 0x030000
270 #define ECG3_RRGAIN_16 0x040000
271 #define ECG3_RRGAIN_32 0x050000
272 #define ECG3_RRGAIN_64 0x060000
273 #define ECG3_RRGAIN_128 0x070000
274 #define ECG3_RRGAIN_256 0x080000
275 #define ECG3_RRGAIN_512 0x090000
276 #define ECG3_RRGAIN_1024 0x0A0000
277 #define ECG3_RRGAIN_2048 0x0B0000
278 #define ECG3_RRGAIN_4096 0x0C0000
279 #define ECG3_RRGAIN_8192 0x0D0000
280 #define ECG3_RRGAIN_16384 0x0E0000
281 #define ECG3_RRGAIN_AUTO_SCALE 0x0F0000
282 #define ECG3_RTOR_EN 0x008000
283 #define ECG3_PAVG_2 0x000000
284 #define ECG3_PAVG_4 0x001000
285 #define ECG3_PAVG_8 0x002000
286 #define ECG3_PAVG_16 0x003000
287 
293 #define ECG3_WRONG_ADDR 0x01
294 #define ECG3_OK 0x00
295 #define ECG3_INT_OCCURRED 0x01
296 #define ECG3_INT_NOT_OCCURRED 0x00
297 #define ECG3_DUMMY_BYTE 0x00
298  // End group macro
300 // --------------------------------------------------------------- PUBLIC TYPES
309 typedef struct
310 {
311  // Output pins
312 
313  digital_out_t cs;
314  digital_out_t clk;
315 
316  // Input pins
317 
318  digital_in_t int_pin;
319 
320  // Modules
321 
322  spi_master_t spi;
323  pin_name_t chip_select;
324 
325 } ecg3_t;
326 
330 typedef struct
331 {
332  // Communication gpio pins
333 
334  pin_name_t miso;
335  pin_name_t mosi;
336  pin_name_t sck;
337  pin_name_t cs;
338 
339  // Additional gpio pins
340 
341  pin_name_t clk;
342  pin_name_t int_pin;
343 
344  // static variable
345 
346  uint32_t spi_speed;
347  spi_master_mode_t spi_mode;
348  spi_master_chip_select_polarity_t cs_polarity;
349 
350 } ecg3_cfg_t;
351  // End types group
353 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
354 
359 #ifdef __cplusplus
360 extern "C"{
361 #endif
362 
371 void ecg3_cfg_setup ( ecg3_cfg_t *cfg );
372 
381 ECG3_RETVAL ecg3_init ( ecg3_t *ctx, ecg3_cfg_t *cfg );
382 
390 void ecg3_default_cfg ( ecg3_t *ctx );
391 
403 void ecg3_generic_transfer ( ecg3_t *ctx, uint8_t *wr_buf, uint16_t wr_len, uint8_t *rd_buf, uint16_t rd_len );
404 
416 uint8_t ecg3_write_reg ( ecg3_t *ctx, uint8_t reg_addr, uint32_t data_in );
417 
429 uint8_t ecg3_read_reg ( ecg3_t *ctx, uint8_t reg_addr, uint32_t *data_out );
430 
441 uint8_t ecg3_check_status ( ecg3_t *ctx, uint32_t bit_mask );
442 
450 void ecg3_sw_reset ( ecg3_t *ctx );
451 
459 void ecg3_fifo_reset ( ecg3_t *ctx );
460 
468 void ecg3_sync ( ecg3_t *ctx );
469 
478 void ecg3_get_ecg ( ecg3_t *ctx, uint32_t *out_ecg );
479 
490 void ecg3_get_rtor ( ecg3_t *ctx, uint16_t *out_hr, uint16_t *out_rr );
491 
492 
493 #ifdef __cplusplus
494 }
495 #endif
496 #endif // _ECG3_H_
497  // End public_function group
500 
501 // ------------------------------------------------------------------------- END
ecg3_t::clk
digital_out_t clk
Definition: ecg3.h:314
ecg3_fifo_reset
void ecg3_fifo_reset(ecg3_t *ctx)
FIFO Reset function.
ecg3_generic_transfer
void ecg3_generic_transfer(ecg3_t *ctx, uint8_t *wr_buf, uint16_t wr_len, uint8_t *rd_buf, uint16_t rd_len)
Generic transfer function.
ecg3_cfg_t::miso
pin_name_t miso
Definition: ecg3.h:334
ecg3_cfg_t::int_pin
pin_name_t int_pin
Definition: ecg3.h:342
ecg3_cfg_t::sck
pin_name_t sck
Definition: ecg3.h:336
ecg3_default_cfg
void ecg3_default_cfg(ecg3_t *ctx)
Click Default Configuration function.
ecg3_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: ecg3.h:347
ecg3_write_reg
uint8_t ecg3_write_reg(ecg3_t *ctx, uint8_t reg_addr, uint32_t data_in)
Generic Write function.
ecg3_check_status
uint8_t ecg3_check_status(ecg3_t *ctx, uint32_t bit_mask)
Status Check function.
ecg3_t
Click ctx object definition.
Definition: ecg3.h:309
ecg3_cfg_t
Click configuration structure definition.
Definition: ecg3.h:330
ecg3_read_reg
uint8_t ecg3_read_reg(ecg3_t *ctx, uint8_t reg_addr, uint32_t *data_out)
Generic Read function.
ecg3_sw_reset
void ecg3_sw_reset(ecg3_t *ctx)
SW Reset function.
ecg3_sync
void ecg3_sync(ecg3_t *ctx)
Synchronization function.
ecg3_cfg_t::clk
pin_name_t clk
Definition: ecg3.h:341
ecg3_cfg_t::spi_speed
uint32_t spi_speed
Definition: ecg3.h:346
ecg3_t::cs
digital_out_t cs
Definition: ecg3.h:313
ecg3_cfg_t::mosi
pin_name_t mosi
Definition: ecg3.h:335
ecg3_cfg_t::cs
pin_name_t cs
Definition: ecg3.h:337
ecg3_t::int_pin
digital_in_t int_pin
Definition: ecg3.h:318
ecg3_t::chip_select
pin_name_t chip_select
Definition: ecg3.h:323
ecg3_get_rtor
void ecg3_get_rtor(ecg3_t *ctx, uint16_t *out_hr, uint16_t *out_rr)
RTOR Get function.
ECG3_RETVAL
#define ECG3_RETVAL
Definition: ecg3.h:66
ecg3_t::spi
spi_master_t spi
Definition: ecg3.h:322
ecg3_get_ecg
void ecg3_get_ecg(ecg3_t *ctx, uint32_t *out_ecg)
ECG Get function.
ecg3_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: ecg3.h:348
ecg3_init
ECG3_RETVAL ecg3_init(ecg3_t *ctx, ecg3_cfg_t *cfg)
Initialization function.
ecg3_cfg_setup
void ecg3_cfg_setup(ecg3_cfg_t *cfg)
Config Object Initialization function.