heartrate3  2.0.0.0
heartrate3.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef HEARTRATE3_H
36 #define HEARTRATE3_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_i2c_master.h"
41 
42 // -------------------------------------------------------------- PUBLIC MACROS
52 #define HEARTRATE3_MAP_MIKROBUS( cfg, mikrobus ) \
53  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
54  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
55  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
56  cfg.clk = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
57  cfg.rdy = MIKROBUS( mikrobus, MIKROBUS_INT )
58 
64 #define HEARTRATE3_RETVAL uint8_t
65 
66 #define HEARTRATE3_OK 0x00
67 #define HEARTRATE3_INIT_ERROR 0xFF
68 
74 #define HEARTRATE3_SLAVE_ADDR 0x58
75 
81 #define HEARTRATE3_CONTROL0 0x00
82 #define HEARTRATE3_LED2STC 0x01
83 #define HEARTRATE3_LED2ENDC 0x02
84 #define HEARTRATE3_LED1LEDSTC 0x03
85 #define HEARTRATE3_LED1LEDENDC 0x04
86 #define HEARTRATE3_ALED2STC 0x05
87 #define HEARTRATE3_ALED2ENDC 0x06
88 #define HEARTRATE3_LED1STC 0x07
89 #define HEARTRATE3_LED1ENDC 0x08
90 #define HEARTRATE3_LED2LEDSTC 0x09
91 #define HEARTRATE3_LED2LEDENDC 0x0A
92 #define HEARTRATE3_ALED1STC 0x0B
93 #define HEARTRATE3_ALED1ENDC 0x0C
94 #define HEARTRATE3_LED2CONVST 0x0D
95 #define HEARTRATE3_LED2CONVEND 0x0E
96 #define HEARTRATE3_ALED2CONVST 0x0F
97 #define HEARTRATE3_ALED2CONVEND 0x10
98 #define HEARTRATE3_LED1CONVST 0x11
99 #define HEARTRATE3_LED1CONVEND 0x12
100 #define HEARTRATE3_ALED1CONVST 0x13
101 #define HEARTRATE3_ALED1CONVEND 0x14
102 #define HEARTRATE3_ADCRSTSTCT0 0x15
103 #define HEARTRATE3_ADCRSTENDCT0 0x16
104 #define HEARTRATE3_ADCRSTSTCT1 0x17
105 #define HEARTRATE3_ADCRSTENDCT1 0x18
106 #define HEARTRATE3_ADCRSTSTCT2 0x19
107 #define HEARTRATE3_ADCRSTENDCT2 0x1A
108 #define HEARTRATE3_ADCRSTSTCT3 0x1B
109 #define HEARTRATE3_ADCRSTENDCT3 0x1C
110 #define HEARTRATE3_PRPCOUNT 0x1D
111 #define HEARTRATE3_CONTROL1 0x1E
112 #define HEARTRATE3_TIA_GAIN_SEP 0x20
113 #define HEARTRATE3_TIA_GAIN 0x21
114 #define HEARTRATE3_LEDCNTRL 0x22
115 #define HEARTRATE3_CONTROL2 0x23
116 #define HEARTRATE3_ALARM 0x29
117 #define HEARTRATE3_LED2VAL 0x2A
118 #define HEARTRATE3_ALED2VAL 0x2B
119 #define HEARTRATE3_LED1VAL 0x2C
120 #define HEARTRATE3_ALED1VAL 0x2D
121 #define HEARTRATE3_LED2_ALED2VAL 0x2E
122 #define HEARTRATE3_LED1_ALED1VAL 0x2F
123 #define HEARTRATE3_CONTROL3 0x31
124 #define HEARTRATE3_PDNCYCLESTC 0x32
125 #define HEARTRATE3_PDNCYCLEENDC 0x33
126 #define HEARTRATE3_PROG_TG_STC 0x34
127 #define HEARTRATE3_PROG_TG_ENDC 0x35
128 #define HEARTRATE3_LED3LEDSTC 0x36
129 #define HEARTRATE3_LED3LEDENDC 0x37
130 #define HEARTRATE3_CLKDIV_PRF 0x39
131 #define HEARTRATE3_OFFDAC 0x3A
132 #define HEARTRATE3_DEC 0x3D
133 #define HEARTRATE3_AVG_LED2_ALED2VAL 0x3F
134 #define HEARTRATE3_AVG_LED1_ALED1VAL 0x40
135 
141 #define HEARTRATE3_CONTROL0_CMD 0x000000
142 #define HEARTRATE3_LED2STC_CMD 0x000050
143 #define HEARTRATE3_LED2ENDC_CMD 0x00018F
144 #define HEARTRATE3_LED1LEDSTC_CMD 0x000320
145 #define HEARTRATE3_LED1LEDENDC_CMD 0x0004AF
146 #define HEARTRATE3_ALED2STC_CMD 0x0001E0
147 #define HEARTRATE3_ALED2ENDC_CMD 0x00031F
148 #define HEARTRATE3_LED1STC_CMD 0x000370
149 #define HEARTRATE3_LED1ENDC_CMD 0x0004AF
150 #define HEARTRATE3_LED2LEDSTC_CMD 0x000000
151 #define HEARTRATE3_LED2LEDENDC_CMD 0x00018F
152 #define HEARTRATE3_ALED1STC_CMD 0x0004FF
153 #define HEARTRATE3_ALED1ENDC_CMD 0x00063E
154 #define HEARTRATE3_LED2CONVST_CMD 0x000198
155 #define HEARTRATE3_LED2CONVEND_CMD 0x0005BB
156 #define HEARTRATE3_ALED2CONVST_CMD 0x0005C4
157 #define HEARTRATE3_ALED2CONVEND_CMD 0x0009E7
158 #define HEARTRATE3_LED1CONVST_CMD 0x0009F0
159 #define HEARTRATE3_LED1CONVEND_CMD 0x000E13
160 #define HEARTRATE3_ALED1CONVST_CMD 0x000E1C
161 #define HEARTRATE3_ALED1CONVEND_CMD 0x00123F
162 #define HEARTRATE3_ADCRSTSTCT0_CMD 0x000191
163 #define HEARTRATE3_ADCRSTENDCT0_CMD 0x000197
164 #define HEARTRATE3_ADCRSTSTCT1_CMD 0x0005BD
165 #define HEARTRATE3_ADCRSTENDCT1_CMD 0x0005C3
166 #define HEARTRATE3_ADCRSTSTCT2_CMD 0x0009E9
167 #define HEARTRATE3_ADCRSTENDCT2_CMD 0x0009EF
168 #define HEARTRATE3_ADCRSTSTCT3_CMD 0x000E15
169 #define HEARTRATE3_ADCRSTENDCT3_CMD 0x000E1B
170 #define HEARTRATE3_PRPCOUNT_CMD 0x009C3E
171 #define HEARTRATE3_CONTROL1_CMD 0x000103
172 #define HEARTRATE3_TIA_GAIN_SEP_CMD 0x008003
173 #define HEARTRATE3_TIA_GAIN_CMD 0x000003
174 #define HEARTRATE3_LEDCNTRL_CMD 0x01B6D9
175 #define HEARTRATE3_CONTROL2_CMD 0x104218
176 #define HEARTRATE3_ALARM_CMD 0x000000
177 #define HEARTRATE3_CONTROL3_CMD 0x000000
178 #define HEARTRATE3_PDNCYCLESTC_CMD 0x00155F
179 #define HEARTRATE3_PDNCYCLEENDC_CMD 0x00991E
180 #define HEARTRATE3_PROG_TG_STC_CMD 0x000000
181 #define HEARTRATE3_PROG_TG_ENDC_CMD 0x000000
182 #define HEARTRATE3_LED3LEDSTC_CMD 0x000190
183 #define HEARTRATE3_LED3LEDENDC_CMD 0x00031F
184 #define HEARTRATE3_CLKDIV_PRF_CMD 0x000000
185 #define HEARTRATE3_OFFDAC_CMD 0x000000
186 
192 #define HEARTRATE3_PIN_STATE_LOW 0x00
193 #define HEARTRATE3_PIN_STATE_HIGH 0x01
194  // End group macro
197 // --------------------------------------------------------------- PUBLIC TYPES
206 typedef struct
207 {
208  // Output pins
209 
210  digital_out_t rst;
211  digital_out_t clk;
212 
213  // Input pins
214 
215  digital_in_t rdy;
216 
217  // Modules
218 
219  i2c_master_t i2c;
220 
221  // ctx variable
222 
223  uint8_t slave_address;
224 
225 } heartrate3_t;
226 
230 typedef struct
231 {
232  // Communication gpio pins
233 
234  pin_name_t scl;
235  pin_name_t sda;
236 
237  // Additional gpio pins
238 
239  pin_name_t rst;
240  pin_name_t clk;
241  pin_name_t rdy;
242 
243  // static variable
244 
245  uint32_t i2c_speed;
246  uint8_t i2c_address;
247 
249  // End types group
251 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
252 
258 #ifdef __cplusplus
259 extern "C"{
260 #endif
261 
272 
283 
563 
574 void heartrate3_generic_write ( heartrate3_t *ctx, uint8_t reg,
575  uint8_t *data_buf, uint8_t len );
576 
587 void heartrate3_generic_read ( heartrate3_t *ctx, uint8_t reg,
588  uint8_t *data_buf, uint8_t len );
589 
599 void heartrate3_write_data ( heartrate3_t *ctx, uint8_t reg_adr,
600  uint32_t wr_data );
601 
612 uint32_t heartrate3_read_u32 ( heartrate3_t *ctx, uint8_t reg_adr );
613 
624 uint16_t heartrate3_read_u16 ( heartrate3_t *ctx, uint8_t reg_adr );
625 
634 void heartrate3_rst_state ( heartrate3_t *ctx, uint8_t state );
635 
644 void heartrate3_clk_state ( heartrate3_t *ctx, uint8_t state );
645 
656 
657 
658 #ifdef __cplusplus
659 }
660 #endif
661 #endif // _HEARTRATE3_H_
662  // End public_function group
665 
666 // ------------------------------------------------------------------------- END
heartrate3_t::clk
digital_out_t clk
Definition: heartrate3.h:211
heartrate3_t
Click ctx object definition.
Definition: heartrate3.h:206
heartrate3_cfg_t::sda
pin_name_t sda
Definition: heartrate3.h:235
heartrate3_cfg_t::i2c_address
uint8_t i2c_address
Definition: heartrate3.h:246
heartrate3_default_cfg
void heartrate3_default_cfg(heartrate3_t *ctx)
Click Default Configuration function.
heartrate3_generic_write
void heartrate3_generic_write(heartrate3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
heartrate3_t::rdy
digital_in_t rdy
Definition: heartrate3.h:215
heartrate3_cfg_t::scl
pin_name_t scl
Definition: heartrate3.h:234
heartrate3_cfg_t::rdy
pin_name_t rdy
Definition: heartrate3.h:241
heartrate3_t::rst
digital_out_t rst
Definition: heartrate3.h:210
heartrate3_cfg_t::rst
pin_name_t rst
Definition: heartrate3.h:239
heartrate3_cfg_t::clk
pin_name_t clk
Definition: heartrate3.h:240
heartrate3_t::slave_address
uint8_t slave_address
Definition: heartrate3.h:223
heartrate3_write_data
void heartrate3_write_data(heartrate3_t *ctx, uint8_t reg_adr, uint32_t wr_data)
Write data function.
heartrate3_t::i2c
i2c_master_t i2c
Definition: heartrate3.h:219
heartrate3_init
HEARTRATE3_RETVAL heartrate3_init(heartrate3_t *ctx, heartrate3_cfg_t *cfg)
Initialization function.
heartrate3_clk_state
void heartrate3_clk_state(heartrate3_t *ctx, uint8_t state)
Set Clock pin state.
heartrate3_generic_read
void heartrate3_generic_read(heartrate3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
heartrate3_cfg_t
Click configuration structure definition.
Definition: heartrate3.h:230
heartrate3_check_data_ready
uint8_t heartrate3_check_data_ready(heartrate3_t *ctx)
Check data ready function.
HEARTRATE3_RETVAL
#define HEARTRATE3_RETVAL
Definition: heartrate3.h:64
heartrate3_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: heartrate3.h:245
heartrate3_cfg_setup
void heartrate3_cfg_setup(heartrate3_cfg_t *cfg)
Config Object Initialization function.
heartrate3_read_u16
uint16_t heartrate3_read_u16(heartrate3_t *ctx, uint8_t reg_adr)
Read 16-bit data function.
heartrate3_read_u32
uint32_t heartrate3_read_u32(heartrate3_t *ctx, uint8_t reg_adr)
Read 32-bit data function.
heartrate3_rst_state
void heartrate3_rst_state(heartrate3_t *ctx, uint8_t state)
Set Reset pin state.