38 #include "drv_digital_out.h" 39 #include "drv_digital_in.h" 40 #include "drv_i2c_master.h" 41 #include "drv_spi_master.h" 54 #define C3DHALL3_MAP_MIKROBUS( cfg, mikrobus ) \ 55 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \ 56 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \ 57 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \ 58 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \ 59 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \ 60 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \ 61 cfg.ccs = MIKROBUS( mikrobus, MIKROBUS_RST ); \ 62 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT ); 69 #define C3DHALL3_MASTER_I2C 0 70 #define C3DHALL3_MASTER_SPI 1 77 #define C3DHALL3_RETVAL uint8_t 79 #define C3DHALL3_OK 0x00 80 #define C3DHALL3_INIT_ERROR 0xFF 87 #define C3DHALL3_OFFSET_X_REG_L 0x45 88 #define C3DHALL3_OFFSET_Y_REG_L 0x47 89 #define C3DHALL3_OFFSET_Z_REG_L 0x49 90 #define C3DHALL3_INT_CRTL 0x63 91 #define C3DHALL3_INT_SOURCE 0x64 92 #define C3DHALL3_INT_THS_L 0x65 93 #define C3DHALL3_STATUS 0x67 94 #define C3DHALL3_OUTX_L 0x68 95 #define C3DHALL3_OUTY_L 0x6A 96 #define C3DHALL3_OUTZ_L 0x6C 97 #define C3DHALL3_CONFIGURATION_REGISTER_A 0x60 98 #define C3DHALL3_CONFIGURATION_REGISTER_B 0x61 99 #define C3DHALL3_CONFIGURATION_REGISTER_C 0x62 100 #define C3DHALL3_INTERRUPT_CONTROL 0x63 101 #define C3DHALL3_TEMPERATURE_L 0x6E 102 #define C3DHALL3_TEMPERATURE_H 0x6F 109 #define C3DHALL3_CFGA_TEMPERATURE_COMPENSATION 0x80 110 #define C3DHALL3_CFGA_REBOOT_MEMORY 0x40 111 #define C3DHALL3_CFGA_SOFT_RESET 0x20 112 #define C3DHALL3_CFGA_LOW_POWER_MODE 0x10 113 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_10 0x00 114 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_20 0x04 115 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_50 0x08 116 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_100 0x0C 117 #define C3DHALL3_CFGA_MODE_CONTINIOUS 0x00 118 #define C3DHALL3_CFGA_MODE_SINGLE 0x01 119 #define C3DHALL3_CFGA_MODE_IDLE 0x02 120 #define C3DHALL3_CFGA_MODE_IDLE_DEFAULT 0x03 126 #define C3DHALL3_CFGB_OFFSET_CANCELLATION_SINGLE_MODE 0x10 127 #define C3DHALL3_CFGB_INT_ON_DATAOFF 0x08 128 #define C3DHALL3_CFGB_SET_PULSE_FREQUENCY_EVERY_63_ODR 0x00 129 #define C3DHALL3_CFGB_SET_PULSE_FREQUENCY_AFTER_PD 0x04 130 #define C3DHALL3_CFGB_OFFSET_CANCELLATION 0x02 131 #define C3DHALL3_CFGB_LOW_PASS_FILTER_ODR_2 0x00 132 #define C3DHALL3_CFGB_LOW_PASS_FILTER_ODR_4 0x01 139 #define C3DHALL3_CFGC_INTERRUPT_ON_INT 0x40 140 #define C3DHALL3_CFGC_I2C_DISABLE 0x20 141 #define C3DHALL3_CFGC_ASYNC_DATA_READ 0x10 142 #define C3DHALL3_CFGC_DATA_INVERT 0x08 143 #define C3DHALL3_CFGC_SELF_TEST 0x02 144 #define C3DHALL3_CFGC_DATA_READY_ON_INT 0x01 151 #define C3DHALL3_INTCTRL_INTERRUPT_ON_X_AXIS 0x80 152 #define C3DHALL3_INTCTRL_INTERRUPT_ON_Y_AXIS 0x40 153 #define C3DHALL3_INTCTRL_INTERRUPT_ON_Z_AXIS 0x20 154 #define C3DHALL3_INTCTRL_INTERRUPT_POLARITY_LOW 0x00 155 #define C3DHALL3_INTCTRL_INTERRUPT_POLARITY_HIGH 0x40 156 #define C3DHALL3_INTCTRL_INTERRUPT_BIT_LATCHED 0x00 157 #define C3DHALL3_INTCTRL_INTERRUPT_BIT_PULSED 0x20 158 #define C3DHALL3_INTCTRL_INTERRUPT_ENABLE 0x01 386 #endif // _C3DHALL3_H_ int16_t c3dhall3_read_x(c3dhall3_t *ctx)
Read X value.
uint8_t slave_address
Definition: c3dhall3.h:198
pin_name_t chip_select
Definition: c3dhall3.h:199
uint8_t c3dhall3_select_t
Communication type.
Definition: c3dhall3.h:170
i2c_master_t i2c
Definition: c3dhall3.h:193
C3DHALL3_RETVAL c3dhall3_init(c3dhall3_t *ctx, c3dhall3_cfg_t *cfg)
Initialization function.
uint8_t c3dhall3_read_status(c3dhall3_t *ctx)
Read status register.
void c3dhall3_read_xyz(c3dhall3_t *ctx, int16_t *out_xyz)
Read XYZ value.
void c3dhall3_interrupt_threshold(c3dhall3_t *ctx, uint16_t threshold)
Set Interrupt Threshold.
c3dhall3_master_io_t write_f
Definition: c3dhall3.h:200
void c3dhall3_generic_read(c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
digital_out_t cs
Definition: c3dhall3.h:185
pin_name_t sck
Definition: c3dhall3.h:217
pin_name_t int_pin
Definition: c3dhall3.h:223
pin_name_t scl
Definition: c3dhall3.h:213
uint8_t spi_mode
Definition: c3dhall3.h:230
Click configuration structure definition.
Definition: c3dhall3.h:209
uint32_t i2c_speed
Definition: c3dhall3.h:227
spi_master_t spi
Definition: c3dhall3.h:194
int16_t c3dhall3_read_y(c3dhall3_t *ctx)
Read Y value.
digital_out_t ccs
Definition: c3dhall3.h:184
uint32_t spi_speed
Definition: c3dhall3.h:229
void c3dhall3_write_offset(c3dhall3_t *ctx, uint8_t axis, uint16_t offset)
Write offset value.
spi_master_chip_select_polarity_t cs_polarity
Definition: c3dhall3.h:231
void c3dhall3_cfg_setup(c3dhall3_cfg_t *cfg)
Config Object Initialization function.
c3dhall3_master_io_t read_f
Definition: c3dhall3.h:201
c3dhall3_select_t sel
Definition: c3dhall3.h:233
Click ctx object definition.
Definition: c3dhall3.h:180
#define C3DHALL3_RETVAL
Definition: c3dhall3.h:77
c3dhall3_select_t master_sel
Definition: c3dhall3.h:202
pin_name_t mosi
Definition: c3dhall3.h:216
void c3dhall3_generic_write(c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
pin_name_t sda
Definition: c3dhall3.h:214
void(* c3dhall3_master_io_t)(struct c3dhall3_s *, uint8_t, uint8_t *, uint8_t)
Master Input/Output type.
Definition: c3dhall3.h:175
uint8_t c3dhall3_check_int_pin(c3dhall3_t *ctx)
Check status of the int pin.
int16_t c3dhall3_read_z(c3dhall3_t *ctx)
Read Z value.
void c3dhall3_default_cfg(c3dhall3_t *ctx)
Click Default Configuration function.
pin_name_t cs
Definition: c3dhall3.h:218
pin_name_t miso
Definition: c3dhall3.h:215
digital_in_t int_pin
Definition: c3dhall3.h:189
uint8_t i2c_address
Definition: c3dhall3.h:228
pin_name_t ccs
Definition: c3dhall3.h:222
struct c3dhall3_s c3dhall3_t
Click ctx object definition.
uint8_t c3dhall3_read_interrupt_source(c3dhall3_t *ctx)
Read interrupt source.