c3dhall3  2.0.0.0
c3dhall3.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef C3DHALL3_H
36 #define C3DHALL3_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_i2c_master.h"
41 #include "drv_spi_master.h"
42 
43 // -------------------------------------------------------------- PUBLIC MACROS
54 #define C3DHALL3_MAP_MIKROBUS( cfg, mikrobus ) \
55  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
56  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
57  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
58  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
59  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
60  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
61  cfg.ccs = MIKROBUS( mikrobus, MIKROBUS_RST ); \
62  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT );
63 
69 #define C3DHALL3_MASTER_I2C 0
70 #define C3DHALL3_MASTER_SPI 1
71 
77 #define C3DHALL3_RETVAL uint8_t
78 
79 #define C3DHALL3_OK 0x00
80 #define C3DHALL3_INIT_ERROR 0xFF
81 
87 #define C3DHALL3_OFFSET_X_REG_L 0x45
88 #define C3DHALL3_OFFSET_Y_REG_L 0x47
89 #define C3DHALL3_OFFSET_Z_REG_L 0x49
90 #define C3DHALL3_INT_CRTL 0x63
91 #define C3DHALL3_INT_SOURCE 0x64
92 #define C3DHALL3_INT_THS_L 0x65
93 #define C3DHALL3_STATUS 0x67
94 #define C3DHALL3_OUTX_L 0x68
95 #define C3DHALL3_OUTY_L 0x6A
96 #define C3DHALL3_OUTZ_L 0x6C
97 #define C3DHALL3_CONFIGURATION_REGISTER_A 0x60
98 #define C3DHALL3_CONFIGURATION_REGISTER_B 0x61
99 #define C3DHALL3_CONFIGURATION_REGISTER_C 0x62
100 #define C3DHALL3_INTERRUPT_CONTROL 0x63
101 #define C3DHALL3_TEMPERATURE_L 0x6E
102 #define C3DHALL3_TEMPERATURE_H 0x6F
103 
109 #define C3DHALL3_CFGA_TEMPERATURE_COMPENSATION 0x80
110 #define C3DHALL3_CFGA_REBOOT_MEMORY 0x40
111 #define C3DHALL3_CFGA_SOFT_RESET 0x20
112 #define C3DHALL3_CFGA_LOW_POWER_MODE 0x10
113 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_10 0x00
114 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_20 0x04
115 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_50 0x08
116 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_100 0x0C
117 #define C3DHALL3_CFGA_MODE_CONTINIOUS 0x00
118 #define C3DHALL3_CFGA_MODE_SINGLE 0x01
119 #define C3DHALL3_CFGA_MODE_IDLE 0x02
120 #define C3DHALL3_CFGA_MODE_IDLE_DEFAULT 0x03
121 
126 #define C3DHALL3_CFGB_OFFSET_CANCELLATION_SINGLE_MODE 0x10
127 #define C3DHALL3_CFGB_INT_ON_DATAOFF 0x08
128 #define C3DHALL3_CFGB_SET_PULSE_FREQUENCY_EVERY_63_ODR 0x00
129 #define C3DHALL3_CFGB_SET_PULSE_FREQUENCY_AFTER_PD 0x04
130 #define C3DHALL3_CFGB_OFFSET_CANCELLATION 0x02
131 #define C3DHALL3_CFGB_LOW_PASS_FILTER_ODR_2 0x00
132 #define C3DHALL3_CFGB_LOW_PASS_FILTER_ODR_4 0x01
133 
139 #define C3DHALL3_CFGC_INTERRUPT_ON_INT 0x40
140 #define C3DHALL3_CFGC_I2C_DISABLE 0x20
141 #define C3DHALL3_CFGC_ASYNC_DATA_READ 0x10
142 #define C3DHALL3_CFGC_DATA_INVERT 0x08
143 #define C3DHALL3_CFGC_SELF_TEST 0x02
144 #define C3DHALL3_CFGC_DATA_READY_ON_INT 0x01
145 
151 #define C3DHALL3_INTCTRL_INTERRUPT_ON_X_AXIS 0x80
152 #define C3DHALL3_INTCTRL_INTERRUPT_ON_Y_AXIS 0x40
153 #define C3DHALL3_INTCTRL_INTERRUPT_ON_Z_AXIS 0x20
154 #define C3DHALL3_INTCTRL_INTERRUPT_POLARITY_LOW 0x00
155 #define C3DHALL3_INTCTRL_INTERRUPT_POLARITY_HIGH 0x40
156 #define C3DHALL3_INTCTRL_INTERRUPT_BIT_LATCHED 0x00
157 #define C3DHALL3_INTCTRL_INTERRUPT_BIT_PULSED 0x20
158 #define C3DHALL3_INTCTRL_INTERRUPT_ENABLE 0x01
159  // End group macro
161 // --------------------------------------------------------------- PUBLIC TYPES
170 typedef uint8_t c3dhall3_select_t;
171 
175 typedef void ( *c3dhall3_master_io_t )( struct c3dhall3_s*, uint8_t, uint8_t*, uint8_t );
176 
180 typedef struct c3dhall3_s
181 {
182  // Output pins
183 
184  digital_out_t ccs;
185  digital_out_t cs;
186 
187  // Input pins
188 
189  digital_in_t int_pin;
190 
191  // Modules
192 
193  i2c_master_t i2c;
194  spi_master_t spi;
195 
196  // ctx variable
197 
198  uint8_t slave_address;
199  pin_name_t chip_select;
203 
205 
209 typedef struct
210 {
211  // Communication gpio pins
212 
213  pin_name_t scl;
214  pin_name_t sda;
215  pin_name_t miso;
216  pin_name_t mosi;
217  pin_name_t sck;
218  pin_name_t cs;
219 
220  // Additional gpio pins
221 
222  pin_name_t ccs;
223  pin_name_t int_pin;
224 
225  // static variable
226 
227  uint32_t i2c_speed;
228  uint8_t i2c_address;
229  uint32_t spi_speed;
230  uint8_t spi_mode;
231  spi_master_chip_select_polarity_t cs_polarity;
232 
234 
236 
237 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
243 #ifdef __cplusplus
244 extern "C"{
245 #endif
246 
256 
265 
274 
285 void c3dhall3_generic_write ( c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
286 
297 void c3dhall3_generic_read ( c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
298 
307 
315 int16_t c3dhall3_read_x ( c3dhall3_t *ctx );
316 
324 int16_t c3dhall3_read_y ( c3dhall3_t *ctx );
325 
333 int16_t c3dhall3_read_z ( c3dhall3_t *ctx );
334 
343 void c3dhall3_read_xyz ( c3dhall3_t *ctx, int16_t *out_xyz );
344 
354 void c3dhall3_write_offset (c3dhall3_t *ctx, uint8_t axis, uint16_t offset );
355 
364 
373 void c3dhall3_interrupt_threshold ( c3dhall3_t *ctx, uint16_t threshold );
374 
383 #ifdef __cplusplus
384 }
385 #endif
386 #endif // _C3DHALL3_H_
387  // End public_function group
390 
391 // ------------------------------------------------------------------------- END
c3dhall3_cfg_t::i2c_address
uint8_t i2c_address
Definition: c3dhall3.h:228
c3dhall3_default_cfg
void c3dhall3_default_cfg(c3dhall3_t *ctx)
Click Default Configuration function.
c3dhall3_s::master_sel
c3dhall3_select_t master_sel
Definition: c3dhall3.h:202
c3dhall3_s::i2c
i2c_master_t i2c
Definition: c3dhall3.h:193
c3dhall3_read_y
int16_t c3dhall3_read_y(c3dhall3_t *ctx)
Read Y value.
c3dhall3_s::slave_address
uint8_t slave_address
Definition: c3dhall3.h:198
c3dhall3_init
C3DHALL3_RETVAL c3dhall3_init(c3dhall3_t *ctx, c3dhall3_cfg_t *cfg)
Initialization function.
c3dhall3_s::ccs
digital_out_t ccs
Definition: c3dhall3.h:184
c3dhall3_t
struct c3dhall3_s c3dhall3_t
Click ctx object definition.
c3dhall3_cfg_t::sck
pin_name_t sck
Definition: c3dhall3.h:217
c3dhall3_s
Click ctx object definition.
Definition: c3dhall3.h:181
c3dhall3_read_status
uint8_t c3dhall3_read_status(c3dhall3_t *ctx)
Read status register.
c3dhall3_cfg_t::int_pin
pin_name_t int_pin
Definition: c3dhall3.h:223
c3dhall3_read_interrupt_source
uint8_t c3dhall3_read_interrupt_source(c3dhall3_t *ctx)
Read interrupt source.
c3dhall3_select_t
uint8_t c3dhall3_select_t
Communication type.
Definition: c3dhall3.h:170
c3dhall3_s::int_pin
digital_in_t int_pin
Definition: c3dhall3.h:189
c3dhall3_s::write_f
c3dhall3_master_io_t write_f
Definition: c3dhall3.h:200
c3dhall3_cfg_t::spi_mode
uint8_t spi_mode
Definition: c3dhall3.h:230
c3dhall3_cfg_t::scl
pin_name_t scl
Definition: c3dhall3.h:213
c3dhall3_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: c3dhall3.h:227
c3dhall3_generic_read
void c3dhall3_generic_read(c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
c3dhall3_cfg_t::spi_speed
uint32_t spi_speed
Definition: c3dhall3.h:229
c3dhall3_cfg_t::sel
c3dhall3_select_t sel
Definition: c3dhall3.h:233
c3dhall3_interrupt_threshold
void c3dhall3_interrupt_threshold(c3dhall3_t *ctx, uint16_t threshold)
Set Interrupt Threshold.
c3dhall3_s::spi
spi_master_t spi
Definition: c3dhall3.h:194
c3dhall3_write_offset
void c3dhall3_write_offset(c3dhall3_t *ctx, uint8_t axis, uint16_t offset)
Write offset value.
c3dhall3_cfg_setup
void c3dhall3_cfg_setup(c3dhall3_cfg_t *cfg)
Config Object Initialization function.
c3dhall3_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: c3dhall3.h:231
c3dhall3_s::read_f
c3dhall3_master_io_t read_f
Definition: c3dhall3.h:201
c3dhall3_cfg_t
Click configuration structure definition.
Definition: c3dhall3.h:210
c3dhall3_cfg_t::sda
pin_name_t sda
Definition: c3dhall3.h:214
c3dhall3_master_io_t
void(* c3dhall3_master_io_t)(struct c3dhall3_s *, uint8_t, uint8_t *, uint8_t)
Master Input/Output type.
Definition: c3dhall3.h:175
c3dhall3_s::chip_select
pin_name_t chip_select
Definition: c3dhall3.h:199
c3dhall3_read_z
int16_t c3dhall3_read_z(c3dhall3_t *ctx)
Read Z value.
c3dhall3_generic_write
void c3dhall3_generic_write(c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
C3DHALL3_RETVAL
#define C3DHALL3_RETVAL
Definition: c3dhall3.h:77
c3dhall3_cfg_t::mosi
pin_name_t mosi
Definition: c3dhall3.h:216
c3dhall3_check_int_pin
uint8_t c3dhall3_check_int_pin(c3dhall3_t *ctx)
Check status of the int pin.
c3dhall3_read_x
int16_t c3dhall3_read_x(c3dhall3_t *ctx)
Read X value.
c3dhall3_cfg_t::cs
pin_name_t cs
Definition: c3dhall3.h:218
c3dhall3_read_xyz
void c3dhall3_read_xyz(c3dhall3_t *ctx, int16_t *out_xyz)
Read XYZ value.
c3dhall3_cfg_t::miso
pin_name_t miso
Definition: c3dhall3.h:215
c3dhall3_s::cs
digital_out_t cs
Definition: c3dhall3.h:185
c3dhall3_cfg_t::ccs
pin_name_t ccs
Definition: c3dhall3.h:222