Go to the documentation of this file.
38 #include "mikrosdk_version.h"
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_i2c_master.h"
51 #include "drv_spi_master.h"
64 #define C3DHALL3_MAP_MIKROBUS( cfg, mikrobus ) \
65 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
66 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
67 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
68 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
69 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
70 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
71 cfg.ccs = MIKROBUS( mikrobus, MIKROBUS_RST ); \
72 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT );
79 #define C3DHALL3_MASTER_I2C 0
80 #define C3DHALL3_MASTER_SPI 1
87 #define C3DHALL3_RETVAL uint8_t
89 #define C3DHALL3_OK 0x00
90 #define C3DHALL3_INIT_ERROR 0xFF
97 #define C3DHALL3_OFFSET_X_REG_L 0x45
98 #define C3DHALL3_OFFSET_Y_REG_L 0x47
99 #define C3DHALL3_OFFSET_Z_REG_L 0x49
100 #define C3DHALL3_INT_CRTL 0x63
101 #define C3DHALL3_INT_SOURCE 0x64
102 #define C3DHALL3_INT_THS_L 0x65
103 #define C3DHALL3_STATUS 0x67
104 #define C3DHALL3_OUTX_L 0x68
105 #define C3DHALL3_OUTY_L 0x6A
106 #define C3DHALL3_OUTZ_L 0x6C
107 #define C3DHALL3_CONFIGURATION_REGISTER_A 0x60
108 #define C3DHALL3_CONFIGURATION_REGISTER_B 0x61
109 #define C3DHALL3_CONFIGURATION_REGISTER_C 0x62
110 #define C3DHALL3_INTERRUPT_CONTROL 0x63
111 #define C3DHALL3_TEMPERATURE_L 0x6E
112 #define C3DHALL3_TEMPERATURE_H 0x6F
119 #define C3DHALL3_CFGA_TEMPERATURE_COMPENSATION 0x80
120 #define C3DHALL3_CFGA_REBOOT_MEMORY 0x40
121 #define C3DHALL3_CFGA_SOFT_RESET 0x20
122 #define C3DHALL3_CFGA_LOW_POWER_MODE 0x10
123 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_10 0x00
124 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_20 0x04
125 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_50 0x08
126 #define C3DHALL3_CFGA_OUTPUT_DATA_RATE_100 0x0C
127 #define C3DHALL3_CFGA_MODE_CONTINIOUS 0x00
128 #define C3DHALL3_CFGA_MODE_SINGLE 0x01
129 #define C3DHALL3_CFGA_MODE_IDLE 0x02
130 #define C3DHALL3_CFGA_MODE_IDLE_DEFAULT 0x03
136 #define C3DHALL3_CFGB_OFFSET_CANCELLATION_SINGLE_MODE 0x10
137 #define C3DHALL3_CFGB_INT_ON_DATAOFF 0x08
138 #define C3DHALL3_CFGB_SET_PULSE_FREQUENCY_EVERY_63_ODR 0x00
139 #define C3DHALL3_CFGB_SET_PULSE_FREQUENCY_AFTER_PD 0x04
140 #define C3DHALL3_CFGB_OFFSET_CANCELLATION 0x02
141 #define C3DHALL3_CFGB_LOW_PASS_FILTER_ODR_2 0x00
142 #define C3DHALL3_CFGB_LOW_PASS_FILTER_ODR_4 0x01
149 #define C3DHALL3_CFGC_INTERRUPT_ON_INT 0x40
150 #define C3DHALL3_CFGC_I2C_DISABLE 0x20
151 #define C3DHALL3_CFGC_ASYNC_DATA_READ 0x10
152 #define C3DHALL3_CFGC_DATA_INVERT 0x08
153 #define C3DHALL3_CFGC_SELF_TEST 0x02
154 #define C3DHALL3_CFGC_DATA_READY_ON_INT 0x01
161 #define C3DHALL3_INTCTRL_INTERRUPT_ON_X_AXIS 0x80
162 #define C3DHALL3_INTCTRL_INTERRUPT_ON_Y_AXIS 0x40
163 #define C3DHALL3_INTCTRL_INTERRUPT_ON_Z_AXIS 0x20
164 #define C3DHALL3_INTCTRL_INTERRUPT_POLARITY_LOW 0x00
165 #define C3DHALL3_INTCTRL_INTERRUPT_POLARITY_HIGH 0x40
166 #define C3DHALL3_INTCTRL_INTERRUPT_BIT_LATCHED 0x00
167 #define C3DHALL3_INTCTRL_INTERRUPT_BIT_PULSED 0x20
168 #define C3DHALL3_INTCTRL_INTERRUPT_ENABLE 0x01
396 #endif // _C3DHALL3_H_
uint8_t i2c_address
Definition: c3dhall3.h:238
void c3dhall3_default_cfg(c3dhall3_t *ctx)
Click Default Configuration function.
c3dhall3_select_t master_sel
Definition: c3dhall3.h:212
i2c_master_t i2c
Definition: c3dhall3.h:203
int16_t c3dhall3_read_y(c3dhall3_t *ctx)
Read Y value.
uint8_t slave_address
Definition: c3dhall3.h:208
C3DHALL3_RETVAL c3dhall3_init(c3dhall3_t *ctx, c3dhall3_cfg_t *cfg)
Initialization function.
digital_out_t ccs
Definition: c3dhall3.h:194
struct c3dhall3_s c3dhall3_t
Click ctx object definition.
pin_name_t sck
Definition: c3dhall3.h:227
Click ctx object definition.
Definition: c3dhall3.h:191
uint8_t c3dhall3_read_status(c3dhall3_t *ctx)
Read status register.
pin_name_t int_pin
Definition: c3dhall3.h:233
uint8_t c3dhall3_read_interrupt_source(c3dhall3_t *ctx)
Read interrupt source.
uint8_t c3dhall3_select_t
Communication type.
Definition: c3dhall3.h:180
digital_in_t int_pin
Definition: c3dhall3.h:199
c3dhall3_master_io_t write_f
Definition: c3dhall3.h:210
uint8_t spi_mode
Definition: c3dhall3.h:240
pin_name_t scl
Definition: c3dhall3.h:223
uint32_t i2c_speed
Definition: c3dhall3.h:237
void c3dhall3_generic_read(c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
uint32_t spi_speed
Definition: c3dhall3.h:239
c3dhall3_select_t sel
Definition: c3dhall3.h:243
void c3dhall3_interrupt_threshold(c3dhall3_t *ctx, uint16_t threshold)
Set Interrupt Threshold.
spi_master_t spi
Definition: c3dhall3.h:204
void c3dhall3_write_offset(c3dhall3_t *ctx, uint8_t axis, uint16_t offset)
Write offset value.
void c3dhall3_cfg_setup(c3dhall3_cfg_t *cfg)
Config Object Initialization function.
spi_master_chip_select_polarity_t cs_polarity
Definition: c3dhall3.h:241
c3dhall3_master_io_t read_f
Definition: c3dhall3.h:211
Click configuration structure definition.
Definition: c3dhall3.h:220
pin_name_t sda
Definition: c3dhall3.h:224
void(* c3dhall3_master_io_t)(struct c3dhall3_s *, uint8_t, uint8_t *, uint8_t)
Master Input/Output type.
Definition: c3dhall3.h:185
pin_name_t chip_select
Definition: c3dhall3.h:209
int16_t c3dhall3_read_z(c3dhall3_t *ctx)
Read Z value.
void c3dhall3_generic_write(c3dhall3_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
#define C3DHALL3_RETVAL
Definition: c3dhall3.h:87
pin_name_t mosi
Definition: c3dhall3.h:226
uint8_t c3dhall3_check_int_pin(c3dhall3_t *ctx)
Check status of the int pin.
int16_t c3dhall3_read_x(c3dhall3_t *ctx)
Read X value.
pin_name_t cs
Definition: c3dhall3.h:228
void c3dhall3_read_xyz(c3dhall3_t *ctx, int16_t *out_xyz)
Read XYZ value.
pin_name_t miso
Definition: c3dhall3.h:225
digital_out_t cs
Definition: c3dhall3.h:195
pin_name_t ccs
Definition: c3dhall3.h:232