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38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_spi_master.h"
53 #define PIXI_MAP_MIKROBUS( cfg, mikrobus ) \
54 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
55 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
56 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
57 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
58 cfg.cnv = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
59 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
66 #define PIXI_RETVAL uint8_t
68 #define PIXI_INIT_ERROR 0xFF
86 #define PIXI_REG_DEVICE_ID 0x00
87 #define PIXI_REG_INTERRUPT 0x01
88 #define PIXI_REG_ADC_DATA_STATUS 0x02
89 #define PIXI_REG_OVERCURRENT_STATUS 0x04
90 #define PIXI_REG_GPI_STATUS 0x06
91 #define PIXI_REG_INT_TEMP 0x08
92 #define PIXI_REG_EXT_TEMP_1 0x09
93 #define PIXI_REG_EXT_TEMP_2 0x0A
94 #define PIXI_REG_GPI_DATA 0x0B
95 #define PIXI_REG_ADC_DATA_BASE 0x40
102 #define PIXI_REG_GPO_DATA 0x0D
103 #define PIXI_REG_DEVICE_CONTROL 0x10
104 #define PIXI_REG_INTERRUPT_MASK 0x11
105 #define PIXI_REG_GPI_IRQMODE 0x12
106 #define PIXI_REG_DAC_PRESET_1 0x16
107 #define PIXI_REG_DAC_PRESET_2 0x17
108 #define PIXI_REG_TEMP_MONITOR_CONFIG 0x18
109 #define PIXI_REG_TEMP_IN_THRES_HIGH 0x19
110 #define PIXI_REG_TEMP_IN_THRES_LOW 0x1A
111 #define PIXI_REG_TEMP_EXT_1_THRES_HIGH 0x1B
112 #define PIXI_REG_TEMP_EXT_1_THRES_LOW 0x1C
113 #define PIXI_REG_TEMP_EXT_2_THRES_HIGH 0x1D
114 #define PIXI_REG_TEMP_EXT_2_THRES_LOW 0x1E
115 #define PIXI_REG_PORT_CONFIG_BASE 0x20
116 #define PIXI_REG_DAC_DATA_BASE 0x60
123 #define PIXI_CTL_ADCCTL_IDLE 0x0000
124 #define PIXI_CTL_ADCCTL_SINGLESWEEP 0x0001
125 #define PIXI_CTL_ADCCTL_SINGLECONV 0x0002
126 #define PIXI_CTL_ADCCTL_CONTSWEEP 0x0003
127 #define PIXI_CTL_DACCTL_SEQUPDATE 0x0000
128 #define PIXI_CTL_DACCTL_IMMUPDATE 0x0001 << 2
129 #define PIXI_CTL_DACCTL_USEPRST_1 0x0002 << 2
130 #define PIXI_CTL_DACCTL_USEPRST_2 0x0003 << 2
131 #define PIXI_CTL_ADCCONV_200KSPS 0x0000
132 #define PIXI_CTL_ADCCONV_250KSPS 0x0001 << 4
133 #define PIXI_CTL_ADCCONV_333KSPS 0x0002 << 4
134 #define PIXI_CTL_ADCCONV_400KSPS 0x0003 << 4
135 #define PIXI_CTL_DACREF_INTREF 0x0001 << 6
136 #define PIXI_CTL_THSHDN_ENABLE 0x0001 << 7
137 #define PIXI_CTL_TMPCTL_INT 0x0001 << 8
138 #define PIXI_CTL_TMPCTL_EXT_1 0x0002 << 8
139 #define PIXI_CTL_TMPCTL_EXT_2 0x0004 << 8
140 #define PIXI_CTL_TMPPER_EXTENDED 0x0001 << 11
141 #define PIXI_CTL_RS_CANCEL_ENABLE 0x0001 << 12
142 #define PIXI_CTL_LPEN_LOWPOWER 0x0001 << 13
143 #define PIXI_CTL_BRST_CONTEX_INC 0x0001 << 14
144 #define PIXI_CTL_RESET 0x0001 << 15
151 #define PIXI_IMASK_ADCFLAG 0x0001
152 #define PIXI_IMASK_ADCDR 0x0002
153 #define PIXI_IMASK_ADCDM 0x0004
154 #define PIXI_IMASK_GPIDR 0x0008
155 #define PIXI_IMASK_GPIDM 0x0010
156 #define PIXI_IMASK_DACOI 0x0020
157 #define PIXI_IMASK_TMPINT 6
158 #define PIXI_IMASK_TMPEXT1 9
159 #define PIXI_IMASK_TMPEXT2 12
160 #define PIXI_IMASK_VMON 0x8000
167 #define PIXI_TMPMON_INT_4_SMP 0x0000
168 #define PIXI_TMPMOD_INT_8_SMP 0x0001
169 #define PIXI_TMPMON_INT_16_SMP 0x0002
170 #define PIXI_TMPMON_INT_32_SMP 0x0003
171 #define PIXI_TMPMON_EXT1_4_SMP 0x0000
172 #define PIXI_TMPMOD_EXT1_8_SMP 0x0001 << 2
173 #define PIXI_TMPMON_EXT1_16_SMP 0x0002 << 2
174 #define PIXI_TMPMON_EXT1_32_SMP 0x0003 << 2
175 #define PIXI_TMPMON_EXT2_4_SMP 0x0000
176 #define PIXI_TMPMOD_EXT2_8_SMP 0x0001 << 4
177 #define PIXI_TMPMON_EXT2_16_SMP 0x0002 << 4
178 #define PIXI_TMPMON_EXT2_32_SMP 0x0003 << 4
179 #define PIXI_PORT_CFG_CFG_ASSOCIATED 0
180 #define PIXI_PORT_CFG_CFG_SAMPLES_1 0x0000 << 5
181 #define PIXI_PORT_CFG_CFG_SAMPLES_2 0x0001 << 5
182 #define PIXI_PORT_CFG_CFG_SAMPLES_4 0x0002 << 5
183 #define PIXI_PORT_CFG_CFG_SAMPLES_8 0x0003 << 5
184 #define PIXI_PORT_CFG_CFG_SAMPLES_16 0x0004 << 5
185 #define PIXI_PORT_CFG_CFG_SAMPLES_32 0x0005 << 5
186 #define PIXI_PORT_CFG_CFG_SAMPLES_64 0x0006 << 5
187 #define PIXI_PORT_CFG_CFG_SAMPLES_128 0x0007 << 5
188 #define PIXI_PORT_CFG_CFG_RANGE_N 0x0000 << 8
189 #define PIXI_PORT_CFG_CFG_RANGE_1 0x0001 << 8
190 #define PIXI_PORT_CFG_CFG_RANGE_2 0x0002 << 8
191 #define PIXI_PORT_CFG_CFG_RANGE_3 0x0003 << 8
192 #define PIXI_PORT_CFG_CFG_RANGE_4 0x0004 << 8
193 #define PIXI_PORT_CFG_CFG_RANGE_5 0x0005 << 8
194 #define PIXI_PORT_CFG_CFG_RANGE_6 0x0006 << 8
195 #define PIXI_PORT_CFG_CFG_RANGE_7 0x0007 << 8
196 #define PIXI_PORT_CFG_MODE_0 0x0000 << 12
197 #define PIXI_PORT_CFG_MODE_1 0x0001 << 12
198 #define PIXI_PORT_CFG_MODE_2 0x0002 << 12
199 #define PIXI_PORT_CFG_MODE_3 0x0003 << 12
200 #define PIXI_PORT_CFG_MODE_4 0x0004 << 12
201 #define PIXI_PORT_CFG_MODE_5 0x0005 << 12
202 #define PIXI_PORT_CFG_MODE_6 0x0006 << 12
203 #define PIXI_PORT_CFG_MODE_7 0x0007 << 12
204 #define PIXI_PORT_CFG_MODE_8 0x0008 << 12
205 #define PIXI_PORT_CFG_MODE_9 0x0009 << 12
206 #define PIXI_PORT_CFG_MODE_10 0x000A << 12
207 #define PIXI_PORT_CFG_MODE_11 0x000B << 12
208 #define PIXI_PORT_CFG_MODE_12 0x000C << 12
Click configuration structure definition.
Definition: pixi.h:242
pin_name_t chip_select
Definition: pixi.h:235
digital_out_t cs
Definition: pixi.h:226
pin_name_t int_pin
Definition: pixi.h:254
void pixi_default_cfg(pixi_t *ctx)
Click Default Configuration function.
spi_master_mode_t spi_mode
Definition: pixi.h:259
pin_name_t miso
Definition: pixi.h:246
digital_out_t cnv
Definition: pixi.h:225
spi_master_t spi
Definition: pixi.h:234
pin_name_t cs
Definition: pixi.h:249
void pixi_cfg_setup(pixi_cfg_t *cfg)
Config Object Initialization function.
uint32_t spi_speed
Definition: pixi.h:258
pin_name_t mosi
Definition: pixi.h:247
digital_in_t int_pin
Definition: pixi.h:230
#define PIXI_RETVAL
Definition: pixi.h:66
PIXI_RETVAL pixi_init(pixi_t *ctx, pixi_cfg_t *cfg)
Initialization function.
pin_name_t sck
Definition: pixi.h:248
uint8_t pixi_write_reg(pixi_t *ctx, const uint8_t reg_addr, uint32_t reg_data)
Write register function.
spi_master_chip_select_polarity_t cs_polarity
Definition: pixi.h:260
Click ctx object definition.
Definition: pixi.h:221
uint8_t pixi_read_reg(pixi_t *ctx, const uint8_t reg_addr, uint32_t *reg_data)
Read register function.
pin_name_t cnv
Definition: pixi.h:253