pixi  2.0.0.0
pixi.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef PIXI_H
36 #define PIXI_H
37 
42 #ifdef PREINIT_SUPPORTED
43 #include "preinit.h"
44 #endif
45 
46 #ifdef MikroCCoreVersion
47  #if MikroCCoreVersion >= 1
48  #include "delays.h"
49  #endif
50 #endif
51 
52 #include "drv_digital_out.h"
53 #include "drv_digital_in.h"
54 #include "drv_spi_master.h"
55 
56 // -------------------------------------------------------------- PUBLIC MACROS
67 #define PIXI_MAP_MIKROBUS( cfg, mikrobus ) \
68  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
69  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
70  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
71  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
72  cfg.cnv = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
73  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
74 
80 #define PIXI_RETVAL uint8_t
81 
82 #define PIXI_INIT_ERROR 0xFF
83 
89 #define READ_OP 0
90 #define WRITE_OP 1
91 
92 #define PIXI_ERR 1
93 #define PIXI_OK 0
94 
100 #define PIXI_REG_DEVICE_ID 0x00
101 #define PIXI_REG_INTERRUPT 0x01
102 #define PIXI_REG_ADC_DATA_STATUS 0x02
103 #define PIXI_REG_OVERCURRENT_STATUS 0x04
104 #define PIXI_REG_GPI_STATUS 0x06
105 #define PIXI_REG_INT_TEMP 0x08
106 #define PIXI_REG_EXT_TEMP_1 0x09
107 #define PIXI_REG_EXT_TEMP_2 0x0A
108 #define PIXI_REG_GPI_DATA 0x0B
109 #define PIXI_REG_ADC_DATA_BASE 0x40
110 
116 #define PIXI_REG_GPO_DATA 0x0D
117 #define PIXI_REG_DEVICE_CONTROL 0x10
118 #define PIXI_REG_INTERRUPT_MASK 0x11
119 #define PIXI_REG_GPI_IRQMODE 0x12
120 #define PIXI_REG_DAC_PRESET_1 0x16
121 #define PIXI_REG_DAC_PRESET_2 0x17
122 #define PIXI_REG_TEMP_MONITOR_CONFIG 0x18
123 #define PIXI_REG_TEMP_IN_THRES_HIGH 0x19
124 #define PIXI_REG_TEMP_IN_THRES_LOW 0x1A
125 #define PIXI_REG_TEMP_EXT_1_THRES_HIGH 0x1B
126 #define PIXI_REG_TEMP_EXT_1_THRES_LOW 0x1C
127 #define PIXI_REG_TEMP_EXT_2_THRES_HIGH 0x1D
128 #define PIXI_REG_TEMP_EXT_2_THRES_LOW 0x1E
129 #define PIXI_REG_PORT_CONFIG_BASE 0x20
130 #define PIXI_REG_DAC_DATA_BASE 0x60
131 
137 #define PIXI_CTL_ADCCTL_IDLE 0x0000
138 #define PIXI_CTL_ADCCTL_SINGLESWEEP 0x0001
139 #define PIXI_CTL_ADCCTL_SINGLECONV 0x0002
140 #define PIXI_CTL_ADCCTL_CONTSWEEP 0x0003
141 #define PIXI_CTL_DACCTL_SEQUPDATE 0x0000
142 #define PIXI_CTL_DACCTL_IMMUPDATE 0x0001 << 2
143 #define PIXI_CTL_DACCTL_USEPRST_1 0x0002 << 2
144 #define PIXI_CTL_DACCTL_USEPRST_2 0x0003 << 2
145 #define PIXI_CTL_ADCCONV_200KSPS 0x0000
146 #define PIXI_CTL_ADCCONV_250KSPS 0x0001 << 4
147 #define PIXI_CTL_ADCCONV_333KSPS 0x0002 << 4
148 #define PIXI_CTL_ADCCONV_400KSPS 0x0003 << 4
149 #define PIXI_CTL_DACREF_INTREF 0x0001 << 6
150 #define PIXI_CTL_THSHDN_ENABLE 0x0001 << 7
151 #define PIXI_CTL_TMPCTL_INT 0x0001 << 8
152 #define PIXI_CTL_TMPCTL_EXT_1 0x0002 << 8
153 #define PIXI_CTL_TMPCTL_EXT_2 0x0004 << 8
154 #define PIXI_CTL_TMPPER_EXTENDED 0x0001 << 11
155 #define PIXI_CTL_RS_CANCEL_ENABLE 0x0001 << 12
156 #define PIXI_CTL_LPEN_LOWPOWER 0x0001 << 13
157 #define PIXI_CTL_BRST_CONTEX_INC 0x0001 << 14
158 #define PIXI_CTL_RESET 0x0001 << 15
159 
165 #define PIXI_IMASK_ADCFLAG 0x0001
166 #define PIXI_IMASK_ADCDR 0x0002
167 #define PIXI_IMASK_ADCDM 0x0004
168 #define PIXI_IMASK_GPIDR 0x0008
169 #define PIXI_IMASK_GPIDM 0x0010
170 #define PIXI_IMASK_DACOI 0x0020
171 #define PIXI_IMASK_TMPINT 6
172 #define PIXI_IMASK_TMPEXT1 9
173 #define PIXI_IMASK_TMPEXT2 12
174 #define PIXI_IMASK_VMON 0x8000
175 
181 #define PIXI_TMPMON_INT_4_SMP 0x0000
182 #define PIXI_TMPMOD_INT_8_SMP 0x0001
183 #define PIXI_TMPMON_INT_16_SMP 0x0002
184 #define PIXI_TMPMON_INT_32_SMP 0x0003
185 #define PIXI_TMPMON_EXT1_4_SMP 0x0000
186 #define PIXI_TMPMOD_EXT1_8_SMP 0x0001 << 2
187 #define PIXI_TMPMON_EXT1_16_SMP 0x0002 << 2
188 #define PIXI_TMPMON_EXT1_32_SMP 0x0003 << 2
189 #define PIXI_TMPMON_EXT2_4_SMP 0x0000
190 #define PIXI_TMPMOD_EXT2_8_SMP 0x0001 << 4
191 #define PIXI_TMPMON_EXT2_16_SMP 0x0002 << 4
192 #define PIXI_TMPMON_EXT2_32_SMP 0x0003 << 4
193 #define PIXI_PORT_CFG_CFG_ASSOCIATED 0
194 #define PIXI_PORT_CFG_CFG_SAMPLES_1 0x0000 << 5
195 #define PIXI_PORT_CFG_CFG_SAMPLES_2 0x0001 << 5
196 #define PIXI_PORT_CFG_CFG_SAMPLES_4 0x0002 << 5
197 #define PIXI_PORT_CFG_CFG_SAMPLES_8 0x0003 << 5
198 #define PIXI_PORT_CFG_CFG_SAMPLES_16 0x0004 << 5
199 #define PIXI_PORT_CFG_CFG_SAMPLES_32 0x0005 << 5
200 #define PIXI_PORT_CFG_CFG_SAMPLES_64 0x0006 << 5
201 #define PIXI_PORT_CFG_CFG_SAMPLES_128 0x0007 << 5
202 #define PIXI_PORT_CFG_CFG_RANGE_N 0x0000 << 8
203 #define PIXI_PORT_CFG_CFG_RANGE_1 0x0001 << 8
204 #define PIXI_PORT_CFG_CFG_RANGE_2 0x0002 << 8
205 #define PIXI_PORT_CFG_CFG_RANGE_3 0x0003 << 8
206 #define PIXI_PORT_CFG_CFG_RANGE_4 0x0004 << 8
207 #define PIXI_PORT_CFG_CFG_RANGE_5 0x0005 << 8
208 #define PIXI_PORT_CFG_CFG_RANGE_6 0x0006 << 8
209 #define PIXI_PORT_CFG_CFG_RANGE_7 0x0007 << 8
210 #define PIXI_PORT_CFG_MODE_0 0x0000 << 12
211 #define PIXI_PORT_CFG_MODE_1 0x0001 << 12
212 #define PIXI_PORT_CFG_MODE_2 0x0002 << 12
213 #define PIXI_PORT_CFG_MODE_3 0x0003 << 12
214 #define PIXI_PORT_CFG_MODE_4 0x0004 << 12
215 #define PIXI_PORT_CFG_MODE_5 0x0005 << 12
216 #define PIXI_PORT_CFG_MODE_6 0x0006 << 12
217 #define PIXI_PORT_CFG_MODE_7 0x0007 << 12
218 #define PIXI_PORT_CFG_MODE_8 0x0008 << 12
219 #define PIXI_PORT_CFG_MODE_9 0x0009 << 12
220 #define PIXI_PORT_CFG_MODE_10 0x000A << 12
221 #define PIXI_PORT_CFG_MODE_11 0x000B << 12
222 #define PIXI_PORT_CFG_MODE_12 0x000C << 12
223  // End group macro
226 // --------------------------------------------------------------- PUBLIC TYPES
235 typedef struct
236 {
237  // Output pins
238 
239  digital_out_t cnv;
240  digital_out_t cs;
241 
242  // Input pins
243 
244  digital_in_t int_pin;
245 
246  // Modules
247 
248  spi_master_t spi;
249  pin_name_t chip_select;
250 
251 } pixi_t;
252 
256 typedef struct
257 {
258  // Communication gpio pins
259 
260  pin_name_t miso;
261  pin_name_t mosi;
262  pin_name_t sck;
263  pin_name_t cs;
264 
265  // Additional gpio pins
266 
267  pin_name_t cnv;
268  pin_name_t int_pin;
269 
270  // static variable
271 
272  uint32_t spi_speed;
273  spi_master_mode_t spi_mode;
274  spi_master_chip_select_polarity_t cs_polarity;
275 
276 } pixi_cfg_t;
277  // End types group
279 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
280 
285 #ifdef __cplusplus
286 extern "C"{
287 #endif
288 
298 
307 
315 void pixi_default_cfg ( pixi_t *ctx );
316 
326 uint8_t pixi_write_reg ( pixi_t *ctx, const uint8_t reg_addr, uint32_t reg_data );
327 
337 uint8_t pixi_read_reg ( pixi_t *ctx, const uint8_t reg_addr, uint32_t *reg_data );
338 
339 #ifdef __cplusplus
340 }
341 #endif
342 #endif // _PIXI_H_
343  // End public_function group
346 
347 // ------------------------------------------------------------------------- END
pixi_cfg_t
Click configuration structure definition.
Definition: pixi.h:257
pixi_t::chip_select
pin_name_t chip_select
Definition: pixi.h:249
pixi_t::cs
digital_out_t cs
Definition: pixi.h:240
pixi_cfg_t::int_pin
pin_name_t int_pin
Definition: pixi.h:268
pixi_default_cfg
void pixi_default_cfg(pixi_t *ctx)
Click Default Configuration function.
pixi_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: pixi.h:273
pixi_cfg_t::miso
pin_name_t miso
Definition: pixi.h:260
pixi_t::cnv
digital_out_t cnv
Definition: pixi.h:239
pixi_t::spi
spi_master_t spi
Definition: pixi.h:248
pixi_cfg_t::cs
pin_name_t cs
Definition: pixi.h:263
pixi_cfg_setup
void pixi_cfg_setup(pixi_cfg_t *cfg)
Config Object Initialization function.
pixi_cfg_t::spi_speed
uint32_t spi_speed
Definition: pixi.h:272
pixi_cfg_t::mosi
pin_name_t mosi
Definition: pixi.h:261
pixi_t::int_pin
digital_in_t int_pin
Definition: pixi.h:244
PIXI_RETVAL
#define PIXI_RETVAL
Definition: pixi.h:80
pixi_init
PIXI_RETVAL pixi_init(pixi_t *ctx, pixi_cfg_t *cfg)
Initialization function.
pixi_cfg_t::sck
pin_name_t sck
Definition: pixi.h:262
pixi_write_reg
uint8_t pixi_write_reg(pixi_t *ctx, const uint8_t reg_addr, uint32_t reg_data)
Write register function.
pixi_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: pixi.h:274
pixi_t
Click ctx object definition.
Definition: pixi.h:236
pixi_read_reg
uint8_t pixi_read_reg(pixi_t *ctx, const uint8_t reg_addr, uint32_t *reg_data)
Read register function.
pixi_cfg_t::cnv
pin_name_t cnv
Definition: pixi.h:267