vreg  2.0.0.0
vreg.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef VREG_H
36 #define VREG_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_spi_master.h"
41 
42 
43 // -------------------------------------------------------------- PUBLIC MACROS
54 #define VREG_MAP_MIKROBUS( cfg, mikrobus ) \
55  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
56  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
57  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
58  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
59  cfg.cs2 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
60  cfg.sw = MIKROBUS( mikrobus, MIKROBUS_PWM );
61 
67 #define VREG_RETVAL uint8_t
68 
69 #define VREG_OK 0x00
70 #define VREG_INIT_ERROR 0xFF
71 
73 #define VREG_CHANNEL_0 0x00
74 #define VREG_CHANNEL_1 0x01
75 #define VREG_CHANNEL_2 0x02
76 #define VREG_CHANNEL_3 0x03
77 #define VREG_SINGLE_DIFFERENTIAL 0x00
78 #define VREG_SINGLE_ENDED 0x02
79 #define VREG_START_BIT 0x04
80  // End group macro
82 // --------------------------------------------------------------- PUBLIC TYPES
91 typedef struct
92 {
93  // Output pins
94 
95  digital_out_t cs;
96  digital_out_t cs2;
97  digital_out_t sw;
98 
99  // Modules
100 
101  spi_master_t spi;
102  pin_name_t chip_select;
103 
104 } vreg_t;
105 
109 typedef struct
110 {
111  // Communication gpio pins
112 
113  pin_name_t miso;
114  pin_name_t mosi;
115  pin_name_t sck;
116  pin_name_t cs;
117 
118  // Additional gpio pins
119 
120  pin_name_t cs2;
121  pin_name_t sw;
122 
123  // static variable
124 
125  uint32_t spi_speed;
126  spi_master_mode_t spi_mode;
127  spi_master_chip_select_polarity_t cs_polarity;
128 
129 } vreg_cfg_t;
130  // End types group
132 
133 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
134 
139 #ifdef __cplusplus
140 extern "C"{
141 #endif
142 
151 void vreg_cfg_setup ( vreg_cfg_t *cfg );
152 
160 VREG_RETVAL vreg_init ( vreg_t *ctx, vreg_cfg_t *cfg );
161 
174 (
175  vreg_t *ctx,
176  uint8_t *wr_buf,
177  uint16_t wr_len,
178  uint8_t *rd_buf,
179  uint16_t rd_len
180 );
181 
194 uint16_t vreg_get_adc ( vreg_t *ctx, uint8_t channel );
195 
205 void vreg_set_out_voltage ( vreg_t *ctx, uint16_t value_dac );
206 
216 void vreg_set_output_voltage_procentage ( vreg_t *ctx, uint8_t value_dac_pct );
217 
224 void vreg_start_measuring ( vreg_t *ctx );
225 
234 void vreg_stop_measuring ( vreg_t *ctx );
235 
236 #ifdef __cplusplus
237 }
238 #endif
239 #endif // _VREG_H_
240  // End public_function group
243 
244 // ------------------------------------------------------------------------- END
vreg_set_output_voltage_procentage
void vreg_set_output_voltage_procentage(vreg_t *ctx, uint8_t value_dac_pct)
Set output voltage procentage function.
vreg_t::spi
spi_master_t spi
Definition: vreg.h:101
vreg_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: vreg.h:126
vreg_cfg_t::sck
pin_name_t sck
Definition: vreg.h:115
vreg_set_out_voltage
void vreg_set_out_voltage(vreg_t *ctx, uint16_t value_dac)
Set output voltage function.
vreg_t
Click ctx object definition.
Definition: vreg.h:91
vreg_cfg_t
Click configuration structure definition.
Definition: vreg.h:109
vreg_t::cs
digital_out_t cs
Definition: vreg.h:95
vreg_get_adc
uint16_t vreg_get_adc(vreg_t *ctx, uint8_t channel)
Get ADC value function.
vreg_init
VREG_RETVAL vreg_init(vreg_t *ctx, vreg_cfg_t *cfg)
Initialization function.
vreg_stop_measuring
void vreg_stop_measuring(vreg_t *ctx)
Stop the measuring function.
vreg_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: vreg.h:127
vreg_cfg_t::cs
pin_name_t cs
Definition: vreg.h:116
vreg_cfg_t::spi_speed
uint32_t spi_speed
Definition: vreg.h:125
vreg_cfg_t::mosi
pin_name_t mosi
Definition: vreg.h:114
vreg_cfg_setup
void vreg_cfg_setup(vreg_cfg_t *cfg)
Config Object Initialization function.
vreg_t::chip_select
pin_name_t chip_select
Definition: vreg.h:102
vreg_cfg_t::cs2
pin_name_t cs2
Definition: vreg.h:120
vreg_generic_transfer
void vreg_generic_transfer(vreg_t *ctx, uint8_t *wr_buf, uint16_t wr_len, uint8_t *rd_buf, uint16_t rd_len)
Generic transfer function.
vreg_cfg_t::sw
pin_name_t sw
Definition: vreg.h:121
vreg_t::cs2
digital_out_t cs2
Definition: vreg.h:96
VREG_RETVAL
#define VREG_RETVAL
Definition: vreg.h:67
vreg_t::sw
digital_out_t sw
Definition: vreg.h:97
vreg_cfg_t::miso
pin_name_t miso
Definition: vreg.h:113
vreg_start_measuring
void vreg_start_measuring(vreg_t *ctx)
Start the measuring function.