vreg  2.0.0.0
vreg.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef VREG_H
36 #define VREG_H
37 
38 #include "mikrosdk_version.h"
39 
40 #ifdef __GNUC__
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
43 #else
44 #include "delays.h"
45 #endif
46 #endif
47 
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_spi_master.h"
51 
52 
53 // -------------------------------------------------------------- PUBLIC MACROS
64 #define VREG_MAP_MIKROBUS( cfg, mikrobus ) \
65  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
66  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
67  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
68  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
69  cfg.cs2 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
70  cfg.sw = MIKROBUS( mikrobus, MIKROBUS_PWM );
71 
77 #define VREG_RETVAL uint8_t
78 
79 #define VREG_OK 0x00
80 #define VREG_INIT_ERROR 0xFF
81 
83 #define VREG_CHANNEL_0 0x00
84 #define VREG_CHANNEL_1 0x01
85 #define VREG_CHANNEL_2 0x02
86 #define VREG_CHANNEL_3 0x03
87 #define VREG_SINGLE_DIFFERENTIAL 0x00
88 #define VREG_SINGLE_ENDED 0x02
89 #define VREG_START_BIT 0x04
90  // End group macro
92 // --------------------------------------------------------------- PUBLIC TYPES
101 typedef struct
102 {
103  // Output pins
104 
105  digital_out_t cs;
106  digital_out_t cs2;
107  digital_out_t sw;
108 
109  // Modules
110 
111  spi_master_t spi;
112  pin_name_t chip_select;
113 
114 } vreg_t;
115 
119 typedef struct
120 {
121  // Communication gpio pins
122 
123  pin_name_t miso;
124  pin_name_t mosi;
125  pin_name_t sck;
126  pin_name_t cs;
127 
128  // Additional gpio pins
129 
130  pin_name_t cs2;
131  pin_name_t sw;
132 
133  // static variable
134 
135  uint32_t spi_speed;
136  spi_master_mode_t spi_mode;
137  spi_master_chip_select_polarity_t cs_polarity;
138 
139 } vreg_cfg_t;
140  // End types group
142 
143 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
144 
149 #ifdef __cplusplus
150 extern "C"{
151 #endif
152 
162 
171 
184 (
185  vreg_t *ctx,
186  uint8_t *wr_buf,
187  uint16_t wr_len,
188  uint8_t *rd_buf,
189  uint16_t rd_len
190 );
191 
204 uint16_t vreg_get_adc ( vreg_t *ctx, uint8_t channel );
205 
215 void vreg_set_out_voltage ( vreg_t *ctx, uint16_t value_dac );
216 
226 void vreg_set_output_voltage_procentage ( vreg_t *ctx, uint8_t value_dac_pct );
227 
235 
245 
246 #ifdef __cplusplus
247 }
248 #endif
249 #endif // _VREG_H_
250  // End public_function group
253 
254 // ------------------------------------------------------------------------- END
vreg_set_output_voltage_procentage
void vreg_set_output_voltage_procentage(vreg_t *ctx, uint8_t value_dac_pct)
Set output voltage procentage function.
vreg_t::spi
spi_master_t spi
Definition: vreg.h:111
vreg_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: vreg.h:136
vreg_cfg_t::sck
pin_name_t sck
Definition: vreg.h:125
vreg_set_out_voltage
void vreg_set_out_voltage(vreg_t *ctx, uint16_t value_dac)
Set output voltage function.
vreg_t
Click ctx object definition.
Definition: vreg.h:102
vreg_cfg_t
Click configuration structure definition.
Definition: vreg.h:120
vreg_t::cs
digital_out_t cs
Definition: vreg.h:105
vreg_get_adc
uint16_t vreg_get_adc(vreg_t *ctx, uint8_t channel)
Get ADC value function.
vreg_init
VREG_RETVAL vreg_init(vreg_t *ctx, vreg_cfg_t *cfg)
Initialization function.
vreg_stop_measuring
void vreg_stop_measuring(vreg_t *ctx)
Stop the measuring function.
vreg_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: vreg.h:137
vreg_cfg_t::cs
pin_name_t cs
Definition: vreg.h:126
vreg_cfg_t::spi_speed
uint32_t spi_speed
Definition: vreg.h:135
vreg_cfg_t::mosi
pin_name_t mosi
Definition: vreg.h:124
vreg_cfg_setup
void vreg_cfg_setup(vreg_cfg_t *cfg)
Config Object Initialization function.
vreg_t::chip_select
pin_name_t chip_select
Definition: vreg.h:112
vreg_cfg_t::cs2
pin_name_t cs2
Definition: vreg.h:130
vreg_generic_transfer
void vreg_generic_transfer(vreg_t *ctx, uint8_t *wr_buf, uint16_t wr_len, uint8_t *rd_buf, uint16_t rd_len)
Generic transfer function.
vreg_cfg_t::sw
pin_name_t sw
Definition: vreg.h:131
vreg_t::cs2
digital_out_t cs2
Definition: vreg.h:106
VREG_RETVAL
#define VREG_RETVAL
Definition: vreg.h:77
vreg_t::sw
digital_out_t sw
Definition: vreg.h:107
vreg_cfg_t::miso
pin_name_t miso
Definition: vreg.h:123
vreg_start_measuring
void vreg_start_measuring(vreg_t *ctx)
Start the measuring function.