vreg  2.0.0.0
vreg.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef VREG_H
36 #define VREG_H
37 
42 #ifdef PREINIT_SUPPORTED
43 #include "preinit.h"
44 #endif
45 
46 #ifdef MikroCCoreVersion
47  #if MikroCCoreVersion >= 1
48  #include "delays.h"
49  #endif
50 #endif
51 
52 #include "drv_digital_out.h"
53 #include "drv_digital_in.h"
54 #include "drv_spi_master.h"
55 
56 
57 // -------------------------------------------------------------- PUBLIC MACROS
68 #define VREG_MAP_MIKROBUS( cfg, mikrobus ) \
69  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
70  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
71  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
72  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
73  cfg.cs2 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
74  cfg.sw = MIKROBUS( mikrobus, MIKROBUS_PWM );
75 
81 #define VREG_RETVAL uint8_t
82 
83 #define VREG_OK 0x00
84 #define VREG_INIT_ERROR 0xFF
85 
87 #define VREG_CHANNEL_0 0x00
88 #define VREG_CHANNEL_1 0x01
89 #define VREG_CHANNEL_2 0x02
90 #define VREG_CHANNEL_3 0x03
91 #define VREG_SINGLE_DIFFERENTIAL 0x00
92 #define VREG_SINGLE_ENDED 0x02
93 #define VREG_START_BIT 0x04
94  // End group macro
96 // --------------------------------------------------------------- PUBLIC TYPES
105 typedef struct
106 {
107  // Output pins
108 
109  digital_out_t cs;
110  digital_out_t cs2;
111  digital_out_t sw;
112 
113  // Modules
114 
115  spi_master_t spi;
116  pin_name_t chip_select;
117 
118 } vreg_t;
119 
123 typedef struct
124 {
125  // Communication gpio pins
126 
127  pin_name_t miso;
128  pin_name_t mosi;
129  pin_name_t sck;
130  pin_name_t cs;
131 
132  // Additional gpio pins
133 
134  pin_name_t cs2;
135  pin_name_t sw;
136 
137  // static variable
138 
139  uint32_t spi_speed;
140  spi_master_mode_t spi_mode;
141  spi_master_chip_select_polarity_t cs_polarity;
142 
143 } vreg_cfg_t;
144  // End types group
146 
147 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
148 
153 #ifdef __cplusplus
154 extern "C"{
155 #endif
156 
166 
175 
188 (
189  vreg_t *ctx,
190  uint8_t *wr_buf,
191  uint16_t wr_len,
192  uint8_t *rd_buf,
193  uint16_t rd_len
194 );
195 
208 uint16_t vreg_get_adc ( vreg_t *ctx, uint8_t channel );
209 
219 void vreg_set_out_voltage ( vreg_t *ctx, uint16_t value_dac );
220 
230 void vreg_set_output_voltage_procentage ( vreg_t *ctx, uint8_t value_dac_pct );
231 
239 
249 
250 #ifdef __cplusplus
251 }
252 #endif
253 #endif // _VREG_H_
254  // End public_function group
257 
258 // ------------------------------------------------------------------------- END
vreg_set_output_voltage_procentage
void vreg_set_output_voltage_procentage(vreg_t *ctx, uint8_t value_dac_pct)
Set output voltage procentage function.
vreg_t::spi
spi_master_t spi
Definition: vreg.h:115
vreg_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: vreg.h:140
vreg_cfg_t::sck
pin_name_t sck
Definition: vreg.h:129
vreg_set_out_voltage
void vreg_set_out_voltage(vreg_t *ctx, uint16_t value_dac)
Set output voltage function.
vreg_t
Click ctx object definition.
Definition: vreg.h:106
vreg_cfg_t
Click configuration structure definition.
Definition: vreg.h:124
vreg_t::cs
digital_out_t cs
Definition: vreg.h:109
vreg_get_adc
uint16_t vreg_get_adc(vreg_t *ctx, uint8_t channel)
Get ADC value function.
vreg_init
VREG_RETVAL vreg_init(vreg_t *ctx, vreg_cfg_t *cfg)
Initialization function.
vreg_stop_measuring
void vreg_stop_measuring(vreg_t *ctx)
Stop the measuring function.
vreg_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: vreg.h:141
vreg_cfg_t::cs
pin_name_t cs
Definition: vreg.h:130
vreg_cfg_t::spi_speed
uint32_t spi_speed
Definition: vreg.h:139
vreg_cfg_t::mosi
pin_name_t mosi
Definition: vreg.h:128
vreg_cfg_setup
void vreg_cfg_setup(vreg_cfg_t *cfg)
Config Object Initialization function.
vreg_t::chip_select
pin_name_t chip_select
Definition: vreg.h:116
vreg_cfg_t::cs2
pin_name_t cs2
Definition: vreg.h:134
vreg_generic_transfer
void vreg_generic_transfer(vreg_t *ctx, uint8_t *wr_buf, uint16_t wr_len, uint8_t *rd_buf, uint16_t rd_len)
Generic transfer function.
vreg_cfg_t::sw
pin_name_t sw
Definition: vreg.h:135
vreg_t::cs2
digital_out_t cs2
Definition: vreg.h:110
VREG_RETVAL
#define VREG_RETVAL
Definition: vreg.h:81
vreg_t::sw
digital_out_t sw
Definition: vreg.h:111
vreg_cfg_t::miso
pin_name_t miso
Definition: vreg.h:127
vreg_start_measuring
void vreg_start_measuring(vreg_t *ctx)
Start the measuring function.