accel5 2.0.0.0
accel5.h
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1/*
2 * MikroSDK - MikroE Software Development Kit
3 * Copyright (c) 2019, MikroElektronika - www.mikroe.com
4 * All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
19 * SOFTWARE.
20 */
21
28// ----------------------------------------------------------------------------
29
30#ifndef ACCEL5_H
31#define ACCEL5_H
32
33#include "drv_digital_out.h"
34#include "drv_digital_in.h"
35#include "drv_i2c_master.h"
36
37// -------------------------------------------------------------- PUBLIC MACROS
47#define ACCEL5_MAP_MIKROBUS( cfg, mikrobus ) \
48 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
49 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
50 cfg.it2 = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
51 cfg.it1 = MIKROBUS( mikrobus, MIKROBUS_INT );
52
59#define ACCEL5_OK 0
60#define ACCEL5_INIT_ERROR (-1)
67#define ACCEL5_CHIP_ID 0x90
74#define ACCEL5_REG_CHIP_ID 0x00
75#define ACCEL5_REG_ERR_REG 0x02
76#define ACCEL5_REG_STATUS 0x03
77#define ACCEL5_REG_ACC_X_LSB 0x04
78#define ACCEL5_REG_ACC_X_MSB 0x05
79#define ACCEL5_REG_ACC_Y_LSB 0x06
80#define ACCEL5_REG_ACC_Y_MSB 0x07
81#define ACCEL5_REG_ACC_Z_LSB 0x08
82#define ACCEL5_REG_ACC_Z_MSB 0x09
83#define ACCEL5_REG_SENSOR_TIME_0 0x0A
84#define ACCEL5_REG_SENSOR_TIME_1 0x0B
85#define ACCEL5_REG_SENSOR_TIME_2 0x0C
86#define ACCEL5_REG_EVENT 0x0D
87#define ACCEL5_REG_INT_STATUS_0 0x0E
88#define ACCEL5_REG_INT_STATUS_1 0x0F
89#define ACCEL5_REG_INT_STATUS_2 0x10
90#define ACCEL5_REG_TEMPERATURE 0x11
91#define ACCEL5_REG_FIFO_LENGTH_0 0x12
92#define ACCEL5_REG_FIFO_LENGTH_1 0x13
93#define ACCEL5_REG_FIFO_DATA 0x14
94#define ACCEL5_REG_STEP_CNT_0 0x15
95#define ACCEL5_REG_STEP_CNT_1 0x16
96#define ACCEL5_REG_STEP_CNT_2 0x17
97#define ACCEL5_REG_STEP_STATUS 0x18
98#define ACCEL5_REG_ACC_CONGIG_0 0x19
99#define ACCEL5_REG_ACC_CONGIG_1 0x1A
100#define ACCEL5_REG_ACC_CONGIG_2 0x1B
101#define ACCEL5_REG_INT_CONFIG_0 0x1F
102#define ACCEL5_REG_INT_CONFIG_1 0x20
103#define ACCEL5_REG_INT1_MAP 0x21
104#define ACCEL5_REG_INT2_MAP 0x22
105#define ACCEL5_REG_INT12_MAP 0x23
106#define ACCEL5_REG_INT12_IO_CTRL 0x24
107#define ACCEL5_REG_FIFO_CONFIG_0 0x26
108#define ACCEL5_REG_FIFO_CONFIG_1 0x27
109#define ACCEL5_REG_FIFO_CONFIG_2 0x28
110#define ACCEL5_REG_FIFO_PWR_CONFIG 0x29
111#define ACCEL5_REG_AUTO_LOW_POW_0 0x2A
112#define ACCEL5_REG_AUTO_LOW_POW_1 0x2B
113#define ACCEL5_REG_AUTO_WAKEUP_0 0x2C
114#define ACCEL5_REG_AUTO_WAKEUP_1 0x2D
115#define ACCEL5_REG_WAKEUP_CONFIG_0 0x2F
116#define ACCEL5_REG_WAKEUP_CONFIG_1 0x30
117#define ACCEL5_REG_WAKEUP_CONFIG_2 0x31
118#define ACCEL5_REG_WAKEUP_CONFIG_3 0x32
119#define ACCEL5_REG_WAKEUP_CONFIG_4 0x33
120#define ACCEL5_REG_ORIENTCH_CONFIG_0 0x35
121#define ACCEL5_REG_ORIENTCH_CONFIG_1 0x36
122#define ACCEL5_REG_ORIENTCH_CONFIG_2 0x37
123#define ACCEL5_REG_ORIENTCH_CONFIG_3 0x38
124#define ACCEL5_REG_ORIENTCH_CONFIG_4 0x39
125#define ACCEL5_REG_ORIENTCH_CONFIG_5 0x3A
126#define ACCEL5_REG_ORIENTCH_CONFIG_6 0x3B
127#define ACCEL5_REG_ORIENTCH_CONFIG_7 0x3C
128#define ACCEL5_REG_ORIENTCH_CONFIG_8 0x3D
129#define ACCEL5_REG_ORIENTCH_CONFIG_9 0x3E
130#define ACCEL5_REG_GEN1_INT_CONFIG_0 0x3F
131#define ACCEL5_REG_GEN1_INT_CONFIG_1 0x40
132#define ACCEL5_REG_GEN1_INT_CONFIG_2 0x41
133#define ACCEL5_REG_GEN1_INT_CONFIG_3 0x42
134#define ACCEL5_REG_GEN1_INT_CONFIG_31 0x43
135#define ACCEL5_REG_GEN1_INT_CONFIG_4 0x44
136#define ACCEL5_REG_GEN1_INT_CONFIG_5 0x45
137#define ACCEL5_REG_GEN1_INT_CONFIG_6 0x46
138#define ACCEL5_REG_GEN1_INT_CONFIG_7 0x47
139#define ACCEL5_REG_GEN1_INT_CONFIG_8 0x48
140#define ACCEL5_REG_GEN1_INT_CONFIG_9 0x49
141#define ACCEL5_REG_GEN2_INT_CONFIG_0 0x4A
142#define ACCEL5_REG_GEN2_INT_CONFIG_1 0x4B
143#define ACCEL5_REG_GEN2_INT_CONFIG_2 0x4C
144#define ACCEL5_REG_GEN2_INT_CONFIG_3 0x4D
145#define ACCEL5_REG_GEN2_INT_CONFIG_31 0x4E
146#define ACCEL5_REG_GEN2_INT_CONFIG_4 0x4F
147#define ACCEL5_REG_GEN2_INT_CONFIG_5 0x50
148#define ACCEL5_REG_GEN2_INT_CONFIG_6 0x51
149#define ACCEL5_REG_GEN2_INT_CONFIG_7 0x52
150#define ACCEL5_REG_GEN2_INT_CONFIG_8 0x53
151#define ACCEL5_REG_GEN2_INT_CONFIG_9 0x54
152#define ACCEL5_REG_ACTCH_CONFIG_0 0x55
153#define ACCEL5_REG_ACTCH_CONFIG_1 0x56
154#define ACCEL5_REG_TAP_CONFIG_0 0x57
155#define ACCEL5_REG_TAP_CONFIG_1 0x58
156#define ACCEL5_REG_STEP_CNT_CONFIG_0 0x59
157#define ACCEL5_REG_STEP_CNT_CONFIG_1 0x5A
158#define ACCEL5_REG_STEP_CNT_CONFIG_2 0x5B
159#define ACCEL5_REG_STEP_CNT_CONFIG_3 0x5C
160#define ACCEL5_REG_STEP_CNT_CONFIG_4 0x5D
161#define ACCEL5_REG_STEP_CNT_CONFIG_5 0x5E
162#define ACCEL5_REG_STEP_CNT_CONFIG_6 0x5F
163#define ACCEL5_REG_STEP_CNT_CONFIG_7 0x60
164#define ACCEL5_REG_STEP_CNT_CONFIG_8 0x61
165#define ACCEL5_REG_STEP_CNT_CONFIG_9 0x62
166#define ACCEL5_REG_STEP_CNT_CONFIG_10 0x63
167#define ACCEL5_REG_STEP_CNT_CONFIG_11 0x64
168#define ACCEL5_REG_STEP_CNT_CONFIG_12 0x65
169#define ACCEL5_REG_STEP_CNT_CONFIG_13 0x66
170#define ACCEL5_REG_STEP_CNT_CONFIG_14 0x67
171#define ACCEL5_REG_STEP_CNT_CONFIG_15 0x68
172#define ACCEL5_REG_STEP_CNT_CONFIG_16 0x69
173#define ACCEL5_REG_STEP_CNT_CONFIG_17 0x6A
174#define ACCEL5_REG_STEP_CNT_CONFIG_18 0x6B
175#define ACCEL5_REG_STEP_CNT_CONFIG_19 0x6C
176#define ACCEL5_REG_STEP_CNT_CONFIG_20 0x6D
177#define ACCEL5_REG_STEP_CNT_CONFIG_21 0x6E
178#define ACCEL5_REG_STEP_CNT_CONFIG_22 0x6F
179#define ACCEL5_REG_STEP_CNT_CONFIG_23 0x70
180#define ACCEL5_REG_STEP_CNT_CONFIG_24 0x71
181#define ACCEL5_REG_IF_CONFIG 0x7C
182#define ACCEL5_REG_SELF_TEST 0x7D
183#define ACCEL5_REG_CMD 0x7E
190#define ACCEL5_ERROR_CMD 0x02
197#define ACCEL5_STATUS_DATA_RDY_START 0x80
198#define ACCEL5_STATUS_RDY_CMD 0x10
199#define ACCEL5_STATUS_NORMAL_MODE 0x04
200#define ACCEL5_STATUS_LOW_POWER_MODE 0x02
201#define ACCEL5_STATUS_SLEEP_MODE 0x04
202#define ACCEL5_STATUS_INT_ACTIVE_TRIGGERED 0x01
203#define ACCEL5_STATUS_INT_ACTIVE_NOT_TRIGGERED 0x00
210#define ACCEL5_EVENT_POR_DETECTED 0x01
217#define ACCEL5_INT_STATUS_0_DATA_RDY_STATUS 0x80
218#define ACCEL5_INT_STATUS_0_FIFO_WATERMARK 0x40
219#define ACCEL5_INT_STATUS_0_FIFO_FULL 0x20
220#define ACCEL5_INT_STATUS_0_IENG_OVERRUN_STATUS 0x10
221#define ACCEL5_INT_STATUS_0_GEN2_INT_STATUS 0x08
222#define ACCEL5_INT_STATUS_0_GEN1_INT_STATUS 0x04
223#define ACCEL5_INT_STATUS_0_ORIENTCH_INT_STATUS 0x02
224#define ACCEL5_INT_STATUS_0_WAKEUP_INT_STATUS 0x01
231#define ACCEL5_INT_STATUS_1_IENG_OVERRUN_STATUS 0x10
232#define ACCEL5_INT_STATUS_1_DOUBLE_TAP 0x08
233#define ACCEL5_INT_STATUS_1_SINGLE_TAP 0x04
234#define ACCEL5_INT_STATUS_1_STEP_NO_SET 0x00
235#define ACCEL5_INT_STATUS_1_STEP_SET 0x01
236#define ACCEL5_INT_STATUS_1_STEP_DETECT 0x02
237#define ACCEL5_INT_STATUS_1_STEP_NO_USED 0x03
244#define ACCEL5_INT_STATUS_2_IENG_OVERRUN_STATUS 0x10
245#define ACCEL5_INT_STATUS_2_ACTCH_Z_INIT_STATUS 0x04
246#define ACCEL5_INT_STATUS_2_ACTCH_Y_INIT_STATUS 0x02
247#define ACCEL5_INT_STATUS_2_ACTCH_X_INIT_STATUS 0x01
254#define ACCEL5_STEP_STATUS_WALKING 0x01
255#define ACCEL5_STEP_STATUS_RUNNING 0x02
256#define ACCEL5_STEP_STATUS_NO_WALK_RUN 0x00
263#define ACCEL5_CFG_0_FILT1_BW_LOW_0_2X_ODR 0x80
264#define ACCEL5_CFG_0_FILT1_BW_HIGH_0_4X_ODR 0x00
265#define ACCEL5_CFG_0_SLEEP_MODE 0x00
266#define ACCEL5_CFG_0_LOW_POWER_MODE 0x01
267#define ACCEL5_CFG_0_NORMAL_MODE 0x02
274#define ACCEL5_CFG_1_ACC_RANGE_2g 0x00
275#define ACCEL5_CFG_1_ACC_RANGE_4g 0x40
276#define ACCEL5_CFG_1_ACC_RANGE_8g 0x80
277#define ACCEL5_CFG_1_ACC_RANGE_16g 0xC0
278#define ACCEL5_CFG_1_OSR_LOW_POWER 0x00
279#define ACCEL5_CFG_1_OSR_HIGH_POWER 0x30
280#define ACCEL5_CFG_1_ODR_12p5_5 0x00
281#define ACCEL5_CFG_1_ODR_12p5_4 0x01
282#define ACCEL5_CFG_1_ODR_12p5_3 0x02
283#define ACCEL5_CFG_1_ODR_12p5_2 0x03
284#define ACCEL5_CFG_1_ODR_12p5_1 0x04
285#define ACCEL5_CFG_1_ODR_12p5 0x05
286#define ACCEL5_CFG_1_ODR_25 0x06
287#define ACCEL5_CFG_1_ODR_50 0x07
288#define ACCEL5_CFG_1_ODR_100 0x08
289#define ACCEL5_CFG_1_ODR_200 0x09
290#define ACCEL5_CFG_1_ODR_400 0x0A
291#define ACCEL5_CFG_1_ODR_800 0x0B
292#define ACCEL5_CFG_1_ODR_800_1 0x0C
293#define ACCEL5_CFG_1_ODR_800_2 0x0D
294#define ACCEL5_CFG_1_ODR_800_3 0x0E
295#define ACCEL5_CFG_1_ODR_800_4 0x0F
302#define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_1 0x00
303#define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_2 0x04
304#define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_LP 0x08
311#define ACCEL5_INT_CFG_0_DATA_RDY 0x80
312#define ACCEL5_INT_CFG_0_FIFO_WATERMARK 0x40
313#define ACCEL5_INT_CFG_0_FIFO_FULL 0x20
314#define ACCEL5_INT_CFG_0_GEN2_INT_STATUS 0x08
315#define ACCEL5_INT_CFG_0_GEN1_INT_STATUS 0x04
316#define ACCEL5_INT_CFG_0_ORIENTCH_INT 0x02
323#define ACCEL5_INT_CFG_1_LATCH_MODE_NOLATCH 0x00
324#define ACCEL5_INT_CFG_1_LATCH_MODE_LATCHING 0x80
325#define ACCEL5_INT_CFG_1_ACTCH_INT_ENABLE 0x10
326#define ACCEL5_INT_CFG_1_DOUBLE_TAP_ENABLE 0x08
327#define ACCEL5_INT_CFG_1_SINGLE_TAP_ENABLE 0x04
328#define ACCEL5_INT_CFG_1_STEP_INT_ENABLE 0x01
335#define ACCEL5_INT1_MAP_DATA_RDY_STATUS 0x80
336#define ACCEL5_INT1_MAP_FIFO_WATERMARK 0x40
337#define ACCEL5_INT1_MAP_FIFO_FULL 0x20
338#define ACCEL5_INT1_MAP_IENG_OVERRUN_STATUS 0x10
339#define ACCEL5_INT1_MAP_GEN2_INT_STATUS 0x08
340#define ACCEL5_INT1_MAP_GEN1_INT_STATUS 0x04
341#define ACCEL5_INT1_MAP_ORIENTCH_INT_STATUS 0x02
342#define ACCEL5_INT1_MAP_WAKEUP_INT_STATUS 0x01
349#define ACCEL5_INT2_MAP_DATA_RDY_STATUS 0x80
350#define ACCEL5_INT2_MAP_FIFO_WATERMARK 0x40
351#define ACCEL5_INT2_MAP_FIFO_FULL 0x20
352#define ACCEL5_INT2_MAP_IENG_OVERRUN_STATUS 0x10
353#define ACCEL5_INT2_MAP_GEN2_INT_STATUS 0x08
354#define ACCEL5_INT2_MAP_GEN1_INT_STATUS 0x04
355#define ACCEL5_INT2_MAP_ORIENTCH_INT_STATUS 0x02
356#define ACCEL5_INT2_MAP_WAKEUP_INT_STATUS 0x01
363#define ACCEL5_INT12_MAP_ACTCH_INT2 0x80
364#define ACCEL5_INT12_MAP_TAP_INT2 0x40
365#define ACCEL5_INT12_MAP_STEP_INT2 0x10
366#define ACCEL5_INT12_MAP_ACTCH_INT1 0x08
367#define ACCEL5_INT12_MAP_TAP_INT1 0x04
368#define ACCEL5_INT12_MAP_STEP_INT1 0x01
375#define ACCEL5_INT12_CTRL_INT2_OPEN_DRAIN 0x40
376#define ACCEL5_INT12_CTRL_INT1_OPEN_DRAIN 0x04
377#define ACCEL5_INT12_CTRL_INT2_HIGH_ACTIVE 0x20
378#define ACCEL5_INT12_CTRL_INT1_HIGH_ACTIVE 0x02
385#define ACCEL5_FIFO_CFG0_Z_AXIS_ENABLE 0x80
386#define ACCEL5_FIFO_CFG0_Y_AXIS_ENABLE 0x40
387#define ACCEL5_FIFO_CFG0_X_AXIS_ENABLE 0x20
388#define ACCEL5_FIFO_CFG0_8bit_ENABLE 0x10
389#define ACCEL5_FIFO_CFG0_DATA_SRC_ENABLE 0x08
390#define ACCEL5_FIFO_CFG0_TIME_ENABLE 0x04
391#define ACCEL5_FIFO_CFG0_STOP_NO_FULL_ENABLE 0x02
392#define ACCEL5_FIFO_CFG0_AUTO_FLUSH_ENABLE 0x01
399#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_0 0x00
400#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_1 0x04
401#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_2 0x08
402#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_3 0x0C
403#define ACCEL5_FIFO_AUTO_TRIG_GEN1_INT 0x02
404#define ACCEL5_FIFO_AUTO_TRIG_DATA_RDY 0x01
411#define ACCEL5_WAKEUP_TIMEOUT_ENABLE 0x04
412#define ACCEL5_WAKEUP_ENABLE 0x02
419#define ACCEL5_WAKEUP_Z_AXIS_ENABLE 0x80
420#define ACCEL5_WAKEUP_Y_AXIS_ENABLE 0x40
421#define ACCEL5_WAKEUP_X_AXIS_ENABLE 0x20
422#define ACCEL5_WAKEUP_NUMBER_OF_SIMPLE 0x10
423#define ACCEL5_WAKEUP_REFU_MANUAL 0x00
424#define ACCEL5_WAKEUP_REFU_ONETIME 0x01
425#define ACCEL5_WAKEUP_REFU_EVERYTIME 0x02
432#define ACCEL5_ORIENT_Z_AXIS_ENABLE 0x80
433#define ACCEL5_ORIENT_Y_AXIS_ENABLE 0x40
434#define ACCEL5_ORIENT_X_AXIS_ENABLE 0x20
435#define ACCEL5_ORIENT_DATA_SRC_ENABLE 0x10
436#define ACCEL5_ORIENT_REFU_MANUAL 0x00
437#define ACCEL5_ORIENT_REFU_ONETIME_2 0x04
438#define ACCEL5_ORIENT_REFU_ONETIME_IP 0x08
439#define ACCEL5_ORIENT_STABILITY_INACTIVE 0x00
440#define ACCEL5_ORIENT_STABILITY_ENABLED_1 0x01
441#define ACCEL5_ORIENT_STABILITY_ENABLED_2 0x02
448#define ACCEL5_GEN1_CFG0_ACT_Z_ENABLE 0x80
449#define ACCEL5_GEN1_CFG0_ACT_Y_ENABLE 0x40
450#define ACCEL5_GEN1_CFG0_ACT_X_ENABLE 0x20
451#define ACCEL5_GEN1_CFG0_DATA_ENABLE 0x10
452#define ACCEL5_GEN1_CFG0_REFU_MANUAL 0x00
453#define ACCEL5_GEN1_CFG0_REFU_ONETIME 0x04
454#define ACCEL5_GEN1_CFG0_REFU_EVERYTIME 0x08
455#define ACCEL5_GEN1_CFG0_HYST_24mg 0x01
456#define ACCEL5_GEN1_CFG0_HYST_48mg 0x02
457#define ACCEL5_GEN1_CFG0_HYST_96mg 0x03
458#define ACCEL5_GEN1_CFG0_HYST_NO_ACTIVE 0x00
465#define ACCEL5_GEN1_CFG1_CRITERION_SEL_ACTIVE 0x20
466#define ACCEL5_GEN1_CFG1_CRITERION_SEL_INACTIVE 0x00
467#define ACCEL5_GEN1_CFG1_COMB_SEL_AND 0x10
468#define ACCEL5_GEN1_CFG1_COMB_SEL_OR 0x00
475#define ACCEL5_GEN2_CFG0_ACT_Z_ENABLE 0x80
476#define ACCEL5_GEN2_CFG0_ACT_Y_ENABLE 0x40
477#define ACCEL5_GEN2_CFG0_ACT_X_ENABLE 0x20
478#define ACCEL5_GEN2_CFG0_DATA_ENABLE 0x10
479#define ACCEL5_GEN2_CFG0_REFU_MANUAL 0x00
480#define ACCEL5_GEN2_CFG0_REFU_ONETIME 0x04
481#define ACCEL5_GEN2_CFG0_REFU_EVERYTIME 0x08
482#define ACCEL5_GEN2_CFG0_HYST_24mg 0x01
483#define ACCEL5_GEN2_CFG0_HYST_48mg 0x02
484#define ACCEL5_GEN2_CFG0_HYST_96mg 0x03
485#define ACCEL5_GEN2_CFG0_HYST_NO_ACTIVE 0x00
492#define ACCEL5_GEN2_CFG1_CRITERION_SEL_ACTIVE 0x20
493#define ACCEL5_GEN2_CFG1_CRITERION_SEL_INACTIVE 0x00
494#define ACCEL5_GEN2_CFG1_COMB_SEL_AND 0x10
495#define ACCEL5_GEN2_CFG1_COMB_SEL_OR 0x00
502#define ACCEL5_ACTCH_CFG0_Z_AXIS_ENABLE 0x80
503#define ACCEL5_ACTCH_CFG0_Y_AXIS_ENABLE 0x40
504#define ACCEL5_ACTCH_CFG0_X_AXIS_ENABLE 0x20
505#define ACCEL5_ACTCH_CFG0_DATA_ENABLE 0x10
506#define ACCEL5_ACTCH_CFG0_NPTS_POINT_32 0x00
507#define ACCEL5_ACTCH_CFG0_NPTS_POINT_64 0x01
508#define ACCEL5_ACTCH_CFG0_NPTS_POINT_128 0x02
509#define ACCEL5_ACTCH_CFG0_NPTS_POINT_256 0x03
510#define ACCEL5_ACTCH_CFG0_NPTS_POINT_512 0x04
517#define ACCEL5_TAP_CFG0_USE_Z_AXIS 0x00
518#define ACCEL5_TAP_CFG0_USE_Y_AXIS 0x01
519#define ACCEL5_TAP_CFG0_USE_X_AXIS 0x02
520#define ACCEL5_TAP_CFG0_TAP_SEL_HIGH 0x00
521#define ACCEL5_TAP_CFG0_TAP_SEL_LOW 0x10
528#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_4 0x00
529#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_8 0x10
530#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_12 0x20
531#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_16 0x30
532#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_60 0x00
533#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_80 0x04
534#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_100 0x08
535#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_120 0x0C
536#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_6 0x00
537#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_9 0x01
538#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_12 0x02
539#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_18 0x03
546#define ACCEL5_IF_CONFIG_SPI_4_WIRE 0x00
547#define ACCEL5_IF_CONFIG_SPI_3_WIRE 0x01
554#define ACCEL5_TEST_SIGN_ENABLE 0x08
555#define ACCEL5_TEST_Z_AXIS_ENABLE 0x04
556#define ACCEL5_TEST_Y_AXIS_ENABLE 0x02
557#define ACCEL5_TEST_X_AXIS_ENABLE 0x01
564#define ACCEL5_CMD_FIFO_FLUSH 0xB0
565#define ACCEL5_CMD_STEP_CNT_CLEAR 0xB1
566#define ACCEL5_CMD_SOFTWARE_RESET 0xB6
573#define ACCEL5_X_AXIS 0x04
574#define ACCEL5_Y_AXIS 0x06
575#define ACCEL5_Z_AXIS 0x08
582#define DEVICE_ERROR 0x01
583#define DEVICE_OK 0x00 // End group macro
587// --------------------------------------------------------------- PUBLIC TYPES
596typedef struct
597{
598
599 // Input pins
600
601 digital_in_t it2;
602 digital_in_t it1;
603
604 // Modules
605
606 i2c_master_t i2c;
607
608 // ctx variable
609
611
612} accel5_t;
613
617typedef struct
618{
619 // Communication gpio pins
620
621 pin_name_t scl;
622 pin_name_t sda;
623
624 // Additional gpio pins
625
626 pin_name_t it2;
627 pin_name_t it1;
628
629 // static variable
630
631 uint32_t i2c_speed;
632 uint8_t i2c_address;
633
635 // End types group
637
638// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
639
645#ifdef __cplusplus
646extern "C"{
647#endif
648
656
664err_t accel5_init ( accel5_t *ctx, accel5_cfg_t *cfg );
665
674err_t accel5_generic_write ( accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
675
684err_t accel5_generic_read ( accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );
685
696void accel5_default_cfg ( accel5_t *ctx, uint8_t mode, uint8_t range );
697
706void accel5_write_byte ( accel5_t *ctx, uint8_t reg, uint8_t reg_data );
707
715uint8_t accel5_read_byte ( accel5_t *ctx, uint8_t reg );
716
724uint16_t accel5_read_data ( accel5_t *ctx, uint8_t reg );
725
733int16_t accel5_get_axis ( accel5_t *ctx, uint8_t axis );
734
743uint32_t accel5_sensor_time ( accel5_t *ctx );
744
752
760
761
762#ifdef __cplusplus
763}
764#endif
765#endif // ACCEL5_H
766 // End public_function group // End click Driver group
769
770// ------------------------------------------------------------------------ END
void accel5_default_cfg(accel5_t *ctx, uint8_t mode, uint8_t range)
Click Default Configuration function..
uint32_t accel5_sensor_time(accel5_t *ctx)
Functions for initialize the chip.
err_t accel5_init(accel5_t *ctx, accel5_cfg_t *cfg)
Initialization function.
int16_t accel5_get_axis(accel5_t *ctx, uint8_t axis)
Functions for read axis data.
err_t accel5_generic_read(accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
uint16_t accel5_read_data(accel5_t *ctx, uint8_t reg)
Functions for read data from register.
uint8_t accel5_read_byte(accel5_t *ctx, uint8_t reg)
Functions for read byte from register.
float accel5_get_temperature(accel5_t *ctx)
Functions for read temperature.
void accel5_write_byte(accel5_t *ctx, uint8_t reg, uint8_t reg_data)
Functions for write one byte in register.
void accel5_cfg_setup(accel5_cfg_t *cfg)
Config Object Initialization function.
err_t accel5_generic_write(accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
void accel5_soft_reset(accel5_t *ctx)
Functions for software reset.
Click configuration structure definition.
Definition: accel5.h:618
pin_name_t it2
Definition: accel5.h:626
uint32_t i2c_speed
Definition: accel5.h:631
pin_name_t it1
Definition: accel5.h:627
pin_name_t scl
Definition: accel5.h:621
pin_name_t sda
Definition: accel5.h:622
uint8_t i2c_address
Definition: accel5.h:632
Click ctx object definition.
Definition: accel5.h:597
digital_in_t it2
Definition: accel5.h:601
i2c_master_t i2c
Definition: accel5.h:606
uint8_t slave_address
Definition: accel5.h:610
digital_in_t it1
Definition: accel5.h:602