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33 #include "mikrosdk_version.h"
36 #if mikroSDK_GET_VERSION < 20800ul
37 #include "rcu_delays.h"
43 #include "drv_digital_out.h"
44 #include "drv_digital_in.h"
45 #include "drv_i2c_master.h"
57 #define ACCEL5_MAP_MIKROBUS( cfg, mikrobus ) \
58 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
59 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
60 cfg.it2 = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
61 cfg.it1 = MIKROBUS( mikrobus, MIKROBUS_INT );
70 #define ACCEL5_INIT_ERROR (-1)
77 #define ACCEL5_CHIP_ID 0x90
84 #define ACCEL5_REG_CHIP_ID 0x00
85 #define ACCEL5_REG_ERR_REG 0x02
86 #define ACCEL5_REG_STATUS 0x03
87 #define ACCEL5_REG_ACC_X_LSB 0x04
88 #define ACCEL5_REG_ACC_X_MSB 0x05
89 #define ACCEL5_REG_ACC_Y_LSB 0x06
90 #define ACCEL5_REG_ACC_Y_MSB 0x07
91 #define ACCEL5_REG_ACC_Z_LSB 0x08
92 #define ACCEL5_REG_ACC_Z_MSB 0x09
93 #define ACCEL5_REG_SENSOR_TIME_0 0x0A
94 #define ACCEL5_REG_SENSOR_TIME_1 0x0B
95 #define ACCEL5_REG_SENSOR_TIME_2 0x0C
96 #define ACCEL5_REG_EVENT 0x0D
97 #define ACCEL5_REG_INT_STATUS_0 0x0E
98 #define ACCEL5_REG_INT_STATUS_1 0x0F
99 #define ACCEL5_REG_INT_STATUS_2 0x10
100 #define ACCEL5_REG_TEMPERATURE 0x11
101 #define ACCEL5_REG_FIFO_LENGTH_0 0x12
102 #define ACCEL5_REG_FIFO_LENGTH_1 0x13
103 #define ACCEL5_REG_FIFO_DATA 0x14
104 #define ACCEL5_REG_STEP_CNT_0 0x15
105 #define ACCEL5_REG_STEP_CNT_1 0x16
106 #define ACCEL5_REG_STEP_CNT_2 0x17
107 #define ACCEL5_REG_STEP_STATUS 0x18
108 #define ACCEL5_REG_ACC_CONGIG_0 0x19
109 #define ACCEL5_REG_ACC_CONGIG_1 0x1A
110 #define ACCEL5_REG_ACC_CONGIG_2 0x1B
111 #define ACCEL5_REG_INT_CONFIG_0 0x1F
112 #define ACCEL5_REG_INT_CONFIG_1 0x20
113 #define ACCEL5_REG_INT1_MAP 0x21
114 #define ACCEL5_REG_INT2_MAP 0x22
115 #define ACCEL5_REG_INT12_MAP 0x23
116 #define ACCEL5_REG_INT12_IO_CTRL 0x24
117 #define ACCEL5_REG_FIFO_CONFIG_0 0x26
118 #define ACCEL5_REG_FIFO_CONFIG_1 0x27
119 #define ACCEL5_REG_FIFO_CONFIG_2 0x28
120 #define ACCEL5_REG_FIFO_PWR_CONFIG 0x29
121 #define ACCEL5_REG_AUTO_LOW_POW_0 0x2A
122 #define ACCEL5_REG_AUTO_LOW_POW_1 0x2B
123 #define ACCEL5_REG_AUTO_WAKEUP_0 0x2C
124 #define ACCEL5_REG_AUTO_WAKEUP_1 0x2D
125 #define ACCEL5_REG_WAKEUP_CONFIG_0 0x2F
126 #define ACCEL5_REG_WAKEUP_CONFIG_1 0x30
127 #define ACCEL5_REG_WAKEUP_CONFIG_2 0x31
128 #define ACCEL5_REG_WAKEUP_CONFIG_3 0x32
129 #define ACCEL5_REG_WAKEUP_CONFIG_4 0x33
130 #define ACCEL5_REG_ORIENTCH_CONFIG_0 0x35
131 #define ACCEL5_REG_ORIENTCH_CONFIG_1 0x36
132 #define ACCEL5_REG_ORIENTCH_CONFIG_2 0x37
133 #define ACCEL5_REG_ORIENTCH_CONFIG_3 0x38
134 #define ACCEL5_REG_ORIENTCH_CONFIG_4 0x39
135 #define ACCEL5_REG_ORIENTCH_CONFIG_5 0x3A
136 #define ACCEL5_REG_ORIENTCH_CONFIG_6 0x3B
137 #define ACCEL5_REG_ORIENTCH_CONFIG_7 0x3C
138 #define ACCEL5_REG_ORIENTCH_CONFIG_8 0x3D
139 #define ACCEL5_REG_ORIENTCH_CONFIG_9 0x3E
140 #define ACCEL5_REG_GEN1_INT_CONFIG_0 0x3F
141 #define ACCEL5_REG_GEN1_INT_CONFIG_1 0x40
142 #define ACCEL5_REG_GEN1_INT_CONFIG_2 0x41
143 #define ACCEL5_REG_GEN1_INT_CONFIG_3 0x42
144 #define ACCEL5_REG_GEN1_INT_CONFIG_31 0x43
145 #define ACCEL5_REG_GEN1_INT_CONFIG_4 0x44
146 #define ACCEL5_REG_GEN1_INT_CONFIG_5 0x45
147 #define ACCEL5_REG_GEN1_INT_CONFIG_6 0x46
148 #define ACCEL5_REG_GEN1_INT_CONFIG_7 0x47
149 #define ACCEL5_REG_GEN1_INT_CONFIG_8 0x48
150 #define ACCEL5_REG_GEN1_INT_CONFIG_9 0x49
151 #define ACCEL5_REG_GEN2_INT_CONFIG_0 0x4A
152 #define ACCEL5_REG_GEN2_INT_CONFIG_1 0x4B
153 #define ACCEL5_REG_GEN2_INT_CONFIG_2 0x4C
154 #define ACCEL5_REG_GEN2_INT_CONFIG_3 0x4D
155 #define ACCEL5_REG_GEN2_INT_CONFIG_31 0x4E
156 #define ACCEL5_REG_GEN2_INT_CONFIG_4 0x4F
157 #define ACCEL5_REG_GEN2_INT_CONFIG_5 0x50
158 #define ACCEL5_REG_GEN2_INT_CONFIG_6 0x51
159 #define ACCEL5_REG_GEN2_INT_CONFIG_7 0x52
160 #define ACCEL5_REG_GEN2_INT_CONFIG_8 0x53
161 #define ACCEL5_REG_GEN2_INT_CONFIG_9 0x54
162 #define ACCEL5_REG_ACTCH_CONFIG_0 0x55
163 #define ACCEL5_REG_ACTCH_CONFIG_1 0x56
164 #define ACCEL5_REG_TAP_CONFIG_0 0x57
165 #define ACCEL5_REG_TAP_CONFIG_1 0x58
166 #define ACCEL5_REG_STEP_CNT_CONFIG_0 0x59
167 #define ACCEL5_REG_STEP_CNT_CONFIG_1 0x5A
168 #define ACCEL5_REG_STEP_CNT_CONFIG_2 0x5B
169 #define ACCEL5_REG_STEP_CNT_CONFIG_3 0x5C
170 #define ACCEL5_REG_STEP_CNT_CONFIG_4 0x5D
171 #define ACCEL5_REG_STEP_CNT_CONFIG_5 0x5E
172 #define ACCEL5_REG_STEP_CNT_CONFIG_6 0x5F
173 #define ACCEL5_REG_STEP_CNT_CONFIG_7 0x60
174 #define ACCEL5_REG_STEP_CNT_CONFIG_8 0x61
175 #define ACCEL5_REG_STEP_CNT_CONFIG_9 0x62
176 #define ACCEL5_REG_STEP_CNT_CONFIG_10 0x63
177 #define ACCEL5_REG_STEP_CNT_CONFIG_11 0x64
178 #define ACCEL5_REG_STEP_CNT_CONFIG_12 0x65
179 #define ACCEL5_REG_STEP_CNT_CONFIG_13 0x66
180 #define ACCEL5_REG_STEP_CNT_CONFIG_14 0x67
181 #define ACCEL5_REG_STEP_CNT_CONFIG_15 0x68
182 #define ACCEL5_REG_STEP_CNT_CONFIG_16 0x69
183 #define ACCEL5_REG_STEP_CNT_CONFIG_17 0x6A
184 #define ACCEL5_REG_STEP_CNT_CONFIG_18 0x6B
185 #define ACCEL5_REG_STEP_CNT_CONFIG_19 0x6C
186 #define ACCEL5_REG_STEP_CNT_CONFIG_20 0x6D
187 #define ACCEL5_REG_STEP_CNT_CONFIG_21 0x6E
188 #define ACCEL5_REG_STEP_CNT_CONFIG_22 0x6F
189 #define ACCEL5_REG_STEP_CNT_CONFIG_23 0x70
190 #define ACCEL5_REG_STEP_CNT_CONFIG_24 0x71
191 #define ACCEL5_REG_IF_CONFIG 0x7C
192 #define ACCEL5_REG_SELF_TEST 0x7D
193 #define ACCEL5_REG_CMD 0x7E
200 #define ACCEL5_ERROR_CMD 0x02
207 #define ACCEL5_STATUS_DATA_RDY_START 0x80
208 #define ACCEL5_STATUS_RDY_CMD 0x10
209 #define ACCEL5_STATUS_NORMAL_MODE 0x04
210 #define ACCEL5_STATUS_LOW_POWER_MODE 0x02
211 #define ACCEL5_STATUS_SLEEP_MODE 0x04
212 #define ACCEL5_STATUS_INT_ACTIVE_TRIGGERED 0x01
213 #define ACCEL5_STATUS_INT_ACTIVE_NOT_TRIGGERED 0x00
220 #define ACCEL5_EVENT_POR_DETECTED 0x01
227 #define ACCEL5_INT_STATUS_0_DATA_RDY_STATUS 0x80
228 #define ACCEL5_INT_STATUS_0_FIFO_WATERMARK 0x40
229 #define ACCEL5_INT_STATUS_0_FIFO_FULL 0x20
230 #define ACCEL5_INT_STATUS_0_IENG_OVERRUN_STATUS 0x10
231 #define ACCEL5_INT_STATUS_0_GEN2_INT_STATUS 0x08
232 #define ACCEL5_INT_STATUS_0_GEN1_INT_STATUS 0x04
233 #define ACCEL5_INT_STATUS_0_ORIENTCH_INT_STATUS 0x02
234 #define ACCEL5_INT_STATUS_0_WAKEUP_INT_STATUS 0x01
241 #define ACCEL5_INT_STATUS_1_IENG_OVERRUN_STATUS 0x10
242 #define ACCEL5_INT_STATUS_1_DOUBLE_TAP 0x08
243 #define ACCEL5_INT_STATUS_1_SINGLE_TAP 0x04
244 #define ACCEL5_INT_STATUS_1_STEP_NO_SET 0x00
245 #define ACCEL5_INT_STATUS_1_STEP_SET 0x01
246 #define ACCEL5_INT_STATUS_1_STEP_DETECT 0x02
247 #define ACCEL5_INT_STATUS_1_STEP_NO_USED 0x03
254 #define ACCEL5_INT_STATUS_2_IENG_OVERRUN_STATUS 0x10
255 #define ACCEL5_INT_STATUS_2_ACTCH_Z_INIT_STATUS 0x04
256 #define ACCEL5_INT_STATUS_2_ACTCH_Y_INIT_STATUS 0x02
257 #define ACCEL5_INT_STATUS_2_ACTCH_X_INIT_STATUS 0x01
264 #define ACCEL5_STEP_STATUS_WALKING 0x01
265 #define ACCEL5_STEP_STATUS_RUNNING 0x02
266 #define ACCEL5_STEP_STATUS_NO_WALK_RUN 0x00
273 #define ACCEL5_CFG_0_FILT1_BW_LOW_0_2X_ODR 0x80
274 #define ACCEL5_CFG_0_FILT1_BW_HIGH_0_4X_ODR 0x00
275 #define ACCEL5_CFG_0_SLEEP_MODE 0x00
276 #define ACCEL5_CFG_0_LOW_POWER_MODE 0x01
277 #define ACCEL5_CFG_0_NORMAL_MODE 0x02
284 #define ACCEL5_CFG_1_ACC_RANGE_2g 0x00
285 #define ACCEL5_CFG_1_ACC_RANGE_4g 0x40
286 #define ACCEL5_CFG_1_ACC_RANGE_8g 0x80
287 #define ACCEL5_CFG_1_ACC_RANGE_16g 0xC0
288 #define ACCEL5_CFG_1_OSR_LOW_POWER 0x00
289 #define ACCEL5_CFG_1_OSR_HIGH_POWER 0x30
290 #define ACCEL5_CFG_1_ODR_12p5_5 0x00
291 #define ACCEL5_CFG_1_ODR_12p5_4 0x01
292 #define ACCEL5_CFG_1_ODR_12p5_3 0x02
293 #define ACCEL5_CFG_1_ODR_12p5_2 0x03
294 #define ACCEL5_CFG_1_ODR_12p5_1 0x04
295 #define ACCEL5_CFG_1_ODR_12p5 0x05
296 #define ACCEL5_CFG_1_ODR_25 0x06
297 #define ACCEL5_CFG_1_ODR_50 0x07
298 #define ACCEL5_CFG_1_ODR_100 0x08
299 #define ACCEL5_CFG_1_ODR_200 0x09
300 #define ACCEL5_CFG_1_ODR_400 0x0A
301 #define ACCEL5_CFG_1_ODR_800 0x0B
302 #define ACCEL5_CFG_1_ODR_800_1 0x0C
303 #define ACCEL5_CFG_1_ODR_800_2 0x0D
304 #define ACCEL5_CFG_1_ODR_800_3 0x0E
305 #define ACCEL5_CFG_1_ODR_800_4 0x0F
312 #define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_1 0x00
313 #define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_2 0x04
314 #define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_LP 0x08
321 #define ACCEL5_INT_CFG_0_DATA_RDY 0x80
322 #define ACCEL5_INT_CFG_0_FIFO_WATERMARK 0x40
323 #define ACCEL5_INT_CFG_0_FIFO_FULL 0x20
324 #define ACCEL5_INT_CFG_0_GEN2_INT_STATUS 0x08
325 #define ACCEL5_INT_CFG_0_GEN1_INT_STATUS 0x04
326 #define ACCEL5_INT_CFG_0_ORIENTCH_INT 0x02
333 #define ACCEL5_INT_CFG_1_LATCH_MODE_NOLATCH 0x00
334 #define ACCEL5_INT_CFG_1_LATCH_MODE_LATCHING 0x80
335 #define ACCEL5_INT_CFG_1_ACTCH_INT_ENABLE 0x10
336 #define ACCEL5_INT_CFG_1_DOUBLE_TAP_ENABLE 0x08
337 #define ACCEL5_INT_CFG_1_SINGLE_TAP_ENABLE 0x04
338 #define ACCEL5_INT_CFG_1_STEP_INT_ENABLE 0x01
345 #define ACCEL5_INT1_MAP_DATA_RDY_STATUS 0x80
346 #define ACCEL5_INT1_MAP_FIFO_WATERMARK 0x40
347 #define ACCEL5_INT1_MAP_FIFO_FULL 0x20
348 #define ACCEL5_INT1_MAP_IENG_OVERRUN_STATUS 0x10
349 #define ACCEL5_INT1_MAP_GEN2_INT_STATUS 0x08
350 #define ACCEL5_INT1_MAP_GEN1_INT_STATUS 0x04
351 #define ACCEL5_INT1_MAP_ORIENTCH_INT_STATUS 0x02
352 #define ACCEL5_INT1_MAP_WAKEUP_INT_STATUS 0x01
359 #define ACCEL5_INT2_MAP_DATA_RDY_STATUS 0x80
360 #define ACCEL5_INT2_MAP_FIFO_WATERMARK 0x40
361 #define ACCEL5_INT2_MAP_FIFO_FULL 0x20
362 #define ACCEL5_INT2_MAP_IENG_OVERRUN_STATUS 0x10
363 #define ACCEL5_INT2_MAP_GEN2_INT_STATUS 0x08
364 #define ACCEL5_INT2_MAP_GEN1_INT_STATUS 0x04
365 #define ACCEL5_INT2_MAP_ORIENTCH_INT_STATUS 0x02
366 #define ACCEL5_INT2_MAP_WAKEUP_INT_STATUS 0x01
373 #define ACCEL5_INT12_MAP_ACTCH_INT2 0x80
374 #define ACCEL5_INT12_MAP_TAP_INT2 0x40
375 #define ACCEL5_INT12_MAP_STEP_INT2 0x10
376 #define ACCEL5_INT12_MAP_ACTCH_INT1 0x08
377 #define ACCEL5_INT12_MAP_TAP_INT1 0x04
378 #define ACCEL5_INT12_MAP_STEP_INT1 0x01
385 #define ACCEL5_INT12_CTRL_INT2_OPEN_DRAIN 0x40
386 #define ACCEL5_INT12_CTRL_INT1_OPEN_DRAIN 0x04
387 #define ACCEL5_INT12_CTRL_INT2_HIGH_ACTIVE 0x20
388 #define ACCEL5_INT12_CTRL_INT1_HIGH_ACTIVE 0x02
395 #define ACCEL5_FIFO_CFG0_Z_AXIS_ENABLE 0x80
396 #define ACCEL5_FIFO_CFG0_Y_AXIS_ENABLE 0x40
397 #define ACCEL5_FIFO_CFG0_X_AXIS_ENABLE 0x20
398 #define ACCEL5_FIFO_CFG0_8bit_ENABLE 0x10
399 #define ACCEL5_FIFO_CFG0_DATA_SRC_ENABLE 0x08
400 #define ACCEL5_FIFO_CFG0_TIME_ENABLE 0x04
401 #define ACCEL5_FIFO_CFG0_STOP_NO_FULL_ENABLE 0x02
402 #define ACCEL5_FIFO_CFG0_AUTO_FLUSH_ENABLE 0x01
409 #define ACCEL5_FIFO_AUTO_IP_TIMEOUT_0 0x00
410 #define ACCEL5_FIFO_AUTO_IP_TIMEOUT_1 0x04
411 #define ACCEL5_FIFO_AUTO_IP_TIMEOUT_2 0x08
412 #define ACCEL5_FIFO_AUTO_IP_TIMEOUT_3 0x0C
413 #define ACCEL5_FIFO_AUTO_TRIG_GEN1_INT 0x02
414 #define ACCEL5_FIFO_AUTO_TRIG_DATA_RDY 0x01
421 #define ACCEL5_WAKEUP_TIMEOUT_ENABLE 0x04
422 #define ACCEL5_WAKEUP_ENABLE 0x02
429 #define ACCEL5_WAKEUP_Z_AXIS_ENABLE 0x80
430 #define ACCEL5_WAKEUP_Y_AXIS_ENABLE 0x40
431 #define ACCEL5_WAKEUP_X_AXIS_ENABLE 0x20
432 #define ACCEL5_WAKEUP_NUMBER_OF_SIMPLE 0x10
433 #define ACCEL5_WAKEUP_REFU_MANUAL 0x00
434 #define ACCEL5_WAKEUP_REFU_ONETIME 0x01
435 #define ACCEL5_WAKEUP_REFU_EVERYTIME 0x02
442 #define ACCEL5_ORIENT_Z_AXIS_ENABLE 0x80
443 #define ACCEL5_ORIENT_Y_AXIS_ENABLE 0x40
444 #define ACCEL5_ORIENT_X_AXIS_ENABLE 0x20
445 #define ACCEL5_ORIENT_DATA_SRC_ENABLE 0x10
446 #define ACCEL5_ORIENT_REFU_MANUAL 0x00
447 #define ACCEL5_ORIENT_REFU_ONETIME_2 0x04
448 #define ACCEL5_ORIENT_REFU_ONETIME_IP 0x08
449 #define ACCEL5_ORIENT_STABILITY_INACTIVE 0x00
450 #define ACCEL5_ORIENT_STABILITY_ENABLED_1 0x01
451 #define ACCEL5_ORIENT_STABILITY_ENABLED_2 0x02
458 #define ACCEL5_GEN1_CFG0_ACT_Z_ENABLE 0x80
459 #define ACCEL5_GEN1_CFG0_ACT_Y_ENABLE 0x40
460 #define ACCEL5_GEN1_CFG0_ACT_X_ENABLE 0x20
461 #define ACCEL5_GEN1_CFG0_DATA_ENABLE 0x10
462 #define ACCEL5_GEN1_CFG0_REFU_MANUAL 0x00
463 #define ACCEL5_GEN1_CFG0_REFU_ONETIME 0x04
464 #define ACCEL5_GEN1_CFG0_REFU_EVERYTIME 0x08
465 #define ACCEL5_GEN1_CFG0_HYST_24mg 0x01
466 #define ACCEL5_GEN1_CFG0_HYST_48mg 0x02
467 #define ACCEL5_GEN1_CFG0_HYST_96mg 0x03
468 #define ACCEL5_GEN1_CFG0_HYST_NO_ACTIVE 0x00
475 #define ACCEL5_GEN1_CFG1_CRITERION_SEL_ACTIVE 0x20
476 #define ACCEL5_GEN1_CFG1_CRITERION_SEL_INACTIVE 0x00
477 #define ACCEL5_GEN1_CFG1_COMB_SEL_AND 0x10
478 #define ACCEL5_GEN1_CFG1_COMB_SEL_OR 0x00
485 #define ACCEL5_GEN2_CFG0_ACT_Z_ENABLE 0x80
486 #define ACCEL5_GEN2_CFG0_ACT_Y_ENABLE 0x40
487 #define ACCEL5_GEN2_CFG0_ACT_X_ENABLE 0x20
488 #define ACCEL5_GEN2_CFG0_DATA_ENABLE 0x10
489 #define ACCEL5_GEN2_CFG0_REFU_MANUAL 0x00
490 #define ACCEL5_GEN2_CFG0_REFU_ONETIME 0x04
491 #define ACCEL5_GEN2_CFG0_REFU_EVERYTIME 0x08
492 #define ACCEL5_GEN2_CFG0_HYST_24mg 0x01
493 #define ACCEL5_GEN2_CFG0_HYST_48mg 0x02
494 #define ACCEL5_GEN2_CFG0_HYST_96mg 0x03
495 #define ACCEL5_GEN2_CFG0_HYST_NO_ACTIVE 0x00
502 #define ACCEL5_GEN2_CFG1_CRITERION_SEL_ACTIVE 0x20
503 #define ACCEL5_GEN2_CFG1_CRITERION_SEL_INACTIVE 0x00
504 #define ACCEL5_GEN2_CFG1_COMB_SEL_AND 0x10
505 #define ACCEL5_GEN2_CFG1_COMB_SEL_OR 0x00
512 #define ACCEL5_ACTCH_CFG0_Z_AXIS_ENABLE 0x80
513 #define ACCEL5_ACTCH_CFG0_Y_AXIS_ENABLE 0x40
514 #define ACCEL5_ACTCH_CFG0_X_AXIS_ENABLE 0x20
515 #define ACCEL5_ACTCH_CFG0_DATA_ENABLE 0x10
516 #define ACCEL5_ACTCH_CFG0_NPTS_POINT_32 0x00
517 #define ACCEL5_ACTCH_CFG0_NPTS_POINT_64 0x01
518 #define ACCEL5_ACTCH_CFG0_NPTS_POINT_128 0x02
519 #define ACCEL5_ACTCH_CFG0_NPTS_POINT_256 0x03
520 #define ACCEL5_ACTCH_CFG0_NPTS_POINT_512 0x04
527 #define ACCEL5_TAP_CFG0_USE_Z_AXIS 0x00
528 #define ACCEL5_TAP_CFG0_USE_Y_AXIS 0x01
529 #define ACCEL5_TAP_CFG0_USE_X_AXIS 0x02
530 #define ACCEL5_TAP_CFG0_TAP_SEL_HIGH 0x00
531 #define ACCEL5_TAP_CFG0_TAP_SEL_LOW 0x10
538 #define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_4 0x00
539 #define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_8 0x10
540 #define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_12 0x20
541 #define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_16 0x30
542 #define ACCEL5_TAP_CFG1_QUIET_SAMPLE_60 0x00
543 #define ACCEL5_TAP_CFG1_QUIET_SAMPLE_80 0x04
544 #define ACCEL5_TAP_CFG1_QUIET_SAMPLE_100 0x08
545 #define ACCEL5_TAP_CFG1_QUIET_SAMPLE_120 0x0C
546 #define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_6 0x00
547 #define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_9 0x01
548 #define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_12 0x02
549 #define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_18 0x03
556 #define ACCEL5_IF_CONFIG_SPI_4_WIRE 0x00
557 #define ACCEL5_IF_CONFIG_SPI_3_WIRE 0x01
564 #define ACCEL5_TEST_SIGN_ENABLE 0x08
565 #define ACCEL5_TEST_Z_AXIS_ENABLE 0x04
566 #define ACCEL5_TEST_Y_AXIS_ENABLE 0x02
567 #define ACCEL5_TEST_X_AXIS_ENABLE 0x01
574 #define ACCEL5_CMD_FIFO_FLUSH 0xB0
575 #define ACCEL5_CMD_STEP_CNT_CLEAR 0xB1
576 #define ACCEL5_CMD_SOFTWARE_RESET 0xB6
583 #define ACCEL5_X_AXIS 0x04
584 #define ACCEL5_Y_AXIS 0x06
585 #define ACCEL5_Z_AXIS 0x08
592 #define DEVICE_ERROR 0x01
593 #define DEVICE_OK 0x00
pin_name_t it1
Definition: accel5.h:637
uint32_t accel5_sensor_time(accel5_t *ctx)
Functions for initialize the chip.
uint16_t accel5_read_data(accel5_t *ctx, uint8_t reg)
Functions for read data from register.
Click configuration structure definition.
Definition: accel5.h:628
err_t accel5_generic_write(accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
void accel5_default_cfg(accel5_t *ctx, uint8_t mode, uint8_t range)
Click Default Configuration function..
err_t accel5_init(accel5_t *ctx, accel5_cfg_t *cfg)
Initialization function.
pin_name_t it2
Definition: accel5.h:636
uint8_t i2c_address
Definition: accel5.h:642
void accel5_soft_reset(accel5_t *ctx)
Functions for software reset.
err_t accel5_generic_read(accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
void accel5_write_byte(accel5_t *ctx, uint8_t reg, uint8_t reg_data)
Functions for write one byte in register.
float accel5_get_temperature(accel5_t *ctx)
Functions for read temperature.
void accel5_cfg_setup(accel5_cfg_t *cfg)
Config Object Initialization function.
uint8_t slave_address
Definition: accel5.h:620
digital_in_t it2
Definition: accel5.h:611
pin_name_t scl
Definition: accel5.h:631
pin_name_t sda
Definition: accel5.h:632
digital_in_t it1
Definition: accel5.h:612
int16_t accel5_get_axis(accel5_t *ctx, uint8_t axis)
Functions for read axis data.
Click ctx object definition.
Definition: accel5.h:607
i2c_master_t i2c
Definition: accel5.h:616
uint32_t i2c_speed
Definition: accel5.h:641
uint8_t accel5_read_byte(accel5_t *ctx, uint8_t reg)
Functions for read byte from register.