Static Timing Analysis

Project : keypad_4x4
Build Time : 11/08/20 16:34:00
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_0 Pin_DB4(0)_PAD 23.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\ \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/busclk \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_11 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_0 Pin_DB4(0)/pin_input 6.151
iocell3 P3[4] 1 Pin_DB4(0) Pin_DB4(0)/pin_input Pin_DB4(0)/pad_out 14.987
Route 1 Pin_DB4(0)_PAD Pin_DB4(0)/pad_out Pin_DB4(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_2 Pin_DB6(0)_PAD 22.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\ \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/busclk \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_13 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_2 Pin_DB6(0)/pin_input 6.190
iocell5 P3[6] 1 Pin_DB6(0) Pin_DB6(0)/pin_input Pin_DB6(0)/pad_out 14.591
Route 1 Pin_DB6(0)_PAD Pin_DB6(0)/pad_out Pin_DB6(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_1 Pin_DB5(0)_PAD 22.692
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\ \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/busclk \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_12 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_1 Pin_DB5(0)/pin_input 5.304
iocell4 P3[5] 1 Pin_DB5(0) Pin_DB5(0)/pin_input Pin_DB5(0)/pad_out 15.338
Route 1 Pin_DB5(0)_PAD Pin_DB5(0)/pad_out Pin_DB5(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_3 Pin_DB7(0)_PAD 22.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\ \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/busclk \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_14 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_3 Pin_DB7(0)/pin_input 5.268
iocell6 P3[7] 1 Pin_DB7(0) Pin_DB7(0)/pin_input Pin_DB7(0)/pad_out 15.161
Route 1 Pin_DB7(0)_PAD Pin_DB7(0)/pad_out Pin_DB7(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_5 Pin_RS(0)_PAD 22.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\ \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/busclk \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_15 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_5 Pin_RS(0)/pin_input 5.307
iocell2 P3[1] 1 Pin_RS(0) Pin_RS(0)/pin_input Pin_RS(0)/pad_out 14.979
Route 1 Pin_RS(0)_PAD Pin_RS(0)/pad_out Pin_RS(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_4 Pin_EN(0)_PAD 21.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\ \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/busclk \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_10 \LCD_2x16:Cntl_Port:Sync:ctrl_reg\/control_4 Pin_EN(0)/pin_input 5.324
iocell1 P3[3] 1 Pin_EN(0) Pin_EN(0)/pin_input Pin_EN(0)/pad_out 14.591
Route 1 Pin_EN(0)_PAD Pin_EN(0)/pad_out Pin_EN(0)_PAD 0.000
Clock Clock path delay 0.000