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35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_i2c_master.h"
59 #define I2CMUX5_REGISTER_0 0x00
60 #define I2CMUX5_REGISTER_1 0x01
61 #define I2CMUX5_REGISTER_2 0x02
62 #define I2CMUX5_REGISTER_3 0x03
85 #define I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED 0x00
86 #define I2CMUX5_SET_REG_0_US_BUS_CONNECTED 0x80
87 #define I2CMUX5_SET_REG_0_ALERT1_STATE_LOW 0x00
88 #define I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH 0x40
89 #define I2CMUX5_SET_REG_0_ALERT2_STATE_LOW 0x00
90 #define I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH 0x20
91 #define I2CMUX5_SET_REG_0_ALERT3_STATE_LOW 0x00
92 #define I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH 0x10
93 #define I2CMUX5_SET_REG_0_ALERT4_STATE_LOW 0x00
94 #define I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH 0x08
95 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED 0x00
96 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK 0x04
97 #define I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT 0x00
98 #define I2CMUX5_SET_REG_0_LATCHED_TIMEOUT 0x02
99 #define I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING 0x00
100 #define I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING 0x01
107 #define I2CMUX5_SET_REG_1_URTAC_INACTIVE 0x00
108 #define I2CMUX5_SET_REG_1_URTAC_ACTIVE 0x80
109 #define I2CMUX5_SET_REG_1_DRTAC_INACTIVE 0x00
110 #define I2CMUX5_SET_REG_1_DRTAC_ACTIVE 0x40
111 #define I2CMUX5_SET_REG_1_GPIO_1_LOW 0x00
112 #define I2CMUX5_SET_REG_1_GPIO_1_HIGH 0x20
113 #define I2CMUX5_SET_REG_1_GPIO_2_LOW 0x00
114 #define I2CMUX5_SET_REG_1_GPIO_2_HIGH 0x10
120 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT 0x00
121 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT 0x80
122 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT 0x00
123 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT 0x40
124 #define I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS 0x00
125 #define I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE 0x20
126 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN 0x00
127 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL 0x10
128 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN 0x00
129 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL 0x08
130 #define I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE 0x00
131 #define I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE 0x04
132 #define I2CMUX5_SET_REG_2_TIMEOUT_DISABLED 0x00
133 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS 0x01
134 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS 0x02
135 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS 0x03
141 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN 0x00
142 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED 0x80
143 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN 0x00
144 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED 0x40
145 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN 0x00
146 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED 0x20
147 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN 0x00
148 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED 0x10
154 #define I2CMUX5_CH_SEL_ERROR 0xFF
161 #define I2CMUX5_SET_DEV_ADDR 0x44
168 #define I2CMUX5_SET_6DOF_IMU_9_ADDR 0x69
169 #define I2CMUX5_SET_6DOF_IMU_11_ADDR 0x0E
170 #define I2CMUX5_SET_RTC_10_ADDR 0x68
171 #define I2CMUX5_SET_ACCEL_10_ADDR 0x18
190 #define I2CMUX5_CH_1 0x01
191 #define I2CMUX5_CH_2 0x02
192 #define I2CMUX5_CH_3 0x03
193 #define I2CMUX5_CH_4 0x04
207 #define I2CMUX5_PIN_STATE_LOW 0
208 #define I2CMUX5_PIN_STATE_HIGH 1
222 #define I2CMUX5_MAP_MIKROBUS( cfg, mikrobus ) \
223 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
224 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
225 cfg.en = MIKROBUS( mikrobus, MIKROBUS_CS ); \
226 cfg.ready = MIKROBUS( mikrobus, MIKROBUS_AN ); \
227 cfg.alert = MIKROBUS( mikrobus, MIKROBUS_INT )
253 uint8_t slave_address;
err_t i2cmux5_generic_write(i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len)
I2C MUX 5 I2C writing function.
void i2cmux5_hw_reset(i2cmux5_t *ctx)
I2C MUX 5 HW reset function.
uint8_t i2cmux5_channel_read_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg)
I2C MUX 5 I2C channel reading function.
err_t i2cmux5_generic_read(i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len)
I2C MUX 5 I2C reading function.
uint8_t i2cmux5_check_alert(i2cmux5_t *ctx)
I2C MUX 5 check alert function.
uint8_t i2cmux5_check_ch_alert(i2cmux5_t *ctx, uint8_t n_channel)
I2C MUX 5 check channel alert function.
void i2cmux5_cfg_setup(i2cmux5_cfg_t *cfg)
I2C MUX 5 configuration object setup function.
uint8_t i2cmux5_check_rdy(i2cmux5_t *ctx)
I2C MUX 5 check rdy function.
void i2cmux5_dev_enable(i2cmux5_t *ctx)
I2C MUX 5 enable the device function.
I2C MUX 5 Click context object.
Definition: i2cmux5.h:235
void i2cmux5_default_cfg(i2cmux5_t *ctx)
I2C MUX 5 default configuration function.
I2C MUX 5 Click configuration object.
Definition: i2cmux5.h:260
err_t i2cmux5_init(i2cmux5_t *ctx, i2cmux5_cfg_t *cfg)
I2C MUX 5 initialization function.
void i2cmux5_channel_write_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data)
I2C MUX 5 I2C channel writing function.