i2cmux5  2.0.0.0
i2cmux5.h
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22 
28 #ifndef I2CMUX5_H
29 #define I2CMUX5_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_i2c_master.h"
38 
59 #define I2CMUX5_REGISTER_0 0x00
60 #define I2CMUX5_REGISTER_1 0x01
61 #define I2CMUX5_REGISTER_2 0x02
62 #define I2CMUX5_REGISTER_3 0x03
63  // i2cmux5_reg
65 
85 #define I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED 0x00
86 #define I2CMUX5_SET_REG_0_US_BUS_CONNECTED 0x80
87 #define I2CMUX5_SET_REG_0_ALERT1_STATE_LOW 0x00
88 #define I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH 0x40
89 #define I2CMUX5_SET_REG_0_ALERT2_STATE_LOW 0x00
90 #define I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH 0x20
91 #define I2CMUX5_SET_REG_0_ALERT3_STATE_LOW 0x00
92 #define I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH 0x10
93 #define I2CMUX5_SET_REG_0_ALERT4_STATE_LOW 0x00
94 #define I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH 0x08
95 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED 0x00
96 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK 0x04
97 #define I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT 0x00
98 #define I2CMUX5_SET_REG_0_LATCHED_TIMEOUT 0x02
99 #define I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING 0x00
100 #define I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING 0x01
101 
102 
107 #define I2CMUX5_SET_REG_1_URTAC_INACTIVE 0x00
108 #define I2CMUX5_SET_REG_1_URTAC_ACTIVE 0x80
109 #define I2CMUX5_SET_REG_1_DRTAC_INACTIVE 0x00
110 #define I2CMUX5_SET_REG_1_DRTAC_ACTIVE 0x40
111 #define I2CMUX5_SET_REG_1_GPIO_1_LOW 0x00
112 #define I2CMUX5_SET_REG_1_GPIO_1_HIGH 0x20
113 #define I2CMUX5_SET_REG_1_GPIO_2_LOW 0x00
114 #define I2CMUX5_SET_REG_1_GPIO_2_HIGH 0x10
115 
120 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT 0x00
121 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT 0x80
122 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT 0x00
123 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT 0x40
124 #define I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS 0x00
125 #define I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE 0x20
126 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN 0x00
127 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL 0x10
128 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN 0x00
129 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL 0x08
130 #define I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE 0x00
131 #define I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE 0x04
132 #define I2CMUX5_SET_REG_2_TIMEOUT_DISABLED 0x00
133 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS 0x01
134 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS 0x02
135 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS 0x03
136 
141 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN 0x00
142 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED 0x80
143 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN 0x00
144 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED 0x40
145 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN 0x00
146 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED 0x20
147 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN 0x00
148 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED 0x10
149 
154 #define I2CMUX5_CH_SEL_ERROR 0xFF
155 
161 #define I2CMUX5_SET_DEV_ADDR 0x44
162 
168 #define I2CMUX5_SET_6DOF_IMU_9_ADDR 0x69
169 #define I2CMUX5_SET_6DOF_IMU_11_ADDR 0x0E
170 #define I2CMUX5_SET_RTC_10_ADDR 0x68
171 #define I2CMUX5_SET_ACCEL_10_ADDR 0x18
172  // i2cmux5_set
174 
190 #define I2CMUX5_CH_1 0x01
191 #define I2CMUX5_CH_2 0x02
192 #define I2CMUX5_CH_3 0x03
193 #define I2CMUX5_CH_4 0x04
194  // sel_ch
196 
207 #define I2CMUX5_PIN_STATE_LOW 0
208 #define I2CMUX5_PIN_STATE_HIGH 1
209 
210  // pin_state
212 
222 #define I2CMUX5_MAP_MIKROBUS( cfg, mikrobus ) \
223  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
224  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
225  cfg.en = MIKROBUS( mikrobus, MIKROBUS_CS ); \
226  cfg.ready = MIKROBUS( mikrobus, MIKROBUS_AN ); \
227  cfg.alert = MIKROBUS( mikrobus, MIKROBUS_INT )
228  // i2cmux5_map // i2cmux5
231 
236 typedef struct
237 {
238  // Output pins
239 
240  digital_out_t en;
242  // Input pins
243 
244  digital_in_t ready;
245  digital_in_t alert;
247  // Modules
248 
249  i2c_master_t i2c;
251  // I2C slave address
252 
253  uint8_t slave_address;
255 } i2cmux5_t;
256 
261 typedef struct
262 {
263  pin_name_t scl;
264  pin_name_t sda;
266  pin_name_t en;
267  pin_name_t ready;
268  pin_name_t alert;
270  uint32_t i2c_speed;
271  uint8_t i2c_address;
273 } i2cmux5_cfg_t;
274 
293 
310 err_t i2cmux5_init ( i2cmux5_t *ctx, i2cmux5_cfg_t *cfg );
311 
328 
339 
351 
363 uint8_t i2cmux5_check_rdy ( i2cmux5_t *ctx );
364 
377 
395 err_t i2cmux5_generic_write ( i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
396 
414 err_t i2cmux5_generic_read ( i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
415 
433 uint8_t i2cmux5_check_ch_alert ( i2cmux5_t *ctx, uint8_t n_channel );
434 
451 void i2cmux5_channel_write_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data );
452 
469 uint8_t i2cmux5_channel_read_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg );
470 
471 #ifdef __cplusplus
472 }
473 #endif
474 #endif // I2CMUX5_H
475  // i2cmux5
477 
478 // ------------------------------------------------------------------------ END
i2cmux5_generic_write
err_t i2cmux5_generic_write(i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len)
I2C MUX 5 I2C writing function.
i2cmux5_t::en
digital_out_t en
Definition: i2cmux5.h:240
i2cmux5_cfg_t::alert
pin_name_t alert
Definition: i2cmux5.h:268
i2cmux5_cfg_t::ready
pin_name_t ready
Definition: i2cmux5.h:267
i2cmux5_hw_reset
void i2cmux5_hw_reset(i2cmux5_t *ctx)
I2C MUX 5 HW reset function.
i2cmux5_channel_read_byte
uint8_t i2cmux5_channel_read_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg)
I2C MUX 5 I2C channel reading function.
i2cmux5_generic_read
err_t i2cmux5_generic_read(i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len)
I2C MUX 5 I2C reading function.
i2cmux5_cfg_t::scl
pin_name_t scl
Definition: i2cmux5.h:263
i2cmux5_check_alert
uint8_t i2cmux5_check_alert(i2cmux5_t *ctx)
I2C MUX 5 check alert function.
i2cmux5_check_ch_alert
uint8_t i2cmux5_check_ch_alert(i2cmux5_t *ctx, uint8_t n_channel)
I2C MUX 5 check channel alert function.
i2cmux5_cfg_t::i2c_address
uint8_t i2c_address
Definition: i2cmux5.h:271
i2cmux5_t::ready
digital_in_t ready
Definition: i2cmux5.h:244
i2cmux5_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: i2cmux5.h:270
i2cmux5_cfg_t::sda
pin_name_t sda
Definition: i2cmux5.h:264
i2cmux5_t::i2c
i2c_master_t i2c
Definition: i2cmux5.h:249
i2cmux5_cfg_setup
void i2cmux5_cfg_setup(i2cmux5_cfg_t *cfg)
I2C MUX 5 configuration object setup function.
i2cmux5_t::alert
digital_in_t alert
Definition: i2cmux5.h:245
i2cmux5_check_rdy
uint8_t i2cmux5_check_rdy(i2cmux5_t *ctx)
I2C MUX 5 check rdy function.
i2cmux5_cfg_t::en
pin_name_t en
Definition: i2cmux5.h:266
i2cmux5_dev_enable
void i2cmux5_dev_enable(i2cmux5_t *ctx)
I2C MUX 5 enable the device function.
i2cmux5_t
I2C MUX 5 Click context object.
Definition: i2cmux5.h:237
i2cmux5_default_cfg
void i2cmux5_default_cfg(i2cmux5_t *ctx)
I2C MUX 5 default configuration function.
i2cmux5_cfg_t
I2C MUX 5 Click configuration object.
Definition: i2cmux5.h:262
i2cmux5_init
err_t i2cmux5_init(i2cmux5_t *ctx, i2cmux5_cfg_t *cfg)
I2C MUX 5 initialization function.
i2cmux5_t::slave_address
uint8_t slave_address
Definition: i2cmux5.h:253
i2cmux5_channel_write_byte
void i2cmux5_channel_write_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data)
I2C MUX 5 I2C channel writing function.