i2cmux5  2.0.0.0
i2cmux5.h
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22 
28 #ifndef I2CMUX5_H
29 #define I2CMUX5_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "mikrosdk_version.h"
36 
37 #ifdef __GNUC__
38 #if mikroSDK_GET_VERSION < 20800ul
39 #include "rcu_delays.h"
40 #else
41 #include "delays.h"
42 #endif
43 #endif
44 
45 #include "drv_digital_out.h"
46 #include "drv_digital_in.h"
47 #include "drv_i2c_master.h"
48 
69 #define I2CMUX5_REGISTER_0 0x00
70 #define I2CMUX5_REGISTER_1 0x01
71 #define I2CMUX5_REGISTER_2 0x02
72 #define I2CMUX5_REGISTER_3 0x03
73  // i2cmux5_reg
75 
95 #define I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED 0x00
96 #define I2CMUX5_SET_REG_0_US_BUS_CONNECTED 0x80
97 #define I2CMUX5_SET_REG_0_ALERT1_STATE_LOW 0x00
98 #define I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH 0x40
99 #define I2CMUX5_SET_REG_0_ALERT2_STATE_LOW 0x00
100 #define I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH 0x20
101 #define I2CMUX5_SET_REG_0_ALERT3_STATE_LOW 0x00
102 #define I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH 0x10
103 #define I2CMUX5_SET_REG_0_ALERT4_STATE_LOW 0x00
104 #define I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH 0x08
105 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED 0x00
106 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK 0x04
107 #define I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT 0x00
108 #define I2CMUX5_SET_REG_0_LATCHED_TIMEOUT 0x02
109 #define I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING 0x00
110 #define I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING 0x01
111 
112 
117 #define I2CMUX5_SET_REG_1_URTAC_INACTIVE 0x00
118 #define I2CMUX5_SET_REG_1_URTAC_ACTIVE 0x80
119 #define I2CMUX5_SET_REG_1_DRTAC_INACTIVE 0x00
120 #define I2CMUX5_SET_REG_1_DRTAC_ACTIVE 0x40
121 #define I2CMUX5_SET_REG_1_GPIO_1_LOW 0x00
122 #define I2CMUX5_SET_REG_1_GPIO_1_HIGH 0x20
123 #define I2CMUX5_SET_REG_1_GPIO_2_LOW 0x00
124 #define I2CMUX5_SET_REG_1_GPIO_2_HIGH 0x10
125 
130 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT 0x00
131 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT 0x80
132 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT 0x00
133 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT 0x40
134 #define I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS 0x00
135 #define I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE 0x20
136 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN 0x00
137 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL 0x10
138 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN 0x00
139 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL 0x08
140 #define I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE 0x00
141 #define I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE 0x04
142 #define I2CMUX5_SET_REG_2_TIMEOUT_DISABLED 0x00
143 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS 0x01
144 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS 0x02
145 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS 0x03
146 
151 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN 0x00
152 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED 0x80
153 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN 0x00
154 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED 0x40
155 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN 0x00
156 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED 0x20
157 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN 0x00
158 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED 0x10
159 
164 #define I2CMUX5_CH_SEL_ERROR 0xFF
165 
171 #define I2CMUX5_SET_DEV_ADDR 0x44
172 
178 #define I2CMUX5_SET_6DOF_IMU_9_ADDR 0x69
179 #define I2CMUX5_SET_6DOF_IMU_11_ADDR 0x0E
180 #define I2CMUX5_SET_RTC_10_ADDR 0x68
181 #define I2CMUX5_SET_ACCEL_10_ADDR 0x18
182  // i2cmux5_set
184 
200 #define I2CMUX5_CH_1 0x01
201 #define I2CMUX5_CH_2 0x02
202 #define I2CMUX5_CH_3 0x03
203 #define I2CMUX5_CH_4 0x04
204  // sel_ch
206 
217 #define I2CMUX5_PIN_STATE_LOW 0
218 #define I2CMUX5_PIN_STATE_HIGH 1
219 
220  // pin_state
222 
232 #define I2CMUX5_MAP_MIKROBUS( cfg, mikrobus ) \
233  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
234  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
235  cfg.en = MIKROBUS( mikrobus, MIKROBUS_CS ); \
236  cfg.ready = MIKROBUS( mikrobus, MIKROBUS_AN ); \
237  cfg.alert = MIKROBUS( mikrobus, MIKROBUS_INT )
238  // i2cmux5_map // i2cmux5
241 
246 typedef struct
247 {
248  // Output pins
249 
250  digital_out_t en;
252  // Input pins
253 
254  digital_in_t ready;
255  digital_in_t alert;
257  // Modules
258 
259  i2c_master_t i2c;
261  // I2C slave address
262 
263  uint8_t slave_address;
265 } i2cmux5_t;
266 
271 typedef struct
272 {
273  pin_name_t scl;
274  pin_name_t sda;
276  pin_name_t en;
277  pin_name_t ready;
278  pin_name_t alert;
280  uint32_t i2c_speed;
281  uint8_t i2c_address;
283 } i2cmux5_cfg_t;
284 
303 
320 err_t i2cmux5_init ( i2cmux5_t *ctx, i2cmux5_cfg_t *cfg );
321 
338 
349 
361 
373 uint8_t i2cmux5_check_rdy ( i2cmux5_t *ctx );
374 
387 
405 err_t i2cmux5_generic_write ( i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
406 
424 err_t i2cmux5_generic_read ( i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
425 
443 uint8_t i2cmux5_check_ch_alert ( i2cmux5_t *ctx, uint8_t n_channel );
444 
461 void i2cmux5_channel_write_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data );
462 
479 uint8_t i2cmux5_channel_read_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg );
480 
481 #ifdef __cplusplus
482 }
483 #endif
484 #endif // I2CMUX5_H
485  // i2cmux5
487 
488 // ------------------------------------------------------------------------ END
i2cmux5_generic_write
err_t i2cmux5_generic_write(i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len)
I2C MUX 5 I2C writing function.
i2cmux5_t::en
digital_out_t en
Definition: i2cmux5.h:250
i2cmux5_cfg_t::alert
pin_name_t alert
Definition: i2cmux5.h:278
i2cmux5_cfg_t::ready
pin_name_t ready
Definition: i2cmux5.h:277
i2cmux5_hw_reset
void i2cmux5_hw_reset(i2cmux5_t *ctx)
I2C MUX 5 HW reset function.
i2cmux5_channel_read_byte
uint8_t i2cmux5_channel_read_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg)
I2C MUX 5 I2C channel reading function.
i2cmux5_generic_read
err_t i2cmux5_generic_read(i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len)
I2C MUX 5 I2C reading function.
i2cmux5_cfg_t::scl
pin_name_t scl
Definition: i2cmux5.h:273
i2cmux5_check_alert
uint8_t i2cmux5_check_alert(i2cmux5_t *ctx)
I2C MUX 5 check alert function.
i2cmux5_check_ch_alert
uint8_t i2cmux5_check_ch_alert(i2cmux5_t *ctx, uint8_t n_channel)
I2C MUX 5 check channel alert function.
i2cmux5_cfg_t::i2c_address
uint8_t i2c_address
Definition: i2cmux5.h:281
i2cmux5_t::ready
digital_in_t ready
Definition: i2cmux5.h:254
i2cmux5_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: i2cmux5.h:280
i2cmux5_cfg_t::sda
pin_name_t sda
Definition: i2cmux5.h:274
i2cmux5_t::i2c
i2c_master_t i2c
Definition: i2cmux5.h:259
i2cmux5_cfg_setup
void i2cmux5_cfg_setup(i2cmux5_cfg_t *cfg)
I2C MUX 5 configuration object setup function.
i2cmux5_t::alert
digital_in_t alert
Definition: i2cmux5.h:255
i2cmux5_check_rdy
uint8_t i2cmux5_check_rdy(i2cmux5_t *ctx)
I2C MUX 5 check rdy function.
i2cmux5_cfg_t::en
pin_name_t en
Definition: i2cmux5.h:276
i2cmux5_dev_enable
void i2cmux5_dev_enable(i2cmux5_t *ctx)
I2C MUX 5 enable the device function.
i2cmux5_t
I2C MUX 5 Click context object.
Definition: i2cmux5.h:247
i2cmux5_default_cfg
void i2cmux5_default_cfg(i2cmux5_t *ctx)
I2C MUX 5 default configuration function.
i2cmux5_cfg_t
I2C MUX 5 Click configuration object.
Definition: i2cmux5.h:272
i2cmux5_init
err_t i2cmux5_init(i2cmux5_t *ctx, i2cmux5_cfg_t *cfg)
I2C MUX 5 initialization function.
i2cmux5_t::slave_address
uint8_t slave_address
Definition: i2cmux5.h:263
i2cmux5_channel_write_byte
void i2cmux5_channel_write_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data)
I2C MUX 5 I2C channel writing function.