i2cmux5  2.0.0.0
i2cmux5.h
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22 
28 #ifndef I2CMUX5_H
29 #define I2CMUX5_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
39 #ifdef PREINIT_SUPPORTED
40 #include "preinit.h"
41 #endif
42 
43 #ifdef MikroCCoreVersion
44  #if MikroCCoreVersion >= 1
45  #include "delays.h"
46  #endif
47 #endif
48 
49 #include "drv_digital_out.h"
50 #include "drv_digital_in.h"
51 #include "drv_i2c_master.h"
52 
73 #define I2CMUX5_REGISTER_0 0x00
74 #define I2CMUX5_REGISTER_1 0x01
75 #define I2CMUX5_REGISTER_2 0x02
76 #define I2CMUX5_REGISTER_3 0x03
77  // i2cmux5_reg
79 
99 #define I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED 0x00
100 #define I2CMUX5_SET_REG_0_US_BUS_CONNECTED 0x80
101 #define I2CMUX5_SET_REG_0_ALERT1_STATE_LOW 0x00
102 #define I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH 0x40
103 #define I2CMUX5_SET_REG_0_ALERT2_STATE_LOW 0x00
104 #define I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH 0x20
105 #define I2CMUX5_SET_REG_0_ALERT3_STATE_LOW 0x00
106 #define I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH 0x10
107 #define I2CMUX5_SET_REG_0_ALERT4_STATE_LOW 0x00
108 #define I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH 0x08
109 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED 0x00
110 #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK 0x04
111 #define I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT 0x00
112 #define I2CMUX5_SET_REG_0_LATCHED_TIMEOUT 0x02
113 #define I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING 0x00
114 #define I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING 0x01
115 
116 
121 #define I2CMUX5_SET_REG_1_URTAC_INACTIVE 0x00
122 #define I2CMUX5_SET_REG_1_URTAC_ACTIVE 0x80
123 #define I2CMUX5_SET_REG_1_DRTAC_INACTIVE 0x00
124 #define I2CMUX5_SET_REG_1_DRTAC_ACTIVE 0x40
125 #define I2CMUX5_SET_REG_1_GPIO_1_LOW 0x00
126 #define I2CMUX5_SET_REG_1_GPIO_1_HIGH 0x20
127 #define I2CMUX5_SET_REG_1_GPIO_2_LOW 0x00
128 #define I2CMUX5_SET_REG_1_GPIO_2_HIGH 0x10
129 
134 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT 0x00
135 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT 0x80
136 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT 0x00
137 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT 0x40
138 #define I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS 0x00
139 #define I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE 0x20
140 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN 0x00
141 #define I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL 0x10
142 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN 0x00
143 #define I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL 0x08
144 #define I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE 0x00
145 #define I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE 0x04
146 #define I2CMUX5_SET_REG_2_TIMEOUT_DISABLED 0x00
147 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS 0x01
148 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS 0x02
149 #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS 0x03
150 
155 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN 0x00
156 #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED 0x80
157 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN 0x00
158 #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED 0x40
159 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN 0x00
160 #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED 0x20
161 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN 0x00
162 #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED 0x10
163 
168 #define I2CMUX5_CH_SEL_ERROR 0xFF
169 
175 #define I2CMUX5_SET_DEV_ADDR 0x44
176 
182 #define I2CMUX5_SET_6DOF_IMU_9_ADDR 0x69
183 #define I2CMUX5_SET_6DOF_IMU_11_ADDR 0x0E
184 #define I2CMUX5_SET_RTC_10_ADDR 0x68
185 #define I2CMUX5_SET_ACCEL_10_ADDR 0x18
186  // i2cmux5_set
188 
204 #define I2CMUX5_CH_1 0x01
205 #define I2CMUX5_CH_2 0x02
206 #define I2CMUX5_CH_3 0x03
207 #define I2CMUX5_CH_4 0x04
208  // sel_ch
210 
221 #define I2CMUX5_PIN_STATE_LOW 0
222 #define I2CMUX5_PIN_STATE_HIGH 1
223 
224  // pin_state
226 
236 #define I2CMUX5_MAP_MIKROBUS( cfg, mikrobus ) \
237  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
238  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
239  cfg.en = MIKROBUS( mikrobus, MIKROBUS_CS ); \
240  cfg.ready = MIKROBUS( mikrobus, MIKROBUS_AN ); \
241  cfg.alert = MIKROBUS( mikrobus, MIKROBUS_INT )
242  // i2cmux5_map // i2cmux5
245 
250 typedef struct
251 {
252  // Output pins
253 
254  digital_out_t en;
256  // Input pins
257 
258  digital_in_t ready;
259  digital_in_t alert;
261  // Modules
262 
263  i2c_master_t i2c;
265  // I2C slave address
266 
267  uint8_t slave_address;
269 } i2cmux5_t;
270 
275 typedef struct
276 {
277  pin_name_t scl;
278  pin_name_t sda;
280  pin_name_t en;
281  pin_name_t ready;
282  pin_name_t alert;
284  uint32_t i2c_speed;
285  uint8_t i2c_address;
287 } i2cmux5_cfg_t;
288 
307 
324 err_t i2cmux5_init ( i2cmux5_t *ctx, i2cmux5_cfg_t *cfg );
325 
342 
353 
365 
377 uint8_t i2cmux5_check_rdy ( i2cmux5_t *ctx );
378 
391 
409 err_t i2cmux5_generic_write ( i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
410 
428 err_t i2cmux5_generic_read ( i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
429 
447 uint8_t i2cmux5_check_ch_alert ( i2cmux5_t *ctx, uint8_t n_channel );
448 
465 void i2cmux5_channel_write_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data );
466 
483 uint8_t i2cmux5_channel_read_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg );
484 
485 #ifdef __cplusplus
486 }
487 #endif
488 #endif // I2CMUX5_H
489  // i2cmux5
491 
492 // ------------------------------------------------------------------------ END
i2cmux5_generic_write
err_t i2cmux5_generic_write(i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len)
I2C MUX 5 I2C writing function.
i2cmux5_t::en
digital_out_t en
Definition: i2cmux5.h:254
i2cmux5_cfg_t::alert
pin_name_t alert
Definition: i2cmux5.h:282
i2cmux5_cfg_t::ready
pin_name_t ready
Definition: i2cmux5.h:281
i2cmux5_hw_reset
void i2cmux5_hw_reset(i2cmux5_t *ctx)
I2C MUX 5 HW reset function.
i2cmux5_channel_read_byte
uint8_t i2cmux5_channel_read_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg)
I2C MUX 5 I2C channel reading function.
i2cmux5_generic_read
err_t i2cmux5_generic_read(i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len)
I2C MUX 5 I2C reading function.
i2cmux5_cfg_t::scl
pin_name_t scl
Definition: i2cmux5.h:277
i2cmux5_check_alert
uint8_t i2cmux5_check_alert(i2cmux5_t *ctx)
I2C MUX 5 check alert function.
i2cmux5_check_ch_alert
uint8_t i2cmux5_check_ch_alert(i2cmux5_t *ctx, uint8_t n_channel)
I2C MUX 5 check channel alert function.
i2cmux5_cfg_t::i2c_address
uint8_t i2c_address
Definition: i2cmux5.h:285
i2cmux5_t::ready
digital_in_t ready
Definition: i2cmux5.h:258
i2cmux5_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: i2cmux5.h:284
i2cmux5_cfg_t::sda
pin_name_t sda
Definition: i2cmux5.h:278
i2cmux5_t::i2c
i2c_master_t i2c
Definition: i2cmux5.h:263
i2cmux5_cfg_setup
void i2cmux5_cfg_setup(i2cmux5_cfg_t *cfg)
I2C MUX 5 configuration object setup function.
i2cmux5_t::alert
digital_in_t alert
Definition: i2cmux5.h:259
i2cmux5_check_rdy
uint8_t i2cmux5_check_rdy(i2cmux5_t *ctx)
I2C MUX 5 check rdy function.
i2cmux5_cfg_t::en
pin_name_t en
Definition: i2cmux5.h:280
i2cmux5_dev_enable
void i2cmux5_dev_enable(i2cmux5_t *ctx)
I2C MUX 5 enable the device function.
i2cmux5_t
I2C MUX 5 Click context object.
Definition: i2cmux5.h:251
i2cmux5_default_cfg
void i2cmux5_default_cfg(i2cmux5_t *ctx)
I2C MUX 5 default configuration function.
i2cmux5_cfg_t
I2C MUX 5 Click configuration object.
Definition: i2cmux5.h:276
i2cmux5_init
err_t i2cmux5_init(i2cmux5_t *ctx, i2cmux5_cfg_t *cfg)
I2C MUX 5 initialization function.
i2cmux5_t::slave_address
uint8_t slave_address
Definition: i2cmux5.h:267
i2cmux5_channel_write_byte
void i2cmux5_channel_write_byte(i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data)
I2C MUX 5 I2C channel writing function.