enocean2  2.0.0.0
enocean2.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN2_H
36 #define ENOCEAN2_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_uart.h"
41 
42 
43 // -------------------------------------------------------------- PUBLIC MACROS
53 #define ENOCEAN2_MAP_MIKROBUS( cfg, mikrobus ) \
54  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
55  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX )
56 
62 #define ENOCEAN2_RETVAL uint8_t
63 
64 #define ENOCEAN2_OK 0x00
65 #define ENOCEAN2_INIT_ERROR 0xFF
66 
72 #define ENOCEAN2_RX_BUFFER_SIZE 200
73 #define ENOCEAN2_SEQUENCE_NUMBER_OFFSET 2
74 #define ENOCEAN2_COMMAND_OFFSET 17
75 
81 #define ENOCEAN2_ERR_OK 0xE0
82 #define ENOCEAN2_ERR_BUFFER_FULL 0xE1
83 #define ENOCEAN2_ERR_CHAR_TIMEOUT 0xE2
84 #define ENOCEAN2_ERR_INVALID_SIZE 0xE3
85 #define ENOCEAN2_ERR_NO_MEMORY 0xE4
86 
92 #define ENOCEAN2_TYPE_RADIO_ERP1 0x01
93 #define ENOCEAN2_TYPE_RESPONSE 0x02
94 #define ENOCEAN2_TYPE_RADIO_SUB_TEL 0x03
95 #define ENOCEAN2_TYPE_EVENT 0x04
96 #define ENOCEAN2_TYPE_COMMON 0x05
97 #define ENOCEAN2_TYPE_SMART_ACK 0x06
98 #define ENOCEAN2_TYPE_REMOTE_MAN 0x07
99 #define ENOCEAN2_TYPE_RADIO_MESSAGE 0x09
100 #define ENOCEAN2_TYPE_RADIO_ERP2 0x0A
101 #define ENOCEAN2_TYPE_RADIO_802_15_4 0x10
102 #define ENOCEAN2_TYPE_COMMAND_2_4 0x11
103 
109 #define ENOCEAN2_EV_SA_RECLAIM_NOT_SUCCESSFUL 0x01
110 #define ENOCEAN2_EV_SA_CONFIRM_LEARN 0x02
111 #define ENOCEAN2_EV_SA_LEARN_ACK 0x03
112 #define ENOCEAN2_EV_CO_READY 0x04
113 #define ENOCEAN2_EV_CO_EVENT_SECUREDEVICES 0x05
114 #define ENOCEAN2_EV_CO_DUTYCYCLE_LIMIT 0x06
115 #define ENOCEAN2_EV_CO_TRANSMIT_FAILED 0x07
116 
122 #define ENOCEAN2_CO_WR_SLEEP 0x01
123 #define ENOCEAN2_CO_WR_RESET 0x02
124 #define ENOCEAN2_CO_RD_VERSION 0x03
125 #define ENOCEAN2_CO_RD_SYS_LOG 0x04
126 #define ENOCEAN2_CO_WR_SYS_LOG 0x05
127 #define ENOCEAN2_CO_WR_BIST 0x06
128 #define ENOCEAN2_CO_WR_IDBASE 0x07
129 #define ENOCEAN2_CO_RD_IDBASE 0x08
130 #define ENOCEAN2_CO_WR_REPEATER 0x09
131 #define ENOCEAN2_CO_RD_REPEATER 0x0A
132 #define ENOCEAN2_CO_WR_FILTER_ADD 0x0B
133 #define ENOCEAN2_CO_WR_FILTER_DEL 0x0C
134 #define ENOCEAN2_CO_WR_FILTER_DEL_ALL 0x0D
135 #define ENOCEAN2_CO_WR_FILTER_ENABLE 0x0E
136 #define ENOCEAN2_CO_RD_FILTER 0x0F
137 #define ENOCEAN2_CO_WR_WAIT_MATURITY 0x10
138 #define ENOCEAN2_CO_WR_SUBTEL 0x11
139 #define ENOCEAN2_CO_WR_MEM 0x12
140 #define ENOCEAN2_CO_RD_MEM 0x13
141 #define ENOCEAN2_CO_RD_MEM_ADDRESS 0x14
142 #define ENOCEAN2_CO_RD_SECURITY 0x15
143 #define ENOCEAN2_CO_WR_SECURITY 0x16
144 #define ENOCEAN2_CO_WR_LEARNMODE 0x17
145 #define ENOCEAN2_CO_RD_LEARNMODE 0x18
146 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD 0x19
147 #define ENOCEAN2_CO_WR_SECUREDEVICE_DEL 0x20
148 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX 0x21
149 #define ENOCEAN2_CO_WR_MODE 0x22
150 #define ENOCEAN2_CO_RD_NUMSECUREDEVICES 0x23
151 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID 0x24
152 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK 0x25
153 #define ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN 0x26
154 #define ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW 0x27
155 #define ENOCEAN2_CO_RD_SECUREDEVICE_PSK 0x28
156 #define ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT 0x29
157 #define ENOCEAN2_CO_SET_BAUDRATE 0x30
158 #define ENOCEAN2_CO_GET_FREQUENCY_INFO 0x31
159 #define ENOCEAN2_CO_GET_STEPCODE 0x32
160 
166 #define ENOCEAN2_SA_WR_LEARNMODE 0x01
167 #define ENOCEAN2_SA_RD_LEARNMODE 0x02
168 #define ENOCEAN2_SA_WR_LEARNCONFIRM 0x03
169 #define ENOCEAN2_SA_WR_CLIENTLEARNRQ 0x04
170 #define ENOCEAN2_SA_WR_RESET 0x05
171 #define ENOCEAN2_SA_RD_LEARNEDCLIENTS 0x06
172 #define ENOCEAN2_SA_WR_RECLAIMS 0x07
173 #define ENOCEAN2_SA_WR_POSTMASTER 0x08
174 
180 #define ENOCEAN2_RET_OK 0x00
181 #define ENOCEAN2_RET_ERROR 0x01
182 #define ENOCEAN2_RET_NOT_SUPPORTED 0x02
183 #define ENOCEAN2_RET_WRONG_PARAM 0x03
184 #define ENOCEAN2_RET_OPERATION_DENIED 0x04
185 #define ENOCEAN2_RET_LOCK_SET 0x05
186 #define ENOCEAN2_RET_BUFFER_TO_SMALL 0x06
187 #define ENOCEAN2_RET_NO_FREE_BUFFER 0x07
188 
194 #define ENOCEAN2_RX_PACKET_MAX_SIZE 256
195 #define ENOCEAN2_SYNC_BYTE 0x55
196 #define ENOCEAN2_HEADER_SIZE 0x04
197 #define ENOCEAN2_SYNC_SIZE 0x06
198 #define ENOCEAN2_CRC8H_OFFSET 0x05
199 #define ENOCEAN2_HEADER_OFFSET 0x01
200 
206 #define STATE_SYNC 1
207 #define STATE_DATA 2
208 #define STATE_FINISH 3
209 
215 #define DRV_RX_BUFFER_SIZE 500
216  // End group macro
219 // --------------------------------------------------------------- PUBLIC TYPES
228 typedef struct
229 {
230  uint16_t data_length;
231  uint8_t option_length;
232  uint8_t type;
233  uint8_t *data_buffer;
234 
236 
240 typedef void ( *enocean2_callback_t ) ( enocean2_packet_t *packet );
241 
245 typedef struct
246 {
247  uint8_t *rx_buffer_begin;
248  uint8_t *rx_buffer_end;
249 
250  uint8_t *rx_head;
251  uint16_t rx_size;
252  uint8_t *rx_tail;
253  uint16_t rx_capacity;
254 
256 
260 typedef struct
261 {
262  uint8_t *rx_buffer;
263  uint16_t rx_size;
264  uint8_t *data_buffer;
265  uint16_t data_size;
266 
268 
272 typedef struct
273 {
274  // Modules
275 
276  uart_t uart;
277 
279  char uart_tx_buffer[ DRV_RX_BUFFER_SIZE ];
280 
283  uint32_t rx_data_cnt;
284  uint32_t rx_packet_size;
285 
287  uint8_t state;
288 
289 } enocean2_t;
290 
294 typedef struct
295 {
296  // Communication gpio pins
297 
298  pin_name_t rx_pin;
299  pin_name_t tx_pin;
300 
301  // static variable
302 
303  uint32_t baud_rate; // Clock speed.
305  uart_data_bits_t data_bit; // Data bits.
306  uart_parity_t parity_bit; // Parity bit.
307  uart_stop_bits_t stop_bit; // Stop bits.
308 
310  // End types group
312 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
313 
319 #ifdef __cplusplus
320 extern "C"{
321 #endif
322 
331 void enocean2_cfg_setup ( enocean2_cfg_t *cfg );
332 
342 
350 void enocean2_default_cfg ( enocean2_t *ctx );
351 
361 void enocean2_generic_write ( enocean2_t *ctx, char *data_buf, uint16_t len );
362 
374 int32_t enocean2_generic_read ( enocean2_t *ctx, char *data_buf, uint16_t max_len );
375 
396 
406 
417 uint8_t enocean2_send ( enocean2_t *ctx, enocean2_packet_t *packet );
418 
431 uint8_t enocean2_rx ( enocean2_ring_buffer_t *rb, uint8_t rx_data );
432 
444 
445 #ifdef __cplusplus
446 }
447 #endif
448 #endif // _ENOCEAN2_H_
449  // End public_function group
452 
453 // ------------------------------------------------------------------------- END
enocean2_t
Click ctx object definition.
Definition: enocean2.h:272
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocean2.h:215
enocean2_t::state
uint8_t state
Definition: enocean2.h:287
enocean2_cfg_t::uart_blocking
bool uart_blocking
Definition: enocean2.h:304
enocean2_ring_buffer_t::rx_buffer_begin
uint8_t * rx_buffer_begin
Definition: enocean2.h:247
enocean2_rx_data_t::data_buffer
uint8_t * data_buffer
Definition: enocean2.h:264
enocean2_t::rx_data_cnt
uint32_t rx_data_cnt
Definition: enocean2.h:283
ENOCEAN2_RETVAL
#define ENOCEAN2_RETVAL
Definition: enocean2.h:62
enocean2_rx_data_t
Click rx data object definition.
Definition: enocean2.h:260
enocean2_t::rx_packet_size
uint32_t rx_packet_size
Definition: enocean2.h:284
enocean2_t::rx_packet_capacity
uint32_t rx_packet_capacity
Definition: enocean2.h:282
enocean2_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocean2.h:306
enocean2_packet_t::option_length
uint8_t option_length
Definition: enocean2.h:231
enocean2_rx
uint8_t enocean2_rx(enocean2_ring_buffer_t *rb, uint8_t rx_data)
Recieve character.
enocean2_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocean2.h:307
enocean2_ring_buffer_t
Click ring buffer object definition.
Definition: enocean2.h:245
enocean2_cfg_t
Click configuration structure definition.
Definition: enocean2.h:294
enocean2_t::recieve_callback
enocean2_callback_t recieve_callback
Definition: enocean2.h:286
enocean2_rx_data_t::rx_size
uint16_t rx_size
Definition: enocean2.h:263
enocean2_cfg_setup
void enocean2_cfg_setup(enocean2_cfg_t *cfg)
Config Object Initialization function.
enocean2_packet_t
Click packet object definition.
Definition: enocean2.h:228
enocean2_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocean2.h:303
enocean2_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocean2.h:299
enocean2_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocean2.h:305
enocean2_ring_buffer_t::rx_head
uint8_t * rx_head
Definition: enocean2.h:250
enocean2_generic_read
int32_t enocean2_generic_read(enocean2_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocean2_init_rx_buff
void enocean2_init_rx_buff(enocean2_t *ctx, enocean2_ring_buffer_t *rb, enocean2_rx_data_t *rx_str)
Module initialization.
enocean2_t::uart
uart_t uart
Definition: enocean2.h:276
enocean2_t::rx_packet
enocean2_packet_t rx_packet
Definition: enocean2.h:281
enocean2_ring_buffer_t::rx_size
uint16_t rx_size
Definition: enocean2.h:251
enocean2_rx_data_t::rx_buffer
uint8_t * rx_buffer
Definition: enocean2.h:262
enocean2_ring_buffer_t::rx_tail
uint8_t * rx_tail
Definition: enocean2.h:252
enocean2_default_cfg
void enocean2_default_cfg(enocean2_t *ctx)
Click Default Configuration function.
enocean2_packet_t::data_length
uint16_t data_length
Definition: enocean2.h:230
enocean2_rx_data_t::data_size
uint16_t data_size
Definition: enocean2.h:265
enocean2_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocean2.h:298
enocean2_packet_t::type
uint8_t type
Definition: enocean2.h:232
enocean2_packet_t::data_buffer
uint8_t * data_buffer
Definition: enocean2.h:233
enocean2_ring_buffer_t::rx_capacity
uint16_t rx_capacity
Definition: enocean2.h:253
uart_rx_buffer
char uart_rx_buffer[PROCESS_RX_BUFFER_SIZE]
Definition: main.c:46
enocean2_callback_t
void(* enocean2_callback_t)(enocean2_packet_t *packet)
Header definition.
Definition: enocean2.h:240
enocean2_ring_buffer_t::rx_buffer_end
uint8_t * rx_buffer_end
Definition: enocean2.h:248
enocean2_send
uint8_t enocean2_send(enocean2_t *ctx, enocean2_packet_t *packet)
Send ESP3 packet.
enocean2_set_callback_handler
void enocean2_set_callback_handler(enocean2_t *ctx, enocean2_callback_t recieve)
Functions for sets callback handler
enocean2_init
ENOCEAN2_RETVAL enocean2_init(enocean2_t *ctx, enocean2_cfg_t *cfg)
Initialization function.
enocean2_packet_recieve
uint8_t enocean2_packet_recieve(enocean2_t *ctx, enocean2_ring_buffer_t *rb)
Process.
enocean2_generic_write
void enocean2_generic_write(enocean2_t *ctx, char *data_buf, uint16_t len)
Generic write function.