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38 #include "mikrosdk_version.h"
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
63 #define ENOCEAN2_MAP_MIKROBUS( cfg, mikrobus ) \
64 cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
65 cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX )
72 #define ENOCEAN2_RETVAL uint8_t
74 #define ENOCEAN2_OK 0x00
75 #define ENOCEAN2_INIT_ERROR 0xFF
82 #define ENOCEAN2_RX_BUFFER_SIZE 200
83 #define ENOCEAN2_SEQUENCE_NUMBER_OFFSET 2
84 #define ENOCEAN2_COMMAND_OFFSET 17
91 #define ENOCEAN2_ERR_OK 0xE0
92 #define ENOCEAN2_ERR_BUFFER_FULL 0xE1
93 #define ENOCEAN2_ERR_CHAR_TIMEOUT 0xE2
94 #define ENOCEAN2_ERR_INVALID_SIZE 0xE3
95 #define ENOCEAN2_ERR_NO_MEMORY 0xE4
102 #define ENOCEAN2_TYPE_RADIO_ERP1 0x01
103 #define ENOCEAN2_TYPE_RESPONSE 0x02
104 #define ENOCEAN2_TYPE_RADIO_SUB_TEL 0x03
105 #define ENOCEAN2_TYPE_EVENT 0x04
106 #define ENOCEAN2_TYPE_COMMON 0x05
107 #define ENOCEAN2_TYPE_SMART_ACK 0x06
108 #define ENOCEAN2_TYPE_REMOTE_MAN 0x07
109 #define ENOCEAN2_TYPE_RADIO_MESSAGE 0x09
110 #define ENOCEAN2_TYPE_RADIO_ERP2 0x0A
111 #define ENOCEAN2_TYPE_RADIO_802_15_4 0x10
112 #define ENOCEAN2_TYPE_COMMAND_2_4 0x11
119 #define ENOCEAN2_EV_SA_RECLAIM_NOT_SUCCESSFUL 0x01
120 #define ENOCEAN2_EV_SA_CONFIRM_LEARN 0x02
121 #define ENOCEAN2_EV_SA_LEARN_ACK 0x03
122 #define ENOCEAN2_EV_CO_READY 0x04
123 #define ENOCEAN2_EV_CO_EVENT_SECUREDEVICES 0x05
124 #define ENOCEAN2_EV_CO_DUTYCYCLE_LIMIT 0x06
125 #define ENOCEAN2_EV_CO_TRANSMIT_FAILED 0x07
132 #define ENOCEAN2_CO_WR_SLEEP 0x01
133 #define ENOCEAN2_CO_WR_RESET 0x02
134 #define ENOCEAN2_CO_RD_VERSION 0x03
135 #define ENOCEAN2_CO_RD_SYS_LOG 0x04
136 #define ENOCEAN2_CO_WR_SYS_LOG 0x05
137 #define ENOCEAN2_CO_WR_BIST 0x06
138 #define ENOCEAN2_CO_WR_IDBASE 0x07
139 #define ENOCEAN2_CO_RD_IDBASE 0x08
140 #define ENOCEAN2_CO_WR_REPEATER 0x09
141 #define ENOCEAN2_CO_RD_REPEATER 0x0A
142 #define ENOCEAN2_CO_WR_FILTER_ADD 0x0B
143 #define ENOCEAN2_CO_WR_FILTER_DEL 0x0C
144 #define ENOCEAN2_CO_WR_FILTER_DEL_ALL 0x0D
145 #define ENOCEAN2_CO_WR_FILTER_ENABLE 0x0E
146 #define ENOCEAN2_CO_RD_FILTER 0x0F
147 #define ENOCEAN2_CO_WR_WAIT_MATURITY 0x10
148 #define ENOCEAN2_CO_WR_SUBTEL 0x11
149 #define ENOCEAN2_CO_WR_MEM 0x12
150 #define ENOCEAN2_CO_RD_MEM 0x13
151 #define ENOCEAN2_CO_RD_MEM_ADDRESS 0x14
152 #define ENOCEAN2_CO_RD_SECURITY 0x15
153 #define ENOCEAN2_CO_WR_SECURITY 0x16
154 #define ENOCEAN2_CO_WR_LEARNMODE 0x17
155 #define ENOCEAN2_CO_RD_LEARNMODE 0x18
156 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD 0x19
157 #define ENOCEAN2_CO_WR_SECUREDEVICE_DEL 0x20
158 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX 0x21
159 #define ENOCEAN2_CO_WR_MODE 0x22
160 #define ENOCEAN2_CO_RD_NUMSECUREDEVICES 0x23
161 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID 0x24
162 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK 0x25
163 #define ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN 0x26
164 #define ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW 0x27
165 #define ENOCEAN2_CO_RD_SECUREDEVICE_PSK 0x28
166 #define ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT 0x29
167 #define ENOCEAN2_CO_SET_BAUDRATE 0x30
168 #define ENOCEAN2_CO_GET_FREQUENCY_INFO 0x31
169 #define ENOCEAN2_CO_GET_STEPCODE 0x32
176 #define ENOCEAN2_SA_WR_LEARNMODE 0x01
177 #define ENOCEAN2_SA_RD_LEARNMODE 0x02
178 #define ENOCEAN2_SA_WR_LEARNCONFIRM 0x03
179 #define ENOCEAN2_SA_WR_CLIENTLEARNRQ 0x04
180 #define ENOCEAN2_SA_WR_RESET 0x05
181 #define ENOCEAN2_SA_RD_LEARNEDCLIENTS 0x06
182 #define ENOCEAN2_SA_WR_RECLAIMS 0x07
183 #define ENOCEAN2_SA_WR_POSTMASTER 0x08
190 #define ENOCEAN2_RET_OK 0x00
191 #define ENOCEAN2_RET_ERROR 0x01
192 #define ENOCEAN2_RET_NOT_SUPPORTED 0x02
193 #define ENOCEAN2_RET_WRONG_PARAM 0x03
194 #define ENOCEAN2_RET_OPERATION_DENIED 0x04
195 #define ENOCEAN2_RET_LOCK_SET 0x05
196 #define ENOCEAN2_RET_BUFFER_TO_SMALL 0x06
197 #define ENOCEAN2_RET_NO_FREE_BUFFER 0x07
204 #define ENOCEAN2_RX_PACKET_MAX_SIZE 256
205 #define ENOCEAN2_SYNC_BYTE 0x55
206 #define ENOCEAN2_HEADER_SIZE 0x04
207 #define ENOCEAN2_SYNC_SIZE 0x06
208 #define ENOCEAN2_CRC8H_OFFSET 0x05
209 #define ENOCEAN2_HEADER_OFFSET 0x01
218 #define STATE_FINISH 3
225 #define DRV_RX_BUFFER_SIZE 500
458 #endif // _ENOCEAN2_H_
Click ctx object definition.
Definition: enocean2.h:283
#define DRV_RX_BUFFER_SIZE
Definition: enocean2.h:225
uint8_t state
Definition: enocean2.h:297
bool uart_blocking
Definition: enocean2.h:314
uint8_t * rx_buffer_begin
Definition: enocean2.h:257
uint8_t * data_buffer
Definition: enocean2.h:274
uint32_t rx_data_cnt
Definition: enocean2.h:293
#define ENOCEAN2_RETVAL
Definition: enocean2.h:72
Click rx data object definition.
Definition: enocean2.h:271
uint32_t rx_packet_size
Definition: enocean2.h:294
uint32_t rx_packet_capacity
Definition: enocean2.h:292
uart_parity_t parity_bit
Definition: enocean2.h:316
uint8_t option_length
Definition: enocean2.h:241
uint8_t enocean2_rx(enocean2_ring_buffer_t *rb, uint8_t rx_data)
Recieve character.
uart_stop_bits_t stop_bit
Definition: enocean2.h:317
Click ring buffer object definition.
Definition: enocean2.h:256
Click configuration structure definition.
Definition: enocean2.h:305
enocean2_callback_t recieve_callback
Definition: enocean2.h:296
uint16_t rx_size
Definition: enocean2.h:273
void enocean2_cfg_setup(enocean2_cfg_t *cfg)
Config Object Initialization function.
Click packet object definition.
Definition: enocean2.h:239
uint32_t baud_rate
Definition: enocean2.h:313
pin_name_t tx_pin
Definition: enocean2.h:309
uart_data_bits_t data_bit
Definition: enocean2.h:315
uint8_t * rx_head
Definition: enocean2.h:260
int32_t enocean2_generic_read(enocean2_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
void enocean2_init_rx_buff(enocean2_t *ctx, enocean2_ring_buffer_t *rb, enocean2_rx_data_t *rx_str)
Module initialization.
uart_t uart
Definition: enocean2.h:286
enocean2_packet_t rx_packet
Definition: enocean2.h:291
uint16_t rx_size
Definition: enocean2.h:261
uint8_t * rx_buffer
Definition: enocean2.h:272
uint8_t * rx_tail
Definition: enocean2.h:262
void enocean2_default_cfg(enocean2_t *ctx)
Click Default Configuration function.
uint16_t data_length
Definition: enocean2.h:240
uint16_t data_size
Definition: enocean2.h:275
pin_name_t rx_pin
Definition: enocean2.h:308
uint8_t type
Definition: enocean2.h:242
uint8_t * data_buffer
Definition: enocean2.h:243
uint16_t rx_capacity
Definition: enocean2.h:263
char uart_rx_buffer[PROCESS_RX_BUFFER_SIZE]
Definition: main.c:46
void(* enocean2_callback_t)(enocean2_packet_t *packet)
Header definition.
Definition: enocean2.h:250
uint8_t * rx_buffer_end
Definition: enocean2.h:258
uint8_t enocean2_send(enocean2_t *ctx, enocean2_packet_t *packet)
Send ESP3 packet.
void enocean2_set_callback_handler(enocean2_t *ctx, enocean2_callback_t recieve)
Functions for sets callback handler
ENOCEAN2_RETVAL enocean2_init(enocean2_t *ctx, enocean2_cfg_t *cfg)
Initialization function.
uint8_t enocean2_packet_recieve(enocean2_t *ctx, enocean2_ring_buffer_t *rb)
Process.
void enocean2_generic_write(enocean2_t *ctx, char *data_buf, uint16_t len)
Generic write function.