enocean2  2.0.0.0
enocean2.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN2_H
36 #define ENOCEAN2_H
37 
38 #include "mikrosdk_version.h"
39 
40 #ifdef __GNUC__
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
43 #else
44 #include "delays.h"
45 #endif
46 #endif
47 
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_uart.h"
51 
52 
53 // -------------------------------------------------------------- PUBLIC MACROS
63 #define ENOCEAN2_MAP_MIKROBUS( cfg, mikrobus ) \
64  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
65  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX )
66 
72 #define ENOCEAN2_RETVAL uint8_t
73 
74 #define ENOCEAN2_OK 0x00
75 #define ENOCEAN2_INIT_ERROR 0xFF
76 
82 #define ENOCEAN2_RX_BUFFER_SIZE 200
83 #define ENOCEAN2_SEQUENCE_NUMBER_OFFSET 2
84 #define ENOCEAN2_COMMAND_OFFSET 17
85 
91 #define ENOCEAN2_ERR_OK 0xE0
92 #define ENOCEAN2_ERR_BUFFER_FULL 0xE1
93 #define ENOCEAN2_ERR_CHAR_TIMEOUT 0xE2
94 #define ENOCEAN2_ERR_INVALID_SIZE 0xE3
95 #define ENOCEAN2_ERR_NO_MEMORY 0xE4
96 
102 #define ENOCEAN2_TYPE_RADIO_ERP1 0x01
103 #define ENOCEAN2_TYPE_RESPONSE 0x02
104 #define ENOCEAN2_TYPE_RADIO_SUB_TEL 0x03
105 #define ENOCEAN2_TYPE_EVENT 0x04
106 #define ENOCEAN2_TYPE_COMMON 0x05
107 #define ENOCEAN2_TYPE_SMART_ACK 0x06
108 #define ENOCEAN2_TYPE_REMOTE_MAN 0x07
109 #define ENOCEAN2_TYPE_RADIO_MESSAGE 0x09
110 #define ENOCEAN2_TYPE_RADIO_ERP2 0x0A
111 #define ENOCEAN2_TYPE_RADIO_802_15_4 0x10
112 #define ENOCEAN2_TYPE_COMMAND_2_4 0x11
113 
119 #define ENOCEAN2_EV_SA_RECLAIM_NOT_SUCCESSFUL 0x01
120 #define ENOCEAN2_EV_SA_CONFIRM_LEARN 0x02
121 #define ENOCEAN2_EV_SA_LEARN_ACK 0x03
122 #define ENOCEAN2_EV_CO_READY 0x04
123 #define ENOCEAN2_EV_CO_EVENT_SECUREDEVICES 0x05
124 #define ENOCEAN2_EV_CO_DUTYCYCLE_LIMIT 0x06
125 #define ENOCEAN2_EV_CO_TRANSMIT_FAILED 0x07
126 
132 #define ENOCEAN2_CO_WR_SLEEP 0x01
133 #define ENOCEAN2_CO_WR_RESET 0x02
134 #define ENOCEAN2_CO_RD_VERSION 0x03
135 #define ENOCEAN2_CO_RD_SYS_LOG 0x04
136 #define ENOCEAN2_CO_WR_SYS_LOG 0x05
137 #define ENOCEAN2_CO_WR_BIST 0x06
138 #define ENOCEAN2_CO_WR_IDBASE 0x07
139 #define ENOCEAN2_CO_RD_IDBASE 0x08
140 #define ENOCEAN2_CO_WR_REPEATER 0x09
141 #define ENOCEAN2_CO_RD_REPEATER 0x0A
142 #define ENOCEAN2_CO_WR_FILTER_ADD 0x0B
143 #define ENOCEAN2_CO_WR_FILTER_DEL 0x0C
144 #define ENOCEAN2_CO_WR_FILTER_DEL_ALL 0x0D
145 #define ENOCEAN2_CO_WR_FILTER_ENABLE 0x0E
146 #define ENOCEAN2_CO_RD_FILTER 0x0F
147 #define ENOCEAN2_CO_WR_WAIT_MATURITY 0x10
148 #define ENOCEAN2_CO_WR_SUBTEL 0x11
149 #define ENOCEAN2_CO_WR_MEM 0x12
150 #define ENOCEAN2_CO_RD_MEM 0x13
151 #define ENOCEAN2_CO_RD_MEM_ADDRESS 0x14
152 #define ENOCEAN2_CO_RD_SECURITY 0x15
153 #define ENOCEAN2_CO_WR_SECURITY 0x16
154 #define ENOCEAN2_CO_WR_LEARNMODE 0x17
155 #define ENOCEAN2_CO_RD_LEARNMODE 0x18
156 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD 0x19
157 #define ENOCEAN2_CO_WR_SECUREDEVICE_DEL 0x20
158 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX 0x21
159 #define ENOCEAN2_CO_WR_MODE 0x22
160 #define ENOCEAN2_CO_RD_NUMSECUREDEVICES 0x23
161 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID 0x24
162 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK 0x25
163 #define ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN 0x26
164 #define ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW 0x27
165 #define ENOCEAN2_CO_RD_SECUREDEVICE_PSK 0x28
166 #define ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT 0x29
167 #define ENOCEAN2_CO_SET_BAUDRATE 0x30
168 #define ENOCEAN2_CO_GET_FREQUENCY_INFO 0x31
169 #define ENOCEAN2_CO_GET_STEPCODE 0x32
170 
176 #define ENOCEAN2_SA_WR_LEARNMODE 0x01
177 #define ENOCEAN2_SA_RD_LEARNMODE 0x02
178 #define ENOCEAN2_SA_WR_LEARNCONFIRM 0x03
179 #define ENOCEAN2_SA_WR_CLIENTLEARNRQ 0x04
180 #define ENOCEAN2_SA_WR_RESET 0x05
181 #define ENOCEAN2_SA_RD_LEARNEDCLIENTS 0x06
182 #define ENOCEAN2_SA_WR_RECLAIMS 0x07
183 #define ENOCEAN2_SA_WR_POSTMASTER 0x08
184 
190 #define ENOCEAN2_RET_OK 0x00
191 #define ENOCEAN2_RET_ERROR 0x01
192 #define ENOCEAN2_RET_NOT_SUPPORTED 0x02
193 #define ENOCEAN2_RET_WRONG_PARAM 0x03
194 #define ENOCEAN2_RET_OPERATION_DENIED 0x04
195 #define ENOCEAN2_RET_LOCK_SET 0x05
196 #define ENOCEAN2_RET_BUFFER_TO_SMALL 0x06
197 #define ENOCEAN2_RET_NO_FREE_BUFFER 0x07
198 
204 #define ENOCEAN2_RX_PACKET_MAX_SIZE 256
205 #define ENOCEAN2_SYNC_BYTE 0x55
206 #define ENOCEAN2_HEADER_SIZE 0x04
207 #define ENOCEAN2_SYNC_SIZE 0x06
208 #define ENOCEAN2_CRC8H_OFFSET 0x05
209 #define ENOCEAN2_HEADER_OFFSET 0x01
210 
216 #define STATE_SYNC 1
217 #define STATE_DATA 2
218 #define STATE_FINISH 3
219 
225 #define DRV_RX_BUFFER_SIZE 500
226  // End group macro
229 // --------------------------------------------------------------- PUBLIC TYPES
238 typedef struct
239 {
240  uint16_t data_length;
241  uint8_t option_length;
242  uint8_t type;
243  uint8_t *data_buffer;
244 
246 
250 typedef void ( *enocean2_callback_t ) ( enocean2_packet_t *packet );
251 
255 typedef struct
256 {
257  uint8_t *rx_buffer_begin;
258  uint8_t *rx_buffer_end;
259 
260  uint8_t *rx_head;
261  uint16_t rx_size;
262  uint8_t *rx_tail;
263  uint16_t rx_capacity;
264 
266 
270 typedef struct
271 {
272  uint8_t *rx_buffer;
273  uint16_t rx_size;
274  uint8_t *data_buffer;
275  uint16_t data_size;
276 
278 
282 typedef struct
283 {
284  // Modules
285 
286  uart_t uart;
287 
289  char uart_tx_buffer[ DRV_RX_BUFFER_SIZE ];
290 
293  uint32_t rx_data_cnt;
294  uint32_t rx_packet_size;
295 
297  uint8_t state;
298 
299 } enocean2_t;
300 
304 typedef struct
305 {
306  // Communication gpio pins
307 
308  pin_name_t rx_pin;
309  pin_name_t tx_pin;
310 
311  // static variable
312 
313  uint32_t baud_rate; // Clock speed.
315  uart_data_bits_t data_bit; // Data bits.
316  uart_parity_t parity_bit; // Parity bit.
317  uart_stop_bits_t stop_bit; // Stop bits.
318 
320  // End types group
322 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
323 
329 #ifdef __cplusplus
330 extern "C"{
331 #endif
332 
342 
352 
361 
371 void enocean2_generic_write ( enocean2_t *ctx, char *data_buf, uint16_t len );
372 
384 int32_t enocean2_generic_read ( enocean2_t *ctx, char *data_buf, uint16_t max_len );
385 
406 
416 
427 uint8_t enocean2_send ( enocean2_t *ctx, enocean2_packet_t *packet );
428 
441 uint8_t enocean2_rx ( enocean2_ring_buffer_t *rb, uint8_t rx_data );
442 
454 
455 #ifdef __cplusplus
456 }
457 #endif
458 #endif // _ENOCEAN2_H_
459  // End public_function group
462 
463 // ------------------------------------------------------------------------- END
enocean2_t
Click ctx object definition.
Definition: enocean2.h:283
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocean2.h:225
enocean2_t::state
uint8_t state
Definition: enocean2.h:297
enocean2_cfg_t::uart_blocking
bool uart_blocking
Definition: enocean2.h:314
enocean2_ring_buffer_t::rx_buffer_begin
uint8_t * rx_buffer_begin
Definition: enocean2.h:257
enocean2_rx_data_t::data_buffer
uint8_t * data_buffer
Definition: enocean2.h:274
enocean2_t::rx_data_cnt
uint32_t rx_data_cnt
Definition: enocean2.h:293
ENOCEAN2_RETVAL
#define ENOCEAN2_RETVAL
Definition: enocean2.h:72
enocean2_rx_data_t
Click rx data object definition.
Definition: enocean2.h:271
enocean2_t::rx_packet_size
uint32_t rx_packet_size
Definition: enocean2.h:294
enocean2_t::rx_packet_capacity
uint32_t rx_packet_capacity
Definition: enocean2.h:292
enocean2_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocean2.h:316
enocean2_packet_t::option_length
uint8_t option_length
Definition: enocean2.h:241
enocean2_rx
uint8_t enocean2_rx(enocean2_ring_buffer_t *rb, uint8_t rx_data)
Recieve character.
enocean2_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocean2.h:317
enocean2_ring_buffer_t
Click ring buffer object definition.
Definition: enocean2.h:256
enocean2_cfg_t
Click configuration structure definition.
Definition: enocean2.h:305
enocean2_t::recieve_callback
enocean2_callback_t recieve_callback
Definition: enocean2.h:296
enocean2_rx_data_t::rx_size
uint16_t rx_size
Definition: enocean2.h:273
enocean2_cfg_setup
void enocean2_cfg_setup(enocean2_cfg_t *cfg)
Config Object Initialization function.
enocean2_packet_t
Click packet object definition.
Definition: enocean2.h:239
enocean2_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocean2.h:313
enocean2_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocean2.h:309
enocean2_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocean2.h:315
enocean2_ring_buffer_t::rx_head
uint8_t * rx_head
Definition: enocean2.h:260
enocean2_generic_read
int32_t enocean2_generic_read(enocean2_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocean2_init_rx_buff
void enocean2_init_rx_buff(enocean2_t *ctx, enocean2_ring_buffer_t *rb, enocean2_rx_data_t *rx_str)
Module initialization.
enocean2_t::uart
uart_t uart
Definition: enocean2.h:286
enocean2_t::rx_packet
enocean2_packet_t rx_packet
Definition: enocean2.h:291
enocean2_ring_buffer_t::rx_size
uint16_t rx_size
Definition: enocean2.h:261
enocean2_rx_data_t::rx_buffer
uint8_t * rx_buffer
Definition: enocean2.h:272
enocean2_ring_buffer_t::rx_tail
uint8_t * rx_tail
Definition: enocean2.h:262
enocean2_default_cfg
void enocean2_default_cfg(enocean2_t *ctx)
Click Default Configuration function.
enocean2_packet_t::data_length
uint16_t data_length
Definition: enocean2.h:240
enocean2_rx_data_t::data_size
uint16_t data_size
Definition: enocean2.h:275
enocean2_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocean2.h:308
enocean2_packet_t::type
uint8_t type
Definition: enocean2.h:242
enocean2_packet_t::data_buffer
uint8_t * data_buffer
Definition: enocean2.h:243
enocean2_ring_buffer_t::rx_capacity
uint16_t rx_capacity
Definition: enocean2.h:263
uart_rx_buffer
char uart_rx_buffer[PROCESS_RX_BUFFER_SIZE]
Definition: main.c:46
enocean2_callback_t
void(* enocean2_callback_t)(enocean2_packet_t *packet)
Header definition.
Definition: enocean2.h:250
enocean2_ring_buffer_t::rx_buffer_end
uint8_t * rx_buffer_end
Definition: enocean2.h:258
enocean2_send
uint8_t enocean2_send(enocean2_t *ctx, enocean2_packet_t *packet)
Send ESP3 packet.
enocean2_set_callback_handler
void enocean2_set_callback_handler(enocean2_t *ctx, enocean2_callback_t recieve)
Functions for sets callback handler
enocean2_init
ENOCEAN2_RETVAL enocean2_init(enocean2_t *ctx, enocean2_cfg_t *cfg)
Initialization function.
enocean2_packet_recieve
uint8_t enocean2_packet_recieve(enocean2_t *ctx, enocean2_ring_buffer_t *rb)
Process.
enocean2_generic_write
void enocean2_generic_write(enocean2_t *ctx, char *data_buf, uint16_t len)
Generic write function.