enocean2  2.0.0.0
enocean2.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN2_H
36 #define ENOCEAN2_H
37 
42 #ifdef PREINIT_SUPPORTED
43 #include "preinit.h"
44 #endif
45 
46 #ifdef MikroCCoreVersion
47  #if MikroCCoreVersion >= 1
48  #include "delays.h"
49  #endif
50 #endif
51 
52 #include "drv_digital_out.h"
53 #include "drv_digital_in.h"
54 #include "drv_uart.h"
55 
56 
57 // -------------------------------------------------------------- PUBLIC MACROS
67 #define ENOCEAN2_MAP_MIKROBUS( cfg, mikrobus ) \
68  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
69  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX )
70 
76 #define ENOCEAN2_RETVAL uint8_t
77 
78 #define ENOCEAN2_OK 0x00
79 #define ENOCEAN2_INIT_ERROR 0xFF
80 
86 #define ENOCEAN2_RX_BUFFER_SIZE 200
87 #define ENOCEAN2_SEQUENCE_NUMBER_OFFSET 2
88 #define ENOCEAN2_COMMAND_OFFSET 17
89 
95 #define ENOCEAN2_ERR_OK 0xE0
96 #define ENOCEAN2_ERR_BUFFER_FULL 0xE1
97 #define ENOCEAN2_ERR_CHAR_TIMEOUT 0xE2
98 #define ENOCEAN2_ERR_INVALID_SIZE 0xE3
99 #define ENOCEAN2_ERR_NO_MEMORY 0xE4
100 
106 #define ENOCEAN2_TYPE_RADIO_ERP1 0x01
107 #define ENOCEAN2_TYPE_RESPONSE 0x02
108 #define ENOCEAN2_TYPE_RADIO_SUB_TEL 0x03
109 #define ENOCEAN2_TYPE_EVENT 0x04
110 #define ENOCEAN2_TYPE_COMMON 0x05
111 #define ENOCEAN2_TYPE_SMART_ACK 0x06
112 #define ENOCEAN2_TYPE_REMOTE_MAN 0x07
113 #define ENOCEAN2_TYPE_RADIO_MESSAGE 0x09
114 #define ENOCEAN2_TYPE_RADIO_ERP2 0x0A
115 #define ENOCEAN2_TYPE_RADIO_802_15_4 0x10
116 #define ENOCEAN2_TYPE_COMMAND_2_4 0x11
117 
123 #define ENOCEAN2_EV_SA_RECLAIM_NOT_SUCCESSFUL 0x01
124 #define ENOCEAN2_EV_SA_CONFIRM_LEARN 0x02
125 #define ENOCEAN2_EV_SA_LEARN_ACK 0x03
126 #define ENOCEAN2_EV_CO_READY 0x04
127 #define ENOCEAN2_EV_CO_EVENT_SECUREDEVICES 0x05
128 #define ENOCEAN2_EV_CO_DUTYCYCLE_LIMIT 0x06
129 #define ENOCEAN2_EV_CO_TRANSMIT_FAILED 0x07
130 
136 #define ENOCEAN2_CO_WR_SLEEP 0x01
137 #define ENOCEAN2_CO_WR_RESET 0x02
138 #define ENOCEAN2_CO_RD_VERSION 0x03
139 #define ENOCEAN2_CO_RD_SYS_LOG 0x04
140 #define ENOCEAN2_CO_WR_SYS_LOG 0x05
141 #define ENOCEAN2_CO_WR_BIST 0x06
142 #define ENOCEAN2_CO_WR_IDBASE 0x07
143 #define ENOCEAN2_CO_RD_IDBASE 0x08
144 #define ENOCEAN2_CO_WR_REPEATER 0x09
145 #define ENOCEAN2_CO_RD_REPEATER 0x0A
146 #define ENOCEAN2_CO_WR_FILTER_ADD 0x0B
147 #define ENOCEAN2_CO_WR_FILTER_DEL 0x0C
148 #define ENOCEAN2_CO_WR_FILTER_DEL_ALL 0x0D
149 #define ENOCEAN2_CO_WR_FILTER_ENABLE 0x0E
150 #define ENOCEAN2_CO_RD_FILTER 0x0F
151 #define ENOCEAN2_CO_WR_WAIT_MATURITY 0x10
152 #define ENOCEAN2_CO_WR_SUBTEL 0x11
153 #define ENOCEAN2_CO_WR_MEM 0x12
154 #define ENOCEAN2_CO_RD_MEM 0x13
155 #define ENOCEAN2_CO_RD_MEM_ADDRESS 0x14
156 #define ENOCEAN2_CO_RD_SECURITY 0x15
157 #define ENOCEAN2_CO_WR_SECURITY 0x16
158 #define ENOCEAN2_CO_WR_LEARNMODE 0x17
159 #define ENOCEAN2_CO_RD_LEARNMODE 0x18
160 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD 0x19
161 #define ENOCEAN2_CO_WR_SECUREDEVICE_DEL 0x20
162 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX 0x21
163 #define ENOCEAN2_CO_WR_MODE 0x22
164 #define ENOCEAN2_CO_RD_NUMSECUREDEVICES 0x23
165 #define ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID 0x24
166 #define ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK 0x25
167 #define ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN 0x26
168 #define ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW 0x27
169 #define ENOCEAN2_CO_RD_SECUREDEVICE_PSK 0x28
170 #define ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT 0x29
171 #define ENOCEAN2_CO_SET_BAUDRATE 0x30
172 #define ENOCEAN2_CO_GET_FREQUENCY_INFO 0x31
173 #define ENOCEAN2_CO_GET_STEPCODE 0x32
174 
180 #define ENOCEAN2_SA_WR_LEARNMODE 0x01
181 #define ENOCEAN2_SA_RD_LEARNMODE 0x02
182 #define ENOCEAN2_SA_WR_LEARNCONFIRM 0x03
183 #define ENOCEAN2_SA_WR_CLIENTLEARNRQ 0x04
184 #define ENOCEAN2_SA_WR_RESET 0x05
185 #define ENOCEAN2_SA_RD_LEARNEDCLIENTS 0x06
186 #define ENOCEAN2_SA_WR_RECLAIMS 0x07
187 #define ENOCEAN2_SA_WR_POSTMASTER 0x08
188 
194 #define ENOCEAN2_RET_OK 0x00
195 #define ENOCEAN2_RET_ERROR 0x01
196 #define ENOCEAN2_RET_NOT_SUPPORTED 0x02
197 #define ENOCEAN2_RET_WRONG_PARAM 0x03
198 #define ENOCEAN2_RET_OPERATION_DENIED 0x04
199 #define ENOCEAN2_RET_LOCK_SET 0x05
200 #define ENOCEAN2_RET_BUFFER_TO_SMALL 0x06
201 #define ENOCEAN2_RET_NO_FREE_BUFFER 0x07
202 
208 #define ENOCEAN2_RX_PACKET_MAX_SIZE 256
209 #define ENOCEAN2_SYNC_BYTE 0x55
210 #define ENOCEAN2_HEADER_SIZE 0x04
211 #define ENOCEAN2_SYNC_SIZE 0x06
212 #define ENOCEAN2_CRC8H_OFFSET 0x05
213 #define ENOCEAN2_HEADER_OFFSET 0x01
214 
220 #define STATE_SYNC 1
221 #define STATE_DATA 2
222 #define STATE_FINISH 3
223 
229 #define DRV_RX_BUFFER_SIZE 500
230  // End group macro
233 // --------------------------------------------------------------- PUBLIC TYPES
242 typedef struct
243 {
244  uint16_t data_length;
245  uint8_t option_length;
246  uint8_t type;
247  uint8_t *data_buffer;
248 
250 
254 typedef void ( *enocean2_callback_t ) ( enocean2_packet_t *packet );
255 
259 typedef struct
260 {
261  uint8_t *rx_buffer_begin;
262  uint8_t *rx_buffer_end;
263 
264  uint8_t *rx_head;
265  uint16_t rx_size;
266  uint8_t *rx_tail;
267  uint16_t rx_capacity;
268 
270 
274 typedef struct
275 {
276  uint8_t *rx_buffer;
277  uint16_t rx_size;
278  uint8_t *data_buffer;
279  uint16_t data_size;
280 
282 
286 typedef struct
287 {
288  // Modules
289 
290  uart_t uart;
291 
293  char uart_tx_buffer[ DRV_RX_BUFFER_SIZE ];
294 
297  uint32_t rx_data_cnt;
298  uint32_t rx_packet_size;
299 
301  uint8_t state;
302 
303 } enocean2_t;
304 
308 typedef struct
309 {
310  // Communication gpio pins
311 
312  pin_name_t rx_pin;
313  pin_name_t tx_pin;
314 
315  // static variable
316 
317  uint32_t baud_rate; // Clock speed.
319  uart_data_bits_t data_bit; // Data bits.
320  uart_parity_t parity_bit; // Parity bit.
321  uart_stop_bits_t stop_bit; // Stop bits.
322 
324  // End types group
326 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
327 
333 #ifdef __cplusplus
334 extern "C"{
335 #endif
336 
346 
356 
365 
375 void enocean2_generic_write ( enocean2_t *ctx, char *data_buf, uint16_t len );
376 
388 int32_t enocean2_generic_read ( enocean2_t *ctx, char *data_buf, uint16_t max_len );
389 
410 
420 
431 uint8_t enocean2_send ( enocean2_t *ctx, enocean2_packet_t *packet );
432 
445 uint8_t enocean2_rx ( enocean2_ring_buffer_t *rb, uint8_t rx_data );
446 
458 
459 #ifdef __cplusplus
460 }
461 #endif
462 #endif // _ENOCEAN2_H_
463  // End public_function group
466 
467 // ------------------------------------------------------------------------- END
enocean2_t
Click ctx object definition.
Definition: enocean2.h:287
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocean2.h:229
enocean2_t::state
uint8_t state
Definition: enocean2.h:301
enocean2_cfg_t::uart_blocking
bool uart_blocking
Definition: enocean2.h:318
enocean2_ring_buffer_t::rx_buffer_begin
uint8_t * rx_buffer_begin
Definition: enocean2.h:261
enocean2_rx_data_t::data_buffer
uint8_t * data_buffer
Definition: enocean2.h:278
enocean2_t::rx_data_cnt
uint32_t rx_data_cnt
Definition: enocean2.h:297
ENOCEAN2_RETVAL
#define ENOCEAN2_RETVAL
Definition: enocean2.h:76
enocean2_rx_data_t
Click rx data object definition.
Definition: enocean2.h:275
enocean2_t::rx_packet_size
uint32_t rx_packet_size
Definition: enocean2.h:298
enocean2_t::rx_packet_capacity
uint32_t rx_packet_capacity
Definition: enocean2.h:296
enocean2_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocean2.h:320
enocean2_packet_t::option_length
uint8_t option_length
Definition: enocean2.h:245
enocean2_rx
uint8_t enocean2_rx(enocean2_ring_buffer_t *rb, uint8_t rx_data)
Recieve character.
enocean2_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocean2.h:321
enocean2_ring_buffer_t
Click ring buffer object definition.
Definition: enocean2.h:260
enocean2_cfg_t
Click configuration structure definition.
Definition: enocean2.h:309
enocean2_t::recieve_callback
enocean2_callback_t recieve_callback
Definition: enocean2.h:300
enocean2_rx_data_t::rx_size
uint16_t rx_size
Definition: enocean2.h:277
enocean2_cfg_setup
void enocean2_cfg_setup(enocean2_cfg_t *cfg)
Config Object Initialization function.
enocean2_packet_t
Click packet object definition.
Definition: enocean2.h:243
enocean2_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocean2.h:317
enocean2_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocean2.h:313
enocean2_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocean2.h:319
enocean2_ring_buffer_t::rx_head
uint8_t * rx_head
Definition: enocean2.h:264
enocean2_generic_read
int32_t enocean2_generic_read(enocean2_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocean2_init_rx_buff
void enocean2_init_rx_buff(enocean2_t *ctx, enocean2_ring_buffer_t *rb, enocean2_rx_data_t *rx_str)
Module initialization.
enocean2_t::uart
uart_t uart
Definition: enocean2.h:290
enocean2_t::rx_packet
enocean2_packet_t rx_packet
Definition: enocean2.h:295
enocean2_ring_buffer_t::rx_size
uint16_t rx_size
Definition: enocean2.h:265
enocean2_rx_data_t::rx_buffer
uint8_t * rx_buffer
Definition: enocean2.h:276
enocean2_ring_buffer_t::rx_tail
uint8_t * rx_tail
Definition: enocean2.h:266
enocean2_default_cfg
void enocean2_default_cfg(enocean2_t *ctx)
Click Default Configuration function.
enocean2_packet_t::data_length
uint16_t data_length
Definition: enocean2.h:244
enocean2_rx_data_t::data_size
uint16_t data_size
Definition: enocean2.h:279
enocean2_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocean2.h:312
enocean2_packet_t::type
uint8_t type
Definition: enocean2.h:246
enocean2_packet_t::data_buffer
uint8_t * data_buffer
Definition: enocean2.h:247
enocean2_ring_buffer_t::rx_capacity
uint16_t rx_capacity
Definition: enocean2.h:267
uart_rx_buffer
char uart_rx_buffer[PROCESS_RX_BUFFER_SIZE]
Definition: main.c:46
enocean2_callback_t
void(* enocean2_callback_t)(enocean2_packet_t *packet)
Header definition.
Definition: enocean2.h:254
enocean2_ring_buffer_t::rx_buffer_end
uint8_t * rx_buffer_end
Definition: enocean2.h:262
enocean2_send
uint8_t enocean2_send(enocean2_t *ctx, enocean2_packet_t *packet)
Send ESP3 packet.
enocean2_set_callback_handler
void enocean2_set_callback_handler(enocean2_t *ctx, enocean2_callback_t recieve)
Functions for sets callback handler
enocean2_init
ENOCEAN2_RETVAL enocean2_init(enocean2_t *ctx, enocean2_cfg_t *cfg)
Initialization function.
enocean2_packet_recieve
uint8_t enocean2_packet_recieve(enocean2_t *ctx, enocean2_ring_buffer_t *rb)
Process.
enocean2_generic_write
void enocean2_generic_write(enocean2_t *ctx, char *data_buf, uint16_t len)
Generic write function.