c9dof2  2.0.0.0
c9dof2.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef C9DOF2_H
36 #define C9DOF2_H
37 
38 #include "mikrosdk_version.h"
39 
40 #ifdef __GNUC__
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
43 #else
44 #include "delays.h"
45 #endif
46 #endif
47 
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_spi_master.h"
51 
52 
53 // -------------------------------------------------------------- PUBLIC MACROS
64 #define C9DOF2_MAP_MIKROBUS( cfg, mikrobus ) \
65  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
66  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
67  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
68  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
69  cfg.snc = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
70  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
71 
77 #define C9DOF2_RETVAL uint8_t
78 
79 #define C9DOF2_OK 0x00
80 #define C9DOF2_INIT_ERROR 0xFF
81 
87 #define C9DOF2_AK09916_ADR 0x0C
88 #define C9DOF2_WHO_AM_I_AK09916 0x01
89 #define C9DOF2_AK09916_ST1 0x10
90 #define C9DOF2_AK09916_XOUT_L 0x11
91 #define C9DOF2_AK09916_XOUT_H 0x12
92 #define C9DOF2_AK09916_YOUT_L 0x13
93 #define C9DOF2_AK09916_YOUT_H 0x14
94 #define C9DOF2_AK09916_ZOUT_L 0x15
95 #define C9DOF2_AK09916_ZOUT_H 0x16
96 #define C9DOF2_AK09916_ST2 0x18
97 #define C9DOF2_AK09916_CNTL 0x30
98 #define C9DOF2_AK09916_CNTL2 0x31
99 
105 #define C9DOF2_WHO_AM_I_ICM20948 0x00
106 #define C9DOF2_USER_CTRL 0x03
107 #define C9DOF2_LP_CCFG 0x05
108 #define C9DOF2_PWR_MGMT_1 0x06
109 #define C9DOF2_PWR_MGMT_2 0x07
110 #define C9DOF2_INT_PIN_CFG 0x0F
111 #define C9DOF2_INT_EN 0x10
112 #define C9DOF2_INT_EN_1 0x11
113 #define C9DOF2_INT_EN_2 0x12
114 #define C9DOF2_INT_EN_3 0x13
115 #define C9DOF2_I2C_MST_STAT 0x17
116 #define C9DOF2_INT_STAT 0x19
117 #define C9DOF2_INT_STAT_1 0x1A
118 #define C9DOF2_INT_STAT_2 0x1B
119 #define C9DOF2_INT_STAT_3 0x1C
120 #define C9DOF2_DELAY_TIMEH 0x28
121 #define C9DOF2_DELAY_TIMEL 0x29
122 #define C9DOF2_ACCEL_XOUT_H 0x2D
123 #define C9DOF2_ACCEL_XOUT_L 0x2E
124 #define C9DOF2_ACCEL_YOUT_H 0x2F
125 #define C9DOF2_ACCEL_YOUT_L 0x30
126 #define C9DOF2_ACCEL_ZOUT_H 0x31
127 #define C9DOF2_ACCEL_ZOUT_L 0x32
128 #define C9DOF2_GYRO_XOUT_H 0x33
129 #define C9DOF2_GYRO_XOUT_L 0x34
130 #define C9DOF2_GYRO_YOUT_H 0x35
131 #define C9DOF2_GYRO_YOUT_L 0x36
132 #define C9DOF2_GYRO_ZOUT_H 0x37
133 #define C9DOF2_GYRO_ZOUT_L 0x38
134 #define C9DOF2_TEMP_OUT_H 0x39
135 #define C9DOF2_TEMP_OUT_L 0x3A
136 #define C9DOF2_EXT_SENS_DATA_00 0x3B
137 #define C9DOF2_EXT_SENS_DATA_01 0x3C
138 #define C9DOF2_EXT_SENS_DATA_02 0x3D
139 #define C9DOF2_EXT_SENS_DATA_03 0x3E
140 #define C9DOF2_EXT_SENS_DATA_04 0x3F
141 #define C9DOF2_EXT_SENS_DATA_05 0x40
142 #define C9DOF2_EXT_SENS_DATA_06 0x41
143 #define C9DOF2_EXT_SENS_DATA_07 0x42
144 #define C9DOF2_EXT_SENS_DATA_08 0x43
145 #define C9DOF2_EXT_SENS_DATA_09 0x44
146 #define C9DOF2_EXT_SENS_DATA_10 0x45
147 #define C9DOF2_EXT_SENS_DATA_11 0x46
148 #define C9DOF2_EXT_SENS_DATA_12 0x47
149 #define C9DOF2_EXT_SENS_DATA_13 0x48
150 #define C9DOF2_EXT_SENS_DATA_14 0x49
151 #define C9DOF2_EXT_SENS_DATA_15 0x4A
152 #define C9DOF2_EXT_SENS_DATA_16 0x4B
153 #define C9DOF2_EXT_SENS_DATA_17 0x4C
154 #define C9DOF2_EXT_SENS_DATA_18 0x4D
155 #define C9DOF2_EXT_SENS_DATA_19 0x4E
156 #define C9DOF2_EXT_SENS_DATA_20 0x4F
157 #define C9DOF2_EXT_SENS_DATA_21 0x50
158 #define C9DOF2_EXT_SENS_DATA_22 0x51
159 #define C9DOF2_EXT_SENS_DATA_23 0x52
160 #define C9DOF2_FIFO_EN_1 0x66
161 #define C9DOF2_FIFO_EN_2 0x67
162 #define C9DOF2_FIFO_RST 0x68
163 #define C9DOF2_FIFO_MODE 0x69
164 #define C9DOF2_FIFO_CNT_H 0x70
165 #define C9DOF2_FIFO_CNT_L 0x71
166 #define C9DOF2_FIFO_R_W 0x72
167 #define C9DOF2_DATA_RDY_STAT 0x74
168 #define C9DOF2_FIFO_CFG 0x76
169 #define C9DOF2_REG_BANK_SEL 0x7F
170 
176 #define C9DOF2_SELF_TEST_X_GYRO 0x02
177 #define C9DOF2_SELF_TEST_Y_GYRO 0x03
178 #define C9DOF2_SELF_TEST_Z_GYRO 0x04
179 #define C9DOF2_SELF_TEST_X_ACCEL 0x0E
180 #define C9DOF2_SELF_TEST_Y_ACCEL 0x0F
181 #define C9DOF2_SELF_TEST_Z_ACCEL 0x10
182 #define C9DOF2_XA_OFFSET_H 0x14
183 #define C9DOF2_XA_OFFSET_L 0x15
184 #define C9DOF2_YA_OFFSET_H 0x17
185 #define C9DOF2_YA_OFFSET_L 0x18
186 #define C9DOF2_ZA_OFFSET_H 0x1A
187 #define C9DOF2_ZA_OFFSET_L 0x1B
188 #define C9DOF2_TIMEBASE_CORREC_PLL 0x28
189 
195 #define C9DOF2_GYRO_SMPLRT_DIV 0x00
196 #define C9DOF2_GYRO_CFG_1 0x01
197 #define C9DOF2_GYRO_CFG_2 0x02
198 #define C9DOF2_XG_OFFSET_H 0x03
199 #define C9DOF2_XG_OFFSET_L 0x04
200 #define C9DOF2_YG_OFFSET_H 0x05
201 #define C9DOF2_YG_OFFSET_L 0x06
202 #define C9DOF2_ZG_OFFSET_H 0x07
203 #define C9DOF2_ZG_OFFSET_L 0x08
204 #define C9DOF2_ODR_ALIGN_EN 0x09
205 #define C9DOF2_ACCEL_SMPLRT_DIV_1 0x10
206 #define C9DOF2_ACCEL_SMPLRT_DIV_2 0x11
207 #define C9DOF2_ACCEL_INTEL_CTRL 0x12
208 #define C9DOF2_ACCEL_WOM_THR 0x13
209 #define C9DOF2_ACCEL_CFG 0x14
210 #define C9DOF2_ACCEL_CFG_2 0x15
211 #define C9DOF2_FSYNC_CFG 0x52
212 #define C9DOF2_TEMP_CFG 0x53
213 #define C9DOF2_MOD_CTRL_USR 0x54
214 
220 #define C9DOF2_I2C_MST_ODR_CFG 0x00
221 #define C9DOF2_I2C_MST_CTRL 0x01
222 #define C9DOF2_I2C_MST_DELAY_CTRL 0x02
223 #define C9DOF2_I2C_SLV0_ADR 0x03
224 #define C9DOF2_I2C_SLV0_REG 0x04
225 #define C9DOF2_I2C_SLV0_CTRL 0x05
226 #define C9DOF2_I2C_SLV0_DO 0x06
227 #define C9DOF2_I2C_SLV1_ADR 0x07
228 #define C9DOF2_I2C_SLV1_REG 0x08
229 #define C9DOF2_I2C_SLV1_CTRL 0x09
230 #define C9DOF2_I2C_SLV1_DO 0x0A
231 #define C9DOF2_I2C_SLV2_ADR 0x0B
232 #define C9DOF2_I2C_SLV2_REG 0x0C
233 #define C9DOF2_I2C_SLV2_CTRL 0x0D
234 #define C9DOF2_I2C_SLV2_DO 0x0E
235 #define C9DOF2_I2C_SLV3_ADR 0x0F
236 #define C9DOF2_I2C_SLV3_REG 0x10
237 #define C9DOF2_I2C_SLV3_CTRL 0x11
238 #define C9DOF2_I2C_SLV3_DO 0x12
239 #define C9DOF2_I2C_SLV4_ADR 0x13
240 #define C9DOF2_I2C_SLV4_REG 0x14
241 #define C9DOF2_I2C_SLV4_CTRL 0x15
242 #define C9DOF2_I2C_SLV4_DO 0x16
243 #define C9DOF2_I2C_SLV4_DI 0x17
244 
250 #define C9DOF2_REG_BANK_0 0x00
251 #define C9DOF2_REG_BANK_1 0x10
252 #define C9DOF2_REG_BANK_2 0x20
253 #define C9DOF2_REG_BANK_3 0x30
254 
260 #define C9DOF2_USER_CTL_DMP_EN 0x80
261 #define C9DOF2_USER_CTL_FIFO_EN 0x40
262 #define C9DOF2_USER_CTL_I2C_MST_EN 0x20
263 #define C9DOF2_USER_CTL_I2C_IF_DIS 0x10
264 #define C9DOF2_USER_CTL_DMP_RST 0x08
265 #define C9DOF2_USER_CTL_SRAM_RST 0x04
266 #define C9DOF2_USER_CTL_I2C_MST_RST 0x02
267 
273 #define C9DOF2_LP_CFG_I2C_MST_CYC 0x80
274 #define C9DOF2_LP_CFG_ACCEL_CYC 0x40
275 #define C9DOF2_LP_CFG_GYRO_CYC 0x20
276 
282 #define C9DOF2_PWR_MGMT_1_DEV_RST 0x80
283 #define C9DOF2_PWR_MGMT_1_SLP 0x40
284 #define C9DOF2_PWR_MGMT_1_LP_EN 0x20
285 #define C9DOF2_PWR_MGMT_1_TEMP_DIS 0x08
286 #define C9DOF2_PWR_MGMT_1_CLKSEL_7 0x07
287 #define C9DOF2_PWR_MGMT_1_CLKSEL_6 0x06
288 #define C9DOF2_PWR_MGMT_1_CLKSEL_5 0x05
289 #define C9DOF2_PWR_MGMT_1_CLKSEL_4 0x04
290 #define C9DOF2_PWR_MGMT_1_CLKSEL_3 0x03
291 #define C9DOF2_PWR_MGMT_1_CLKSEL_2 0x02
292 #define C9DOF2_PWR_MGMT_1_CLKSEL_1 0x01
293 #define C9DOF2_PWR_MGMT_1_CLKSEL_0 0x00
294 
300 #define C9DOF2_PWR_MGMT_2_DIS_XA 0x20
301 #define C9DOF2_PWR_MGMT_2_DIS_YA 0x10
302 #define C9DOF2_PWR_MGMT_2_DIS_ZA 0x08
303 #define C9DOF2_PWR_MGMT_2_DIS_XG 0x04
304 #define C9DOF2_PWR_MGMT_2_DIS_YG 0x02
305 #define C9DOF2_PWR_MGMT_2_DIS_ZG 0x01
306 
312 #define C9DOF2_INT_PIN_CFG_ACTL 0x80
313 #define C9DOF2_INT_PIN_CFG_OPEN 0x40
314 #define C9DOF2_INT_PIN_CFG_LATCH_INT_EN 0x20
315 #define C9DOF2_INT_PIN_CFG_INT_ANYRD_2CLR 0x10
316 #define C9DOF2_INT_PIN_CFG_ACTL_FSYNC 0x08
317 #define C9DOF2_INT_PIN_CFG_FSYNC_INT_MODE_EN 0x04
318 #define C9DOF2_INT_PIN_CFG_BYPASS_EN 0x02
319 
325 #define C9DOF2_INT_ENABLE_REG_WOF_EN 0x80
326 #define C9DOF2_INT_ENABLE_WOM_INT_EN 0x08
327 #define C9DOF2_INT_ENABLE_PLL_RDY_EN 0x04
328 #define C9DOF2_INT_ENABLE_FIFO_OVF_EN 0x10
329 #define C9DOF2_INT_ENABLE_DMP_INT1_EN 0x04
330 #define C9DOF2_INT_ENABLE_I2C_MST_INT_EN 0x01
331 
337 #define C9DOF2_INT_EN_1_RAW_DATA_0_RDY_EN 0x01
338 
344 #define C9DOF2_INT_EN_2_FIFO_OVERFLOW_EN 0x1F
345 
351 #define C9DOF2_INT_ENABLE_3_FIFO_WM_EN 0x1F
352 
358 #define C9DOF2_I2C_MST_STAT_PASS_THROUGH 0x80
359 #define C9DOF2_I2C_MST_STAT_I2C_SLV4_DONE 0x40
360 #define C9DOF2_I2C_MST_STAT_I2C_LOST_ARB 0x20
361 #define C9DOF2_I2C_MST_STAT_I2C_SLV4_NACK 0x10
362 #define C9DOF2_I2C_MST_STAT_I2C_SLV3_NACK 0x08
363 #define C9DOF2_I2C_MST_STAT_I2C_SLV2_NACK 0x04
364 #define C9DOF2_I2C_MST_STAT_I2C_SLV1_NACK 0x02
365 #define C9DOF2_I2C_MST_STAT_I2C_SLV0_NACK 0x01
366 
372 #define C9DOF2_INT_STAT_WOM_INT 0x80
373 #define C9DOF2_INT_STAT_PLL_RDY_INT 0x40
374 #define C9DOF2_INT_STAT_DMP_INT1 0x20
375 #define C9DOF2_INT_STAT_I2C_MST_INT 0x10
376 
382 #define C9DOF2_INT_STAT_1_RAW_DATA_0_RDY_EN 0x01
383 
389 #define C9DOF2_INT_STAT_2_FIFO_OWF_EN 0x1F
390 
396 #define C9DOF2_INT_STAT_3_FIFO_WM_EN 0x1F
397 
403 #define C9DOF2_FIFO_EN_1_SLV_3_FIFO_EN 0x08
404 #define C9DOF2_FIFO_EN_1_SLV_2_FIFO_EN 0x04
405 #define C9DOF2_FIFO_EN_1_SLV_1_FIFO_EN 0x02
406 #define C9DOF2_FIFO_EN_1_SLV_0_FIFO_EN 0x01
407 
413 #define C9DOF2_FIFO_EN_2_ACCEL_FIFO_EN 0x10
414 #define C9DOF2_FIFO_EN_2_GYRO_Z_FIFO_EN 0x08
415 #define C9DOF2_FIFO_EN_2_GYRO_Y_FIFO_EN 0x04
416 #define C9DOF2_FIFO_EN_2_GYRO_X_FIFO_EN 0x02
417 #define C9DOF2_FIFO_EN_2_TEMP_FIFO_EN 0x01
418 
424 #define C9DOF2_FIFO_CFG_CMD 0x01
425 
431 #define C9DOF2_GYRO_CFG_1_DLPFCFG_7 0x38
432 #define C9DOF2_GYRO_CFG_1_DLPFCFG_6 0x30
433 #define C9DOF2_GYRO_CFG_1_DLPFCFG_5 0x28
434 #define C9DOF2_GYRO_CFG_1_DLPFCFG_4 0x20
435 #define C9DOF2_GYRO_CFG_1_DLPFCFG_3 0x18
436 #define C9DOF2_GYRO_CFG_1_DLPFCFG_2 0x10
437 #define C9DOF2_GYRO_CFG_1_DLPFCFG_1 0x08
438 #define C9DOF2_GYRO_CFG_1_DLPFCFG_0 0x00
439 #define C9DOF2_GYRO_CFG_1_FS_SEL_2000 0x06
440 #define C9DOF2_GYRO_CFG_1_FS_SEL_1000 0x04
441 #define C9DOF2_GYRO_CFG_1_FS_SEL_500 0x02
442 #define C9DOF2_GYRO_CFG_1_FS_SEL_250 0x00
443 #define C9DOF2_GYRO_CFG_1_FCHOICE_EN 0x01
444 #define C9DOF2_GYRO_CFG_1_FCHOICE_BP 0x00
445 
451 #define C9DOF2_GYRO_CFG_2_XGYRO_CTEN 0x20
452 #define C9DOF2_GYRO_CFG_2_YGYRO_CTEN 0x10
453 #define C9DOF2_GYRO_CFG_2_ZGYRO_CTEN 0x08
454 #define C9DOF2_GYRO_CFG_2_AVGCFG_7 0x07
455 #define C9DOF2_GYRO_CFG_2_AVGCFG_6 0x06
456 #define C9DOF2_GYRO_CFG_2_AVGCFG_5 0x05
457 #define C9DOF2_GYRO_CFG_2_AVGCFG_4 0x04
458 #define C9DOF2_GYRO_CFG_2_AVGCFG_3 0x03
459 #define C9DOF2_GYRO_CFG_2_AVGCFG_2 0x02
460 #define C9DOF2_GYRO_CFG_2_AVGCFG_1 0x01
461 #define C9DOF2_GYRO_CFG_2_AVGCFG_0 0x00
462 
468 #define C9DOF2_ODR_ALIGN_CMD_EN 0x01
469 #define C9DOF2_ODR_ALIGN_CMD_DIS 0x00
470 
476 #define C9DOF2_ACCEL_INTEL_CTL_INTEL_EN 0x02
477 #define C9DOF2_ACCEL_INTEL_CTL_INTEL_MODE_INT_CURR 0x01
478 #define C9DOF2_ACCEL_INTEL_CTL_INTEL_MODE_INT_INIT 0x00
479 
485 #define C9DOF2_ACCEL_CFG_DLPFCFG_7 0x38
486 #define C9DOF2_ACCEL_CFG_DLPFCFG_6 0x30
487 #define C9DOF2_ACCEL_CFG_DLPFCFG_5 0x28
488 #define C9DOF2_ACCEL_CFG_DLPFCFG_4 0x20
489 #define C9DOF2_ACCEL_CFG_DLPFCFG_3 0x18
490 #define C9DOF2_ACCEL_CFG_DLPFCFG_2 0x10
491 #define C9DOF2_ACCEL_CFG_DLPFCFG_1 0x08
492 #define C9DOF2_ACCEL_CFG_DLPFCFG_0 0x00
493 #define C9DOF2_ACCEL_CFG_FS_SEL_16G 0x06
494 #define C9DOF2_ACCEL_CFG_FS_SEL_8G 0x04
495 #define C9DOF2_ACCEL_CFG_FS_SEL_4G 0x02
496 #define C9DOF2_ACCEL_CFG_FS_SEL_2G 0x00
497 #define C9DOF2_ACCEL_CFG_FCHOICE_EN 0x01
498 #define C9DOF2_ACCEL_CFG_FCHOICE_BP 0x00
499 
505 #define C9DOF2_ACCEL_2_CFG_AX_ST_EN_REG 0x10
506 #define C9DOF2_ACCEL_2_CFG_AY_ST_EN_REG 0x08
507 #define C9DOF2_ACCEL_2_CFG_AZ_ST_EN_REG 0x04
508 #define C9DOF2_ACCEL_2_CFG_DEC3_CFG_32 0x03
509 #define C9DOF2_ACCEL_2_CFG_DEC3_CFG_16 0x02
510 #define C9DOF2_ACCEL_2_CFG_DEC3_CFG_8 0x01
511 #define C9DOF2_ACCEL_2_CFG_DEC3_CFG_4 0x00
512 #define C9DOF2_ACCEL_2_CFG_DEC3_CFG_1 0x00
513 
519 #define C9DOF2_FSYNC_CFG_DELAY_TIME_EN 0x80
520 #define C9DOF2_FSYNC_CFG_WOF_DEGLITCH_EN 0x40
521 #define C9DOF2_FSYNC_CFG_WOF_EDGE_INT 0x20
522 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_ACCEL_ZOUT_L 0x07
523 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_ACCEL_YOUT_L 0x06
524 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_ACCEL_XOUT_L 0x05
525 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_GYRO_ZOUT_L 0x04
526 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_GYRO_YOUT_L 0x03
527 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_GYRO_XOUT_L 0x02
528 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_TEMP_OUT_L 0x01
529 #define C9DOF2_FSYNC_CFG_EXT_SYNC_SET_DIS 0x00
530 
536 #define C9DOF2_TEMP_CFG_DLPFCFG_7 0x07
537 #define C9DOF2_TEMP_CFG_DLPFCFG_6 0x06
538 #define C9DOF2_TEMP_CFG_DLPFCFG_5 0x05
539 #define C9DOF2_TEMP_CFG_DLPFCFG_4 0x04
540 #define C9DOF2_TEMP_CFG_DLPFCFG_3 0x03
541 #define C9DOF2_TEMP_CFG_DLPFCFG_2 0x02
542 #define C9DOF2_TEMP_CFG_DLPFCFG_1 0x01
543 #define C9DOF2_TEMP_CFG_DLPFCFG_0 0x00
544 
550 #define C9DOF2_MOD_CTRL_USR_REG_LP_DMP_EN 0x01
551 #define C9DOF2_MOD_CTRL_USR_REG_LP_DMP_DIS 0x00
552 
558 #define C9DOF2_CNTL2_MODE_SELF_TEST 0x10
559 #define C9DOF2_CNTL2_MODE_CONT_MEAS_4 0x08
560 #define C9DOF2_CNTL2_MODE_CONT_MEAS_3 0x06
561 #define C9DOF2_CNTL2_MODE_CONT_MEAS_2 0x04
562 #define C9DOF2_CNTL2_MODE_CONT_MEAS_1 0x02
563 #define C9DOF2_CNTL2_MODE_ONE_SHOT 0x01
564 #define C9DOF2_CNTL2_MODE_POW_DOWN 0x00
565 
571 #define C9DOF2_CNTL3_SOFT_RST 0x01
572 
578 #define C9DOF2_WHO_AM_I_ICM20948_VAL 0xEA
579 
585 #define C9DOF2_GYRO_SENS_FS_SEL_2000 16.4
586 #define C9DOF2_GYRO_SENS_FS_SEL_1000 32.8
587 #define C9DOF2_GYRO_SENS_FS_SEL_500 65.5
588 #define C9DOF2_GYRO_SENS_FS_SEL_250 131.0
589 #define C9DOF2_ACCEL_SENS_FS_SEL_16G 2048.0
590 #define C9DOF2_ACCEL_SENS_FS_SEL_8G 4096.0
591 #define C9DOF2_ACCEL_SENS_FS_SEL_4G 8192.0
592 #define C9DOF2_ACCEL_SENS_FS_SEL_2G 16384.0
593 
599 #define C9DOF2_POWER_ON 0x01
600 #define C9DOF2_POWER_OFF 0x00
601 
607 #define C9DOF2_SNC_LOW 0x00
608 #define C9DOF2_SNC_HIGH 0x01
609 
615 #define C9DOF2_READ_BIT_MASK 0x80
616 #define C9DOF2_WRITE_BIT_MASK 0x7F
617  // End group macro
619 // --------------------------------------------------------------- PUBLIC TYPES
628 typedef struct
629 {
630  // Output pins
631 
632  digital_out_t snc;
633  digital_out_t cs;
634 
635  // Input pins
636 
637  digital_in_t int_pin;
638 
639  // Modules
640 
641  spi_master_t spi;
642  pin_name_t chip_select;
643 
644 } c9dof2_t;
645 
649 typedef struct
650 {
651  // Communication gpio pins
652 
653  pin_name_t miso;
654  pin_name_t mosi;
655  pin_name_t sck;
656  pin_name_t cs;
657 
658  // Additional gpio pins
659 
660  pin_name_t snc;
661  pin_name_t int_pin;
662 
663  // static variable
664 
665  uint32_t spi_speed;
666  spi_master_mode_t spi_mode;
667  spi_master_chip_select_polarity_t cs_polarity;
668 
669 } c9dof2_cfg_t;
670  // End types group
672 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
673 
678 #ifdef __cplusplus
679 extern "C"{
680 #endif
681 
691 
700 
711 void c9dof2_write_byte ( c9dof2_t *ctx, uint8_t reg, uint8_t wr_data );
712 
723 void c9dof2_write_data ( c9dof2_t *ctx, uint8_t reg, int16_t wr_data );
724 
736 uint8_t c9dof2_read_byte ( c9dof2_t *ctx, uint8_t reg );
737 
749 int16_t c9dof2_read_data ( c9dof2_t *ctx, uint8_t reg );
750 
758 void c9dof2_dev_rst ( c9dof2_t *ctx );
759 
769 void c9dof2_power ( c9dof2_t *ctx, uint8_t on_off );
770 
780 
791 void c9dof2_read_gyroscope ( c9dof2_t *ctx, int16_t *gyro_x, int16_t *gyro_y, int16_t *gyro_z );
792 
803 void c9dof2_angular_rate ( c9dof2_t *ctx, float *x_ang_rte, float *y_ang_rte, float *z_ang_rte );
804 
815 void c9dof2_read_accelerometer ( c9dof2_t *ctx, int16_t *accel_x, int16_t *accel_y, int16_t *accel_z );
816 
827 void c9dof2_acceleration_rate ( c9dof2_t *ctx, float *x_accel_rte, float *y_accel_rte, float *z_accel_rte );
828 
839 float c9dof2_read_temperature ( c9dof2_t *ctx, float temp_offs );
840 
854 uint8_t c9dof2_check_int ( c9dof2_t *ctx );
855 
864 void c9dof2_snc_pin ( c9dof2_t *ctx, uint8_t state );
865 
866 #ifdef __cplusplus
867 }
868 #endif
869 #endif // _C9DOF2_H_
870  // End public_function group
873 
874 // ------------------------------------------------------------------------- END
c9dof2_cfg_t
Click configuration structure definition.
Definition: c9dof2.h:650
c9dof2_cfg_setup
void c9dof2_cfg_setup(c9dof2_cfg_t *cfg)
Config Object Initialization function.
c9dof2_write_data
void c9dof2_write_data(c9dof2_t *ctx, uint8_t reg, int16_t wr_data)
Write Data function.
c9dof2_read_accelerometer
void c9dof2_read_accelerometer(c9dof2_t *ctx, int16_t *accel_x, int16_t *accel_y, int16_t *accel_z)
Read accelerometer data function.
c9dof2_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: c9dof2.h:667
c9dof2_snc_pin
void c9dof2_snc_pin(c9dof2_t *ctx, uint8_t state)
FSYNC Pin State function.
c9dof2_read_byte
uint8_t c9dof2_read_byte(c9dof2_t *ctx, uint8_t reg)
Read Byte function.
c9dof2_t::int_pin
digital_in_t int_pin
Definition: c9dof2.h:637
c9dof2_check_int
uint8_t c9dof2_check_int(c9dof2_t *ctx)
Check Interrupt state function.
c9dof2_write_byte
void c9dof2_write_byte(c9dof2_t *ctx, uint8_t reg, uint8_t wr_data)
Write Byte function.
c9dof2_t::spi
spi_master_t spi
Definition: c9dof2.h:641
c9dof2_acceleration_rate
void c9dof2_acceleration_rate(c9dof2_t *ctx, float *x_accel_rte, float *y_accel_rte, float *z_accel_rte)
Read acceleration Rate function.
c9dof2_power
void c9dof2_power(c9dof2_t *ctx, uint8_t on_off)
Power up function.
c9dof2_init
C9DOF2_RETVAL c9dof2_init(c9dof2_t *ctx, c9dof2_cfg_t *cfg)
Initialization function.
c9dof2_t::chip_select
pin_name_t chip_select
Definition: c9dof2.h:642
c9dof2_read_gyroscope
void c9dof2_read_gyroscope(c9dof2_t *ctx, int16_t *gyro_x, int16_t *gyro_y, int16_t *gyro_z)
Read gyroscope data function.
c9dof2_t
Click ctx object definition.
Definition: c9dof2.h:629
C9DOF2_RETVAL
#define C9DOF2_RETVAL
Definition: c9dof2.h:77
c9dof2_cfg_t::miso
pin_name_t miso
Definition: c9dof2.h:653
c9dof2_dev_rst
void c9dof2_dev_rst(c9dof2_t *ctx)
Device Reset function.
c9dof2_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: c9dof2.h:666
c9dof2_def_settings
void c9dof2_def_settings(c9dof2_t *ctx)
Default settings function.
c9dof2_cfg_t::mosi
pin_name_t mosi
Definition: c9dof2.h:654
c9dof2_angular_rate
void c9dof2_angular_rate(c9dof2_t *ctx, float *x_ang_rte, float *y_ang_rte, float *z_ang_rte)
Read Angular Rate function.
c9dof2_cfg_t::int_pin
pin_name_t int_pin
Definition: c9dof2.h:661
c9dof2_t::cs
digital_out_t cs
Definition: c9dof2.h:633
c9dof2_read_data
int16_t c9dof2_read_data(c9dof2_t *ctx, uint8_t reg)
Read Data function.
c9dof2_cfg_t::sck
pin_name_t sck
Definition: c9dof2.h:655
c9dof2_cfg_t::snc
pin_name_t snc
Definition: c9dof2.h:660
c9dof2_t::snc
digital_out_t snc
Definition: c9dof2.h:632
c9dof2_read_temperature
float c9dof2_read_temperature(c9dof2_t *ctx, float temp_offs)
Read temperture function.
c9dof2_cfg_t::cs
pin_name_t cs
Definition: c9dof2.h:656
c9dof2_cfg_t::spi_speed
uint32_t spi_speed
Definition: c9dof2.h:665