ism  2.0.0.0
ism.h
Go to the documentation of this file.
1 /****************************************************************************
2 ** Copyright (C) 2020 MikroElektronika d.o.o.
3 ** Contact: https://www.mikroe.com/contact
4 **
5 ** Permission is hereby granted, free of charge, to any person obtaining a copy
6 ** of this software and associated documentation files (the "Software"), to deal
7 ** in the Software without restriction, including without limitation the rights
8 ** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 ** copies of the Software, and to permit persons to whom the Software is
10 ** furnished to do so, subject to the following conditions:
11 ** The above copyright notice and this permission notice shall be
12 ** included in all copies or substantial portions of the Software.
13 **
14 ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 ** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 ** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17 ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
18 ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
19 ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 ** USE OR OTHER DEALINGS IN THE SOFTWARE.
21 ****************************************************************************/
22 
28 #ifndef ISM_H
29 #define ISM_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
39 #ifdef PREINIT_SUPPORTED
40 #include "preinit.h"
41 #endif
42 
43 #ifdef MikroCCoreVersion
44  #if MikroCCoreVersion >= 1
45  #include "delays.h"
46  #endif
47 #endif
48 
49 #include "drv_digital_out.h"
50 #include "drv_digital_in.h"
51 #include "drv_spi_master.h"
52 
73 #define ISM_REG_BANK_0_CONFIG 0x00
74 #define ISM_REG_BANK_0_EN_AA 0x01
75 #define ISM_REG_BANK_0_EN_RXADDR 0x02
76 #define ISM_REG_BANK_0_SETUP_AW 0x03
77 #define ISM_REG_BANK_0_SETUP_RETR 0x04
78 #define ISM_REG_BANK_0_RF_CH 0x05
79 #define ISM_REG_BANK_0_RF_SETUP 0x06
80 #define ISM_REG_BANK_0_STATUS 0x07
81 #define ISM_REG_BANK_0_OBSERVE_TX 0x08
82 #define ISM_REG_BANK_0_CD 0x09
83 #define ISM_REG_BANK_0_RX_ADDR_P0 0x0A
84 #define ISM_REG_BANK_0_RX_ADDR_P1 0x0B
85 #define ISM_REG_BANK_0_RX_ADDR_P2 0x0C
86 #define ISM_REG_BANK_0_RX_ADDR_P3 0x0D
87 #define ISM_REG_BANK_0_RX_ADDR_P4 0x0E
88 #define ISM_REG_BANK_0_RX_ADDR_P5 0x0F
89 #define ISM_REG_BANK_0_TX_ADDR 0x10
90 #define ISM_REG_BANK_0_RX_PW_P0 0x11
91 #define ISM_REG_BANK_0_RX_PW_P1 0x12
92 #define ISM_REG_BANK_0_RX_PW_P2 0x13
93 #define ISM_REG_BANK_0_RX_PW_P3 0x14
94 #define ISM_REG_BANK_0_RX_PW_P4 0x15
95 #define ISM_REG_BANK_0_RX_PW_P5 0x16
96 #define ISM_REG_BANK_0_FIFO_STATUS 0x17
97 #define ISM_REG_BANK_0_PAYLOAD_WIDTH 0x1F
98 #define ISM_REG_BANK_1_REG_0 0x00
99 #define ISM_REG_BANK_1_REG_1 0x01
100 #define ISM_REG_BANK_1_REG_2 0x02
101 #define ISM_REG_BANK_1_REG_3 0x03
102 #define ISM_REG_BANK_1_REG_4 0x04
103 #define ISM_REG_BANK_1_REG_5 0x05
104 #define ISM_REG_BANK_1_REG_6 0x06
105 #define ISM_REG_BANK_1_REG_7 0x07
106 #define ISM_REG_BANK_1_REG_8 0x08
107 #define ISM_REG_BANK_1_REG_9 0x09
108 #define ISM_REG_BANK_1_REG_A 0x0A
109 #define ISM_REG_BANK_1_REG_B 0x0B
110 #define ISM_REG_BANK_1_REG_C 0x0C
111 #define ISM_REG_BANK_1_REG_D 0x0D
112 #define ISM_REG_BANK_1_REG_E 0x0E
113  // ism_reg
115 
125 #define ISM_CMD_FLUSH_TX 0xE1
126 #define ISM_CMD_FLUSH_RX 0xE2
127 #define ISM_CMD_REUSE_TX_PL 0xE3
128 #define ISM_CMD_W_TX_PAYLOAD_NOACK 0xB0
129 #define ISM_CMD_W_ACK_PAYLOAD 0xA8
130 #define ISM_CMD_ACTIVATE 0x50
131 #define ISM_CMD_R_RX_PL_WID 0x60
132 #define ISM_CMD_NOP_NOP 0xFF
133  // ism_cmd
135 
150 #define ISM_STATUS_RX_DR 0x40
151 #define ISM_STATUS_TX_DS 0x20
152 #define ISM_STATUS_MAX_RT 0x10
153 #define STATUS_TX_FULL 0x01
154 #define ISM_FIFO_STATUS_TX_REUSE 0x40
155 #define ISM_FIFO_STATUS_TX_FULL 0x20
156 #define ISM_FIFO_STATUS_TX_EMPTY 0x10
157 #define ISM_FIFO_STATUS_RX_FULL 0x02
158 #define ISM_FIFO_STATUS_RX_EMPTY 0x01
159 
164 #define ISM_SEL_BANK_0 0
165 #define ISM_SEL_BANK_1 1
166 
171 #define ISM_MAX_PACKET_LEN 32
172 
177 #define ISM_RT_PIN_STATE_LOW 0
178 #define ISM_RT_PIN_STATE_HIGH 1
179 
184 #define ISM_RD_RX_PLOAD 0x61
185 #define ISM_WR_TX_PLOAD 0xA0
186 
191 #define ISM_READ_BIT_MASK 0x00
192 #define ISM_WRITE_BIT_MASK 0x20
193  // ism_set
195 
210 #define ISM_MAP_MIKROBUS( cfg, mikrobus ) \
211  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
212  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
213  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
214  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
215  cfg.tl = MIKROBUS( mikrobus, MIKROBUS_AN ); \
216  cfg.ce = MIKROBUS( mikrobus, MIKROBUS_RST ); \
217  cfg.rl = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
218  cfg.irq = MIKROBUS( mikrobus, MIKROBUS_INT )
219  // ism_map // ism
222 
227 typedef struct
228 {
229  // Output pins
230  digital_out_t tl;
231  digital_out_t ce;
232  digital_out_t rl;
234  // Input pins
235  digital_in_t irq;
237  // Modules
238  spi_master_t spi;
240  pin_name_t chip_select;
242 } ism_t;
243 
248 typedef struct
249 {
250  // Communication gpio pins
251  pin_name_t miso;
252  pin_name_t mosi;
253  pin_name_t sck;
254  pin_name_t cs;
256  // Additional gpio pins
257  pin_name_t tl;
258  pin_name_t ce;
259  pin_name_t rl;
260  pin_name_t irq;
262  // static variable
263  uint32_t spi_speed;
264  spi_master_mode_t spi_mode;
265  spi_master_chip_select_polarity_t cs_polarity;
267 } ism_cfg_t;
268 
273 typedef enum
274 {
275  ISM_OK = 0,
276  ISM_ERROR = -1
277 
279 
295 void ism_cfg_setup ( ism_cfg_t *cfg );
296 
310 err_t ism_init ( ism_t *ctx, ism_cfg_t *cfg );
311 
321 void ism_default_cfg ( ism_t *ctx );
322 
337 err_t ism_generic_write ( ism_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
338 
353 err_t ism_generic_read ( ism_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
354 
367 err_t ism_set_cmd ( ism_t *ctx, uint8_t cmd, uint8_t cmd_data );
368 
379 void ism_chip_enable ( ism_t *ctx );
380 
391 void ism_chip_disable ( ism_t *ctx );
392 
406 void ism_set_rl_pin_state ( ism_t *ctx, uint8_t rt_pin_state );
407 
421 void ism_set_tl_pin_state ( ism_t *ctx, uint8_t tl_pin_state );
422 
435 
451 err_t ism_switch_bank ( ism_t *ctx, uint8_t bank_sel );
452 
465 err_t ism_switch_rx_mode ( ism_t *ctx );
466 
479 err_t ism_switch_tx_mode ( ism_t *ctx );
480 
493 err_t ism_device_config ( ism_t *ctx );
494 
508 err_t ism_receive_packet ( ism_t *ctx, uint8_t *rx_data );
509 
525 err_t ism_transmit_packet ( ism_t *ctx, uint8_t type, uint8_t *tx_data, uint8_t len );
526 
527 #ifdef __cplusplus
528 }
529 #endif
530 #endif // ISM_H
531  // ism
533 
534 // ------------------------------------------------------------------------ END
ism_generic_read
err_t ism_generic_read(ism_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
ISM data reading function.
ism_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: ism.h:264
ism_t::ce
digital_out_t ce
Definition: ism.h:231
ism_cfg_t::rl
pin_name_t rl
Definition: ism.h:259
ism_t::tl
digital_out_t tl
Definition: ism.h:230
ism_t::rl
digital_out_t rl
Definition: ism.h:232
ism_set_tl_pin_state
void ism_set_tl_pin_state(ism_t *ctx, uint8_t tl_pin_state)
ISM TL pin setting function.
ism_switch_rx_mode
err_t ism_switch_rx_mode(ism_t *ctx)
ISM switch RX mode function.
ism_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: ism.h:265
ism_cfg_setup
void ism_cfg_setup(ism_cfg_t *cfg)
ISM configuration object setup function.
ism_default_cfg
void ism_default_cfg(ism_t *ctx)
ISM default configuration function.
ism_generic_write
err_t ism_generic_write(ism_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
ISM data writing function.
ISM_ERROR
@ ISM_ERROR
Definition: ism.h:276
ism_check_interrupt_request
uint8_t ism_check_interrupt_request(ism_t *ctx)
ISM check interrupt request function.
ism_t
ISM Click context object.
Definition: ism.h:228
ISM_OK
@ ISM_OK
Definition: ism.h:275
ism_cfg_t::spi_speed
uint32_t spi_speed
Definition: ism.h:263
ism_switch_tx_mode
err_t ism_switch_tx_mode(ism_t *ctx)
ISM switch TX mode function.
ism_set_cmd
err_t ism_set_cmd(ism_t *ctx, uint8_t cmd, uint8_t cmd_data)
ISM set command function.
ism_switch_bank
err_t ism_switch_bank(ism_t *ctx, uint8_t bank_sel)
ISM switch bank function.
ism_receive_packet
err_t ism_receive_packet(ism_t *ctx, uint8_t *rx_data)
ISM receive packet function.
ism_cfg_t::mosi
pin_name_t mosi
Definition: ism.h:252
ism_cfg_t::tl
pin_name_t tl
Definition: ism.h:257
ism_cfg_t::irq
pin_name_t irq
Definition: ism.h:260
ism_cfg_t::miso
pin_name_t miso
Definition: ism.h:251
ism_t::spi
spi_master_t spi
Definition: ism.h:238
ism_chip_enable
void ism_chip_enable(ism_t *ctx)
ISM set chip enable function.
ism_t::chip_select
pin_name_t chip_select
Definition: ism.h:240
ism_device_config
err_t ism_device_config(ism_t *ctx)
ISM device configuration function.
ism_cfg_t::cs
pin_name_t cs
Definition: ism.h:254
ism_t::irq
digital_in_t irq
Definition: ism.h:235
ism_set_rl_pin_state
void ism_set_rl_pin_state(ism_t *ctx, uint8_t rt_pin_state)
ISM RL pin setting function.
ism_chip_disable
void ism_chip_disable(ism_t *ctx)
ISM set chip disable function.
ism_cfg_t
ISM Click configuration object.
Definition: ism.h:249
ism_init
err_t ism_init(ism_t *ctx, ism_cfg_t *cfg)
ISM initialization function.
ism_cfg_t::sck
pin_name_t sck
Definition: ism.h:253
ism_cfg_t::ce
pin_name_t ce
Definition: ism.h:258
ism_transmit_packet
err_t ism_transmit_packet(ism_t *ctx, uint8_t type, uint8_t *tx_data, uint8_t len)
ISM transmit package function.
ism_return_value_t
ism_return_value_t
ISM Click return value data.
Definition: ism.h:274