ccrf2  2.0.0.0
ccrf2.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef CCRF2_H
36 #define CCRF2_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_spi_master.h"
41 
42 // -------------------------------------------------------------- PUBLIC MACROS
53 #define CCRF2_MAP_MIKROBUS( cfg, mikrobus ) \
54  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
55  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
56  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
57  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
58  cfg.gp0 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
59  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
60  cfg.gp2 = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
61  cfg.gp3 = MIKROBUS( mikrobus, MIKROBUS_INT )
62 
68 #define CCRF2_RETVAL uint8_t
69 
70 #define CCRF2_OK 0x00
71 #define CCRF2_INIT_ERROR 0xFF
72 
78 #define CCRF2_STATUS_T uint8_t
79 
85 #define CCRF2_IOCFG3 0x0000
86 #define CCRF2_IOCFG2 0x0001
87 #define CCRF2_IOCFG1 0x0002
88 #define CCRF2_IOCFG0 0x0003
89 #define CCRF2_SYNC3 0x0004
90 #define CCRF2_SYNC2 0x0005
91 #define CCRF2_SYNC1 0x0006
92 #define CCRF2_SYNC0 0x0007
93 #define CCRF2_SYNC_CFG1 0x0008
94 #define CCRF2_SYNC_CFG0 0x0009
95 #define CCRF2_DEVIATION_M 0x000A
96 #define CCRF2_MODCFG_DEV_E 0x000B
97 #define CCRF2_DCFILT_CFG 0x000C
98 #define CCRF2_PREAMBLE_CFG1 0x000D
99 #define CCRF2_PREAMBLE_CFG0 0x000E
100 #define CCRF2_FREQ_IF_CFG 0x000F
101 #define CCRF2_IQIC 0x0010
102 #define CCRF2_CHAN_BW 0x0011
103 #define CCRF2_MDMCFG1 0x0012
104 #define CCRF2_MDMCFG0 0x0013
105 #define CCRF2_SYMBOL_RATE2 0x0014
106 #define CCRF2_SYMBOL_RATE1 0x0015
107 #define CCRF2_SYMBOL_RATE0 0x0016
108 #define CCRF2_AGC_REF 0x0017
109 #define CCRF2_AGC_CS_THR 0x0018
110 #define CCRF2_AGC_GAIN_ADJUST 0x0019
111 #define CCRF2_AGC_CFG3 0x001A
112 #define CCRF2_AGC_CFG2 0x001B
113 #define CCRF2_AGC_CFG1 0x001C
114 #define CCRF2_AGC_CFG0 0x001D
115 #define CCRF2_FIFO_CFG 0x001E
116 #define CCRF2_DEV_ADDR 0x001F
117 #define CCRF2_SETTLING_CFG 0x0020
118 #define CCRF2_FS_CFG 0x0021
119 #define CCRF2_WOR_CFG1 0x0022
120 #define CCRF2_WOR_CFG0 0x0023
121 #define CCRF2_WOR_EVENT0_MSB 0x0024
122 #define CCRF2_WOR_EVENT0_LSB 0x0025
123 #define CCRF2_PKT_CFG2 0x0026
124 #define CCRF2_PKT_CFG1 0x0027
125 #define CCRF2_PKT_CFG0 0x0028
126 #define CCRF2_RFEND_CFG1 0x0029
127 #define CCRF2_RFEND_CFG0 0x002A
128 #define CCRF2_PA_CFG2 0x002B
129 #define CCRF2_PA_CFG1 0x002C
130 #define CCRF2_PA_CFG0 0x002D
131 #define CCRF2_PKT_LEN 0x002E
132 
138 #define CCRF2_IF_MIX_CFG 0x2F00
139 #define CCRF2_FREQOFF_CFG 0x2F01
140 #define CCRF2_TOC_CFG 0x2F02
141 #define CCRF2_MARC_SPARE 0x2F03
142 #define CCRF2_ECG_CFG 0x2F04
143 #define CCRF2_CFM_DATA_CFG 0x2F05
144 #define CCRF2_EXT_CTRL 0x2F06
145 #define CCRF2_RCCAL_FINE 0x2F07
146 #define CCRF2_RCCAL_COARSE 0x2F08
147 #define CCRF2_RCCAL_OFFSET 0x2F09
148 #define CCRF2_FREQOFF1 0x2F0A
149 #define CCRF2_FREQOFF0 0x2F0B
150 #define CCRF2_FREQ2 0x2F0C
151 #define CCRF2_FREQ1 0x2F0D
152 #define CCRF2_FREQ0 0x2F0E
153 #define CCRF2_IF_ADC2 0x2F0F
154 #define CCRF2_IF_ADC1 0x2F10
155 #define CCRF2_IF_ADC0 0x2F11
156 #define CCRF2_FS_DIG1 0x2F12
157 #define CCRF2_FS_DIG0 0x2F13
158 #define CCRF2_FS_CAL3 0x2F14
159 #define CCRF2_FS_CAL2 0x2F15
160 #define CCRF2_FS_CAL1 0x2F16
161 #define CCRF2_FS_CAL0 0x2F17
162 #define CCRF2_FS_CHP 0x2F18
163 #define CCRF2_FS_DIVTWO 0x2F19
164 #define CCRF2_FS_DSM1 0x2F1A
165 #define CCRF2_FS_DSM0 0x2F1B
166 #define CCRF2_FS_DVC1 0x2F1C
167 #define CCRF2_FS_DVC0 0x2F1D
168 #define CCRF2_FS_LBI 0x2F1E
169 #define CCRF2_FS_PFD 0x2F1F
170 #define CCRF2_FS_PRE 0x2F20
171 #define CCRF2_FS_REG_DIV_CML 0x2F21
172 #define CCRF2_FS_SPARE 0x2F22
173 #define CCRF2_FS_VCO4 0x2F23
174 #define CCRF2_FS_VCO3 0x2F24
175 #define CCRF2_FS_VCO2 0x2F25
176 #define CCRF2_FS_VCO1 0x2F26
177 #define CCRF2_FS_VCO0 0x2F27
178 #define CCRF2_GBIAS6 0x2F28
179 #define CCRF2_GBIAS5 0x2F29
180 #define CCRF2_GBIAS4 0x2F2A
181 #define CCRF2_GBIAS3 0x2F2B
182 #define CCRF2_GBIAS2 0x2F2C
183 #define CCRF2_GBIAS1 0x2F2D
184 #define CCRF2_GBIAS0 0x2F2E
185 #define CCRF2_IFAMP 0x2F2F
186 #define CCRF2_LNA 0x2F30
187 #define CCRF2_RXMIX 0x2F31
188 #define CCRF2_XOSC5 0x2F32
189 #define CCRF2_XOSC4 0x2F33
190 #define CCRF2_XOSC3 0x2F34
191 #define CCRF2_XOSC2 0x2F35
192 #define CCRF2_XOSC1 0x2F36
193 #define CCRF2_XOSC0 0x2F37
194 #define CCRF2_ANALOG_SPARE 0x2F38
195 #define CCRF2_PA_CFG3 0x2F39
196 #define CCRF2_IRQ0M 0x2F3F
197 #define CCRF2_IRQ0F 0x2F40
198 
204 #define CCRF2_WOR_TIME1 0x2F64
205 #define CCRF2_WOR_TIME0 0x2F65
206 #define CCRF2_WOR_CAPTURE1 0x2F66
207 #define CCRF2_WOR_CAPTURE0 0x2F67
208 #define CCRF2_BIST 0x2F68
209 #define CCRF2_DCFILTOFFSET_I1 0x2F69
210 #define CCRF2_DCFILTOFFSET_I0 0x2F6A
211 #define CCRF2_DCFILTOFFSET_Q1 0x2F6B
212 #define CCRF2_DCFILTOFFSET_Q0 0x2F6C
213 #define CCRF2_IQIE_I1 0x2F6D
214 #define CCRF2_IQIE_I0 0x2F6E
215 #define CCRF2_IQIE_Q1 0x2F6F
216 #define CCRF2_IQIE_Q0 0x2F70
217 #define CCRF2_RSSI1 0x2F71
218 #define CCRF2_RSSI0 0x2F72
219 #define CCRF2_MARCSTATE 0x2F73
220 #define CCRF2_LQI_VAL 0x2F74
221 #define CCRF2_PQT_SYNC_ERR 0x2F75
222 #define CCRF2_DEM_STATUS 0x2F76
223 #define CCRF2_FREQOFF_EST1 0x2F77
224 #define CCRF2_FREQOFF_EST0 0x2F78
225 #define CCRF2_AGC_GAIN3 0x2F79
226 #define CCRF2_AGC_GAIN2 0x2F7A
227 #define CCRF2_AGC_GAIN1 0x2F7B
228 #define CCRF2_AGC_GAIN0 0x2F7C
229 #define CCRF2_CFM_RX_DATA_OUT 0x2F7D
230 #define CCRF2_CFM_TX_DATA_IN 0x2F7E
231 #define CCRF2_ASK_SOFT_RX_DATA 0x2F7F
232 #define CCRF2_RNDGEN 0x2F80
233 #define CCRF2_MAGN2 0x2F81
234 #define CCRF2_MAGN1 0x2F82
235 #define CCRF2_MAGN0 0x2F83
236 #define CCRF2_ANG1 0x2F84
237 #define CCRF2_ANG0 0x2F85
238 #define CCRF2_CHFILT_I2 0x2F86
239 #define CCRF2_CHFILT_I1 0x2F87
240 #define CCRF2_CHFILT_I0 0x2F88
241 #define CCRF2_CHFILT_Q2 0x2F89
242 #define CCRF2_CHFILT_Q1 0x2F8A
243 #define CCRF2_CHFILT_Q0 0x2F8B
244 #define CCRF2_GPIO_STATUS 0x2F8C
245 #define CCRF2_FSCAL_CTRL 0x2F8D
246 #define CCRF2_PHASE_ADJUST 0x2F8E
247 #define CCRF2_PARTNUMBER 0x2F8F
248 #define CCRF2_PARTVERSION 0x2F90
249 #define CCRF2_SERIAL_STATUS 0x2F91
250 #define CCRF2_MODEM_STATUS1 0x2F92
251 #define CCRF2_MODEM_STATUS0 0x2F93
252 #define CCRF2_MARC_STATUS1 0x2F94
253 #define CCRF2_MARC_STATUS0 0x2F95
254 #define CCRF2_PA_IFAMP_TEST 0x2F96
255 #define CCRF2_FSRF_TEST 0x2F97
256 #define CCRF2_PRE_TEST 0x2F98
257 #define CCRF2_PRE_OVR 0x2F99
258 #define CCRF2_ADC_TEST 0x2F9A
259 #define CCRF2_DVC_TEST 0x2F9B
260 #define CCRF2_ATEST 0x2F9C
261 #define CCRF2_ATEST_LVDS 0x2F9D
262 #define CCRF2_ATEST_MODE 0x2F9E
263 #define CCRF2_XOSC_TEST1 0x2F9F
264 #define CCRF2_XOSC_TEST0 0x2FA0
265 
266 #define CCRF2_RXFIRST 0x2FD2
267 #define CCRF2_TXFIRST 0x2FD3
268 #define CCRF2_RXLAST 0x2FD4
269 #define CCRF2_TXLAST 0x2FD5
270 #define CCRF2_NUM_TXBYTES 0x2FD6
271 #define CCRF2_NUM_RXBYTES 0x2FD7
272 #define CCRF2_FIFO_NUM_TXBYTES 0x2FD8
273 #define CCRF2_FIFO_NUM_RXBYTES 0x2FD9
274 
280 #define CCRF2_SINGLE_TXFIFO 0x003F
281 #define CCRF2_BURST_TXFIFO 0x007F
282 #define CCRF2_SINGLE_RXFIFO 0x00BF
283 #define CCRF2_BURST_RXFIFO 0x00FF
284 
285 #define CCRF2_LQI_CRC_OK_BM 0x80
286 #define CCRF2_LQI_EST_BM 0x7F
287 
293 #define CCRF2_SRES 0x30
294 #define CCRF2_SFSTXON 0x31
295 #define CCRF2_SXOFF 0x32
296 #define CCRF2_SCAL 0x33
297 #define CCRF2_SRX 0x34
298 #define CCRF2_STX 0x35
299 #define CCRF2_SIDLE 0x36
300 #define CCRF2_SWOR 0x38
301 #define CCRF2_SPWD 0x39
302 #define CCRF2_SFRX 0x3A
303 #define CCRF2_SFTX 0x3B
304 #define CCRF2_SWORRST 0x3C
305 #define CCRF2_SNOP 0x3D
306 #define CCRF2_AFC 0x37
307 
313 #define CCRF2_STATE_IDLE 0x00
314 #define CCRF2_STATE_RX 0x10
315 #define CCRF2_STATE_TX 0x20
316 #define CCRF2_STATE_FSTXON 0x30
317 #define CCRF2_STATE_CALIBRATE 0x40
318 #define CCRF2_STATE_SETTLING 0x50
319 #define CCRF2_STATE_RXFIFO_ERROR 0x60
320 #define CCRF2_STATE_TXFIFO_ERROR 0x70
321 
322 #define CCRF2_RADIO_BURST_ACCESS 0x40
323 #define CCRF2_RADIO_SINGLE_ACCESS 0x00
324 #define CCRF2_RADIO_READ_ACCESS 0x80
325 #define CCRF2_RADIO_WRITE_ACCESS 0x00
326 
332 #define CCRF2_STATUS_CHIP_RDYn_BM 0x80
333 #define CCRF2_STATUS_STATE_BM 0x70
334 #define CCRF2_STATUS_FIFO_BYTES_AVA_BM 0x0F
335 
336 #define CCRF2_STATUS_ERROR 0x00
337 #define CCRF2_STATUS_OK 0x01
338 
339 #define CCRF2_IDLE_MODE 0x01
340 #define CCRF2_TX_MODE 0x02
341 #define CCRF2_RX_MODE 0x03
342  // End group macro
344 // --------------------------------------------------------------- PUBLIC TYPES
353 typedef struct
354 {
355  // Output pins
356 
357  digital_out_t cs;
358  digital_out_t rst;
359 
360  // Input pins
361 
362  digital_in_t gp0;
363  digital_in_t gp2;
364  digital_in_t gp3;
365  digital_in_t miso;
366 
367  // Modules
368 
369  spi_master_t spi;
370  pin_name_t chip_select;
371 
372  uint16_t packet_counter;
373 } ccrf2_t;
374 
378 typedef struct
379 {
380  // Communication gpio pins
381 
382  pin_name_t miso;
383  pin_name_t mosi;
384  pin_name_t sck;
385  pin_name_t cs;
386 
387  // Additional gpio pins
388 
389  pin_name_t gp0;
390  pin_name_t rst;
391  pin_name_t gp2;
392  pin_name_t gp3;
393 
394  // static variable
395 
396  uint32_t spi_speed;
397  spi_master_mode_t spi_mode;
398  spi_master_chip_select_polarity_t cs_polarity;
399 } ccrf2_cfg_t;
400  // End types group
402 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
403 
408 #ifdef __cplusplus
409 extern "C"{
410 #endif
411 
421 
431 
440 
451 void ccrf2_hw_reset ( ccrf2_t *ctx );
452 
464 uint8_t ccrf2_cmd_strobe ( ccrf2_t *ctx, uint8_t cmd );
465 
477 void ccrf2_read_write_burst_single ( ccrf2_t *ctx, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes );
478 
493 uint8_t ccrf2_8bit_reg_access ( ccrf2_t *ctx, char access_type, uint8_t reg_address, uint8_t *rw_data,
494  uint16_t n_bytes );
495 
511 uint8_t ccrf2_16bit_reg_access ( ccrf2_t *ctx, uint8_t access_type, uint8_t ext_address,
512  uint8_t reg_address, uint8_t *rw_data, uint8_t n_bytes );
513 
527 uint8_t ccrf2_read_reg ( ccrf2_t *ctx, uint16_t reg_address, uint8_t *read_data, uint8_t n_bytes );
528 
542 uint8_t ccrf2_write_reg ( ccrf2_t *ctx, uint16_t reg_address, uint8_t *write_data, uint8_t n_bytes );
543 
556 uint8_t ccrf2_write_reg_single( ccrf2_t *ctx, uint16_t reg_address, uint8_t write_data );
557 
570 uint8_t ccrf2_write_tx_fifo ( ccrf2_t *ctx, uint8_t *write_data, uint8_t n_bytes );
571 
585 uint8_t ccrf2_read_rx_fifo ( ccrf2_t *ctx, uint8_t *read_data, uint8_t n_bytes );
586 
596 
606 
617 
626 uint8_t ccrf2_read_gp0 ( ccrf2_t *ctx );
627 
636 uint8_t ccrf2_read_gp2 ( ccrf2_t *ctx );
637 
646 uint8_t ccrf2_read_gp3 ( ccrf2_t *ctx );
647 
658 void ccrf2_send_tx_data ( ccrf2_t *ctx, uint8_t *tx_data, uint8_t n_bytes );
659 
672 uint8_t ccrf2_receive_rx_data ( ccrf2_t *ctx, uint8_t *rx_data );
673 
674 #ifdef __cplusplus
675 }
676 #endif
677 #endif // _CCRF2_H_
678  // End public_function group
681 
682 // ------------------------------------------------------------------------- END
ccrf2_t::gp3
digital_in_t gp3
Definition: ccrf2.h:364
ccrf2_t::gp0
digital_in_t gp0
Definition: ccrf2.h:362
ccrf2_hw_reset
void ccrf2_hw_reset(ccrf2_t *ctx)
Hardware reset function.
ccrf2_t::miso
digital_in_t miso
Definition: ccrf2.h:365
ccrf2_cfg_t::cs
pin_name_t cs
Definition: ccrf2.h:385
ccrf2_receive_rx_data
uint8_t ccrf2_receive_rx_data(ccrf2_t *ctx, uint8_t *rx_data)
Receive RX data function.
ccrf2_cfg_t
Click configuration structure definition.
Definition: ccrf2.h:379
ccrf2_8bit_reg_access
uint8_t ccrf2_8bit_reg_access(ccrf2_t *ctx, char access_type, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes)
Access 8-bit register function.
ccrf2_cmd_strobe
uint8_t ccrf2_cmd_strobe(ccrf2_t *ctx, uint8_t cmd)
Set command strobe function.
ccrf2_read_gp3
uint8_t ccrf2_read_gp3(ccrf2_t *ctx)
Read state of GP3 pin function.
ccrf2_cfg_t::sck
pin_name_t sck
Definition: ccrf2.h:384
ccrf2_cfg_t::spi_speed
uint32_t spi_speed
Definition: ccrf2.h:396
ccrf2_read_gp0
uint8_t ccrf2_read_gp0(ccrf2_t *ctx)
Read state of GP0 pin function.
ccrf2_cfg_t::gp2
pin_name_t gp2
Definition: ccrf2.h:391
ccrf2_read_rx_fifo
uint8_t ccrf2_read_rx_fifo(ccrf2_t *ctx, uint8_t *read_data, uint8_t n_bytes)
Read RX FIFO register function.
ccrf2_cfg_t::miso
pin_name_t miso
Definition: ccrf2.h:382
ccrf2_set_tx_mode
void ccrf2_set_tx_mode(ccrf2_t *ctx)
Set TX mode function.
ccrf2_read_reg
uint8_t ccrf2_read_reg(ccrf2_t *ctx, uint16_t reg_address, uint8_t *read_data, uint8_t n_bytes)
Read the byte of data function.
ccrf2_manual_calibration
void ccrf2_manual_calibration(ccrf2_t *ctx)
Manual calibration function.
ccrf2_read_gp2
uint8_t ccrf2_read_gp2(ccrf2_t *ctx)
Read state of GP2 pin function.
ccrf2_send_tx_data
void ccrf2_send_tx_data(ccrf2_t *ctx, uint8_t *tx_data, uint8_t n_bytes)
Send TX data function.
ccrf2_default_cfg
void ccrf2_default_cfg(ccrf2_t *ctx)
Click Default Configuration function.
ccrf2_t::cs
digital_out_t cs
Definition: ccrf2.h:357
ccrf2_init
CCRF2_RETVAL ccrf2_init(ccrf2_t *ctx, ccrf2_cfg_t *cfg)
Initialization function.
ccrf2_t::chip_select
pin_name_t chip_select
Definition: ccrf2.h:370
ccrf2_read_write_burst_single
void ccrf2_read_write_burst_single(ccrf2_t *ctx, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes)
Read or write burst single function.
ccrf2_t
Click ctx object definition.
Definition: ccrf2.h:354
ccrf2_t::rst
digital_out_t rst
Definition: ccrf2.h:358
ccrf2_16bit_reg_access
uint8_t ccrf2_16bit_reg_access(ccrf2_t *ctx, uint8_t access_type, uint8_t ext_address, uint8_t reg_address, uint8_t *rw_data, uint8_t n_bytes)
Access 16-bit register function.
ccrf2_set_rx_mode
void ccrf2_set_rx_mode(ccrf2_t *ctx)
Set RX mode function.
ccrf2_cfg_t::rst
pin_name_t rst
Definition: ccrf2.h:390
ccrf2_write_reg
uint8_t ccrf2_write_reg(ccrf2_t *ctx, uint16_t reg_address, uint8_t *write_data, uint8_t n_bytes)
Write sequential data function.
ccrf2_t::packet_counter
uint16_t packet_counter
Definition: ccrf2.h:372
ccrf2_cfg_setup
void ccrf2_cfg_setup(ccrf2_cfg_t *cfg)
Config Object Initialization function.
ccrf2_cfg_t::gp3
pin_name_t gp3
Definition: ccrf2.h:392
ccrf2_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: ccrf2.h:397
ccrf2_write_tx_fifo
uint8_t ccrf2_write_tx_fifo(ccrf2_t *ctx, uint8_t *write_data, uint8_t n_bytes)
Write TX FIFO register function.
ccrf2_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: ccrf2.h:398
ccrf2_cfg_t::mosi
pin_name_t mosi
Definition: ccrf2.h:383
ccrf2_t::spi
spi_master_t spi
Definition: ccrf2.h:369
ccrf2_cfg_t::gp0
pin_name_t gp0
Definition: ccrf2.h:389
CCRF2_RETVAL
#define CCRF2_RETVAL
Definition: ccrf2.h:68
ccrf2_write_reg_single
uint8_t ccrf2_write_reg_single(ccrf2_t *ctx, uint16_t reg_address, uint8_t write_data)
Write one byte data function.
ccrf2_t::gp2
digital_in_t gp2
Definition: ccrf2.h:363