enocan3  2.0.0.0
enocan3.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN3_H
36 #define ENOCEAN3_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_uart.h"
41 
42 
43 // -------------------------------------------------------------- PUBLIC MACROS
53 #define ENOCEAN3_MAP_MIKROBUS( cfg, mikrobus ) \
54  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
55  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX ); \
56  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST )
57 
64 #define ENOCEAN3_RETVAL uint8_t
65 
66 #define ENOCEAN3_OK 0x00
67 #define ENOCEAN3_INIT_ERROR 0xFF
68 
74 #define ENOCEAN3_NEMA_GPGGA 1
75 #define ENOCEAN3_NEMA_GPGLL 3
76 #define ENOCEAN3_NEMA_GPGGA_NUM_ELEMENT 15
77 #define ENOCEAN3_NEMA_GPGLL_NUM_ELEMENT 5
78 
84 #define ENOCEAN3_GPGGA_TIME 1
85 #define ENOCEAN3_GPGGA_LATITUDE 2
86 #define ENOCEAN3_GPGGA_LATITUDE_SIDE 3
87 #define ENOCEAN3_GPGGA_LONGITUDE 4
88 #define ENOCEAN3_GPGGA_LONGITUDE_SIDE 5
89 #define ENOCEAN3_GPGGA_QUALITY_INDICATOR 6
90 #define ENOCEAN3_GPGGA_NUMBER_OF_SATELLITES 7
91 #define ENOCEAN3_GPGGA_H_DILUTION_OF_POS 8
92 #define ENOCEAN3_GPGGA_ALTITUDE 9
93 #define ENOCEAN3_GPGGA_ALTITUDE_UNIT 10
94 #define ENOCEAN3_GPGGA_GEOIDAL_SEPARATION 11
95 #define ENOCEAN3_GPGGA_GEOIDAL_SEPARATION_UNIT 12
96 #define ENOCEAN3_GPGGA_TIME_SINCE_LAST_DGPS 13
97 #define ENOCEAN3_GPGGA_DGPS_REFERENCE_STATION_ID 14
98 
104 #define ENOCEAN3_GPGLL_LATITUDE 1
105 #define ENOCEAN3_GPGLL_LATITUDE_SIDE 2
106 #define ENOCEAN3_GPGLL_LONGITUDE 3
107 #define ENOCEAN3_GPGLL_LONGITUDE_SIDE 4
108 
114 #define ENOCEAN3_ERROR_COMMAND_OR_ELEMENT 0xFF
115 #define ENOCEAN3_ERROR_START_OR_END_COMMAND 0x8F
116 #define ENOCEAN3_ERROR_NEXT_ELEMENT 0x4F
117 #define ENOCEAN3_ERROR_CURRENT_ELEMENT 0x2F
118 #define ENOCEAN3_NO_ERROR 0x00
119 
125 #define DRV_RX_BUFFER_SIZE 500
126 
129 #define ENOCEAN3_SYNC_BYTE 0x55
130 #define ENOCEAN3_MAX_BUFF_SIZE 256
131 #define ENOCEAN3_HEADER_SIZE 0x04
132 #define ENOCEAN3_BUFF_EMPTY 0x00
133 
134 
135 #define ENOCEAN3_RESPONSE_READY 0x01
136 #define ENOCEAN3_RESPONSE_NOT_READY 0x00
137 #define ENOCEAN3_UART_RX_READY 0x01
138 #define ENOCEAN3_UART_RX_NOT_READY 0x00
139 #define ENOCEAN3_OK 0x00
140 #define ENOCEAN3_INVALID_PACKET_SIZE 0x01
141 
142 #define ENOCEAN3_PACK_TYPE_EVENT 0x04
143 #define ENOCEAN3_PACK_TYPE_COMMON_COMMAND 0x05
144 #define ENOCEAN3_CO_EVENT_SECUREDEVICES 0x05
145 #define ENOCEAN3_CO_WR_FILTER_ADD 0x0B
146 #define ENOCEAN3_CO_WR_FILTER_ENABLE 0x0E
147 #define ENOCEAN3_CO_WR_REPEATER 0x09
148 #define ENOCEAN3_CO_SET_NOISETHRESHOLD 0x32
149 
150 #define ENOCEAN3_FILT_TYPE_SOURCE_ID 0x00
151 #define ENOCEAN3_FILT_TYPE_R_ORG 0x01
152 #define ENOCEAN3_FILT_TYPE_RSSI 0x02
153 #define ENOCEAN3_FILT_TYPE_DEST_ID 0x03
154 #define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD 0x00
155 #define ENOCEAN3_FILT_KIND_POS_TEL_FWRD 0x80
156 #define ENOCEAN3_FILT_KIND_NEG_TEL_RPT 0x40
157 #define ENOCEAN3_FILT_KIND_POS_TEL_RPT 0xC0
158 #define ENOCEAN3_FILT_FWRD_OFF 0x00
159 #define ENOCEAN3_FILT_FWRD_ON 0x01
160 #define ENOCEAN3_FILT_OP_OR_ALL_FILT 0x00
161 #define ENOCEAN3_FILT_OP_AND_ALL_FILT 0x01
162 #define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT 0x08
163 #define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT 0x09
164 #define ENOCEAN3_RPT_OFF 0x00
165 #define ENOCEAN3_RPT_ALL_TELEG 0x01
166 #define ENOCEAN3_RPT_SELECTIVE 0x02
167 #define ENOCEAN3_RPT_LEVEL_OFF 0x00
168 #define ENOCEAN3_RPT_LEVEL_ONE 0x01
169 #define ENOCEAN3_RPT_LEVEL_TWO 0x02
170 #define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG 0x2E
171 #define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG 0x2F
172 #define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG 0x30
173 #define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG 0x31
174 #define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG 0x32
175 #define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG 0x33
176 #define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG 0x34
177 #define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG 0x35
178 #define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG 0x36
179 #define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG 0x37
180 #define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG 0x38
181  // End group macro
183 // --------------------------------------------------------------- PUBLIC TYPES /** @{ */
189 
190 typedef struct {
191 
192  uint16_t data_length;
193  uint8_t opt_length;
194  uint8_t packet_type;
195  uint8_t data_buff[ 256 ];
196 
198 
199 typedef void ( *enocean3_hdl_t )( enocean3_packet_t*, uint16_t* );
200 
204 typedef struct
205 {
206  // Output pins
207 
208  digital_out_t rst;
209 
210  // Modules
211 
212  uart_t uart;
213 
214  char uart_rx_buffer[ DRV_RX_BUFFER_SIZE ];
215  char uart_tx_buffer[ DRV_RX_BUFFER_SIZE ];
216 
218  uint8_t response_ready;
219 
220 } enocan3_t;
221 
225 typedef struct
226 {
227  // Communication gpio pins
228 
229  pin_name_t rx_pin;
230  pin_name_t tx_pin;
231 
232  // Additional gpio pins
233 
234  pin_name_t rst;
235 
236  // static variable
237 
238  uint32_t baud_rate; // Clock speed.
240  uart_data_bits_t data_bit; // Data bits.
241  uart_parity_t parity_bit; // Parity bit.
242  uart_stop_bits_t stop_bit; // Stop bits.
243 
244 } enocan3_cfg_t;
245 
249 typedef uint8_t enocan3_error_t;
250  // End types group
252 
253 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
254 
260 #ifdef __cplusplus
261 extern "C"{
262 #endif
263 
273 
282 
288 void enocan3_set_rst_pin ( enocan3_t *ctx, uint8_t state );
289 
296 void enocan3_generic_write ( enocan3_t *ctx, char *data_buf, uint16_t len );
297 
305 uint16_t enocan3_generic_read ( enocan3_t *ctx, char *data_buf, uint16_t max_len );
306 
316 
317 (
318  char *rsp, uint8_t command,
319  uint8_t element, char *parser_buf
320 );
321 
331 
343 
354 
364 
365 
366 #ifdef __cplusplus
367 }
368 #endif
369 #endif // _ENOCEAN3_H_
370  // End public_function group
373 
374 // ------------------------------------------------------------------------- END
enocan3_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocan3.h:240
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocan3.h:125
ENOCEAN3_RETVAL
#define ENOCEAN3_RETVAL
Definition: enocan3.h:64
enocan3_generic_parser
enocan3_error_t enocan3_generic_parser(char *rsp, uint8_t command, uint8_t element, char *parser_buf)
Generic parser function.
enocan3_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocan3.h:229
enocan3_cfg_t
Click configuration structure definition.
Definition: enocan3.h:226
enocan3_set_rst_pin
void enocan3_set_rst_pin(enocan3_t *ctx, uint8_t state)
Set RST ( reset ) pin state.
enocan3_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocan3.h:230
enocean3_send_packet
uint8_t enocean3_send_packet(enocan3_t *ctx, enocean3_packet_t *packet)
Packet Send function.
enocean3_response_ready
uint8_t enocean3_response_ready(enocan3_t *ctx)
Response Ready function.
enocean3_packet_t::opt_length
uint8_t opt_length
Definition: enocan3.h:193
enocan3_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocan3.h:242
enocan3_error_t
uint8_t enocan3_error_t
Error type.
Definition: enocan3.h:249
enocan3_t::response_ready
uint8_t response_ready
Definition: enocan3.h:218
enocan3_t::driver_hdl
enocean3_hdl_t driver_hdl
Definition: enocan3.h:217
enocan3_cfg_t::rst
pin_name_t rst
Definition: enocan3.h:234
enocean3_uart_isr
void enocean3_uart_isr(enocan3_t *ctx)
UART Interrupt Routine function.
enocan3_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocan3.h:238
enocan3_init
ENOCEAN3_RETVAL enocan3_init(enocan3_t *ctx, enocan3_cfg_t *cfg)
Initialization function.
enocean3_response_handler_set
void enocean3_response_handler_set(enocan3_t *ctx, enocean3_hdl_t handler)
Handler Set function.
enocean3_packet_t::packet_type
uint8_t packet_type
Definition: enocan3.h:194
enocan3_generic_write
void enocan3_generic_write(enocan3_t *ctx, char *data_buf, uint16_t len)
Generic write function.
enocan3_generic_read
uint16_t enocan3_generic_read(enocan3_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocan3_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocan3.h:241
enocan3_t::uart
uart_t uart
Definition: enocan3.h:212
enocean3_packet_t::data_length
uint16_t data_length
Definition: enocan3.h:192
enocan3_t::rst
digital_out_t rst
Definition: enocan3.h:208
enocean3_packet_t
Definition: enocan3.h:190
enocean3_hdl_t
void(* enocean3_hdl_t)(enocean3_packet_t *, uint16_t *)
Definition: enocan3.h:199
enocan3_t
Click ctx object definition.
Definition: enocan3.h:205
enocan3_cfg_t::uart_blocking
bool uart_blocking
Definition: enocan3.h:239
enocan3_cfg_setup
void enocan3_cfg_setup(enocan3_cfg_t *cfg)
Config Object Initialization function.