enocan3
2.0.0.0
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Modules | |
MikroBUS | |
Error Code | |
Current support NEMA command | |
GPGGA command elements | |
GPGLL command elements | |
Parser command error | |
Driver define | |
#define ENOCEAN3_BUFF_EMPTY 0x00 |
#define ENOCEAN3_BUFF_EMPTY 0x00 |
#define ENOCEAN3_CO_EVENT_SECUREDEVICES 0x05 |
#define ENOCEAN3_CO_EVENT_SECUREDEVICES 0x05 |
#define ENOCEAN3_CO_SET_NOISETHRESHOLD 0x32 |
#define ENOCEAN3_CO_SET_NOISETHRESHOLD 0x32 |
#define ENOCEAN3_CO_WR_FILTER_ADD 0x0B |
#define ENOCEAN3_CO_WR_FILTER_ADD 0x0B |
#define ENOCEAN3_CO_WR_FILTER_ENABLE 0x0E |
#define ENOCEAN3_CO_WR_FILTER_ENABLE 0x0E |
#define ENOCEAN3_CO_WR_REPEATER 0x09 |
#define ENOCEAN3_CO_WR_REPEATER 0x09 |
#define ENOCEAN3_FILT_FWRD_OFF 0x00 |
#define ENOCEAN3_FILT_FWRD_OFF 0x00 |
#define ENOCEAN3_FILT_FWRD_ON 0x01 |
#define ENOCEAN3_FILT_FWRD_ON 0x01 |
#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD 0x00 |
#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD 0x00 |
#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT 0x40 |
#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT 0x40 |
#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD 0x80 |
#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD 0x80 |
#define ENOCEAN3_FILT_KIND_POS_TEL_RPT 0xC0 |
#define ENOCEAN3_FILT_KIND_POS_TEL_RPT 0xC0 |
#define ENOCEAN3_FILT_OP_AND_ALL_FILT 0x01 |
#define ENOCEAN3_FILT_OP_AND_ALL_FILT 0x01 |
#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT 0x09 |
#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT 0x09 |
#define ENOCEAN3_FILT_OP_OR_ALL_FILT 0x00 |
#define ENOCEAN3_FILT_OP_OR_ALL_FILT 0x00 |
#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT 0x08 |
#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT 0x08 |
#define ENOCEAN3_FILT_TYPE_DEST_ID 0x03 |
#define ENOCEAN3_FILT_TYPE_DEST_ID 0x03 |
#define ENOCEAN3_FILT_TYPE_R_ORG 0x01 |
#define ENOCEAN3_FILT_TYPE_R_ORG 0x01 |
#define ENOCEAN3_FILT_TYPE_RSSI 0x02 |
#define ENOCEAN3_FILT_TYPE_RSSI 0x02 |
#define ENOCEAN3_FILT_TYPE_SOURCE_ID 0x00 |
#define ENOCEAN3_FILT_TYPE_SOURCE_ID 0x00 |
#define ENOCEAN3_HEADER_SIZE 0x04 |
#define ENOCEAN3_HEADER_SIZE 0x04 |
#define ENOCEAN3_INVALID_PACKET_SIZE 0x01 |
#define ENOCEAN3_INVALID_PACKET_SIZE 0x01 |
#define ENOCEAN3_MAX_BUFF_SIZE 256 |
#define ENOCEAN3_MAX_BUFF_SIZE 256 |
#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND 0x05 |
#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND 0x05 |
#define ENOCEAN3_PACK_TYPE_EVENT 0x04 |
#define ENOCEAN3_PACK_TYPE_EVENT 0x04 |
#define ENOCEAN3_RESPONSE_NOT_READY 0x00 |
#define ENOCEAN3_RESPONSE_NOT_READY 0x00 |
#define ENOCEAN3_RESPONSE_READY 0x01 |
#define ENOCEAN3_RESPONSE_READY 0x01 |
#define ENOCEAN3_RPT_ALL_TELEG 0x01 |
#define ENOCEAN3_RPT_ALL_TELEG 0x01 |
#define ENOCEAN3_RPT_LEVEL_OFF 0x00 |
#define ENOCEAN3_RPT_LEVEL_OFF 0x00 |
#define ENOCEAN3_RPT_LEVEL_ONE 0x01 |
#define ENOCEAN3_RPT_LEVEL_ONE 0x01 |
#define ENOCEAN3_RPT_LEVEL_TWO 0x02 |
#define ENOCEAN3_RPT_LEVEL_TWO 0x02 |
#define ENOCEAN3_RPT_OFF 0x00 |
#define ENOCEAN3_RPT_OFF 0x00 |
#define ENOCEAN3_RPT_SELECTIVE 0x02 |
#define ENOCEAN3_RPT_SELECTIVE 0x02 |
#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG 0x2E |
#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG 0x2E |
#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG 0x38 |
#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG 0x38 |
#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG 0x37 |
#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG 0x37 |
#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG 0x36 |
#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG 0x36 |
#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG 0x35 |
#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG 0x35 |
#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG 0x34 |
#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG 0x34 |
#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG 0x33 |
#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG 0x33 |
#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG 0x32 |
#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG 0x32 |
#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG 0x31 |
#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG 0x31 |
#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG 0x30 |
#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG 0x30 |
#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG 0x2F |
#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG 0x2F |
#define ENOCEAN3_SYNC_BYTE 0x55 |
#define ENOCEAN3_SYNC_BYTE 0x55 |
#define ENOCEAN3_UART_RX_NOT_READY 0x00 |
#define ENOCEAN3_UART_RX_NOT_READY 0x00 |
#define ENOCEAN3_UART_RX_READY 0x01 |
#define ENOCEAN3_UART_RX_READY 0x01 |