enocan3  2.0.0.0
Modules | Macros

Modules

 MikroBUS
 
 Error Code
 
 Current support NEMA command
 
 GPGGA command elements
 
 GPGLL command elements
 
 Parser command error
 
 Driver define
 

Macros

#define ENOCEAN3_SYNC_BYTE   0x55
 
#define ENOCEAN3_MAX_BUFF_SIZE   256
 
#define ENOCEAN3_HEADER_SIZE   0x04
 
#define ENOCEAN3_BUFF_EMPTY   0x00
 
#define ENOCEAN3_RESPONSE_READY   0x01
 
#define ENOCEAN3_RESPONSE_NOT_READY   0x00
 
#define ENOCEAN3_UART_RX_READY   0x01
 
#define ENOCEAN3_UART_RX_NOT_READY   0x00
 
#define ENOCEAN3_INVALID_PACKET_SIZE   0x01
 
#define ENOCEAN3_PACK_TYPE_EVENT   0x04
 
#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND   0x05
 
#define ENOCEAN3_CO_EVENT_SECUREDEVICES   0x05
 
#define ENOCEAN3_CO_WR_FILTER_ADD   0x0B
 
#define ENOCEAN3_CO_WR_FILTER_ENABLE   0x0E
 
#define ENOCEAN3_CO_WR_REPEATER   0x09
 
#define ENOCEAN3_CO_SET_NOISETHRESHOLD   0x32
 
#define ENOCEAN3_FILT_TYPE_SOURCE_ID   0x00
 
#define ENOCEAN3_FILT_TYPE_R_ORG   0x01
 
#define ENOCEAN3_FILT_TYPE_RSSI   0x02
 
#define ENOCEAN3_FILT_TYPE_DEST_ID   0x03
 
#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD   0x00
 
#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD   0x80
 
#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT   0x40
 
#define ENOCEAN3_FILT_KIND_POS_TEL_RPT   0xC0
 
#define ENOCEAN3_FILT_FWRD_OFF   0x00
 
#define ENOCEAN3_FILT_FWRD_ON   0x01
 
#define ENOCEAN3_FILT_OP_OR_ALL_FILT   0x00
 
#define ENOCEAN3_FILT_OP_AND_ALL_FILT   0x01
 
#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT   0x08
 
#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT   0x09
 
#define ENOCEAN3_RPT_OFF   0x00
 
#define ENOCEAN3_RPT_ALL_TELEG   0x01
 
#define ENOCEAN3_RPT_SELECTIVE   0x02
 
#define ENOCEAN3_RPT_LEVEL_OFF   0x00
 
#define ENOCEAN3_RPT_LEVEL_ONE   0x01
 
#define ENOCEAN3_RPT_LEVEL_TWO   0x02
 
#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG   0x2E
 
#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG   0x2F
 
#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG   0x30
 
#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG   0x31
 
#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG   0x32
 
#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG   0x33
 
#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG   0x34
 
#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG   0x35
 
#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG   0x36
 
#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG   0x37
 
#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG   0x38
 
#define ENOCEAN3_SYNC_BYTE   0x55
 
#define ENOCEAN3_MAX_BUFF_SIZE   256
 
#define ENOCEAN3_HEADER_SIZE   0x04
 
#define ENOCEAN3_BUFF_EMPTY   0x00
 
#define ENOCEAN3_RESPONSE_READY   0x01
 
#define ENOCEAN3_RESPONSE_NOT_READY   0x00
 
#define ENOCEAN3_UART_RX_READY   0x01
 
#define ENOCEAN3_UART_RX_NOT_READY   0x00
 
#define ENOCEAN3_INVALID_PACKET_SIZE   0x01
 
#define ENOCEAN3_PACK_TYPE_EVENT   0x04
 
#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND   0x05
 
#define ENOCEAN3_CO_EVENT_SECUREDEVICES   0x05
 
#define ENOCEAN3_CO_WR_FILTER_ADD   0x0B
 
#define ENOCEAN3_CO_WR_FILTER_ENABLE   0x0E
 
#define ENOCEAN3_CO_WR_REPEATER   0x09
 
#define ENOCEAN3_CO_SET_NOISETHRESHOLD   0x32
 
#define ENOCEAN3_FILT_TYPE_SOURCE_ID   0x00
 
#define ENOCEAN3_FILT_TYPE_R_ORG   0x01
 
#define ENOCEAN3_FILT_TYPE_RSSI   0x02
 
#define ENOCEAN3_FILT_TYPE_DEST_ID   0x03
 
#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD   0x00
 
#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD   0x80
 
#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT   0x40
 
#define ENOCEAN3_FILT_KIND_POS_TEL_RPT   0xC0
 
#define ENOCEAN3_FILT_FWRD_OFF   0x00
 
#define ENOCEAN3_FILT_FWRD_ON   0x01
 
#define ENOCEAN3_FILT_OP_OR_ALL_FILT   0x00
 
#define ENOCEAN3_FILT_OP_AND_ALL_FILT   0x01
 
#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT   0x08
 
#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT   0x09
 
#define ENOCEAN3_RPT_OFF   0x00
 
#define ENOCEAN3_RPT_ALL_TELEG   0x01
 
#define ENOCEAN3_RPT_SELECTIVE   0x02
 
#define ENOCEAN3_RPT_LEVEL_OFF   0x00
 
#define ENOCEAN3_RPT_LEVEL_ONE   0x01
 
#define ENOCEAN3_RPT_LEVEL_TWO   0x02
 
#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG   0x2E
 
#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG   0x2F
 
#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG   0x30
 
#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG   0x31
 
#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG   0x32
 
#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG   0x33
 
#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG   0x34
 
#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG   0x35
 
#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG   0x36
 
#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG   0x37
 
#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG   0x38
 

Detailed Description

Macro Definition Documentation

◆ ENOCEAN3_BUFF_EMPTY [1/2]

#define ENOCEAN3_BUFF_EMPTY   0x00

◆ ENOCEAN3_BUFF_EMPTY [2/2]

#define ENOCEAN3_BUFF_EMPTY   0x00

◆ ENOCEAN3_CO_EVENT_SECUREDEVICES [1/2]

#define ENOCEAN3_CO_EVENT_SECUREDEVICES   0x05

◆ ENOCEAN3_CO_EVENT_SECUREDEVICES [2/2]

#define ENOCEAN3_CO_EVENT_SECUREDEVICES   0x05

◆ ENOCEAN3_CO_SET_NOISETHRESHOLD [1/2]

#define ENOCEAN3_CO_SET_NOISETHRESHOLD   0x32

◆ ENOCEAN3_CO_SET_NOISETHRESHOLD [2/2]

#define ENOCEAN3_CO_SET_NOISETHRESHOLD   0x32

◆ ENOCEAN3_CO_WR_FILTER_ADD [1/2]

#define ENOCEAN3_CO_WR_FILTER_ADD   0x0B

◆ ENOCEAN3_CO_WR_FILTER_ADD [2/2]

#define ENOCEAN3_CO_WR_FILTER_ADD   0x0B

◆ ENOCEAN3_CO_WR_FILTER_ENABLE [1/2]

#define ENOCEAN3_CO_WR_FILTER_ENABLE   0x0E

◆ ENOCEAN3_CO_WR_FILTER_ENABLE [2/2]

#define ENOCEAN3_CO_WR_FILTER_ENABLE   0x0E

◆ ENOCEAN3_CO_WR_REPEATER [1/2]

#define ENOCEAN3_CO_WR_REPEATER   0x09

◆ ENOCEAN3_CO_WR_REPEATER [2/2]

#define ENOCEAN3_CO_WR_REPEATER   0x09

◆ ENOCEAN3_FILT_FWRD_OFF [1/2]

#define ENOCEAN3_FILT_FWRD_OFF   0x00

◆ ENOCEAN3_FILT_FWRD_OFF [2/2]

#define ENOCEAN3_FILT_FWRD_OFF   0x00

◆ ENOCEAN3_FILT_FWRD_ON [1/2]

#define ENOCEAN3_FILT_FWRD_ON   0x01

◆ ENOCEAN3_FILT_FWRD_ON [2/2]

#define ENOCEAN3_FILT_FWRD_ON   0x01

◆ ENOCEAN3_FILT_KIND_NEG_TEL_FWRD [1/2]

#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD   0x00

◆ ENOCEAN3_FILT_KIND_NEG_TEL_FWRD [2/2]

#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD   0x00

◆ ENOCEAN3_FILT_KIND_NEG_TEL_RPT [1/2]

#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT   0x40

◆ ENOCEAN3_FILT_KIND_NEG_TEL_RPT [2/2]

#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT   0x40

◆ ENOCEAN3_FILT_KIND_POS_TEL_FWRD [1/2]

#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD   0x80

◆ ENOCEAN3_FILT_KIND_POS_TEL_FWRD [2/2]

#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD   0x80

◆ ENOCEAN3_FILT_KIND_POS_TEL_RPT [1/2]

#define ENOCEAN3_FILT_KIND_POS_TEL_RPT   0xC0

◆ ENOCEAN3_FILT_KIND_POS_TEL_RPT [2/2]

#define ENOCEAN3_FILT_KIND_POS_TEL_RPT   0xC0

◆ ENOCEAN3_FILT_OP_AND_ALL_FILT [1/2]

#define ENOCEAN3_FILT_OP_AND_ALL_FILT   0x01

◆ ENOCEAN3_FILT_OP_AND_ALL_FILT [2/2]

#define ENOCEAN3_FILT_OP_AND_ALL_FILT   0x01

◆ ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT [1/2]

#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT   0x09

◆ ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT [2/2]

#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT   0x09

◆ ENOCEAN3_FILT_OP_OR_ALL_FILT [1/2]

#define ENOCEAN3_FILT_OP_OR_ALL_FILT   0x00

◆ ENOCEAN3_FILT_OP_OR_ALL_FILT [2/2]

#define ENOCEAN3_FILT_OP_OR_ALL_FILT   0x00

◆ ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT [1/2]

#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT   0x08

◆ ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT [2/2]

#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT   0x08

◆ ENOCEAN3_FILT_TYPE_DEST_ID [1/2]

#define ENOCEAN3_FILT_TYPE_DEST_ID   0x03

◆ ENOCEAN3_FILT_TYPE_DEST_ID [2/2]

#define ENOCEAN3_FILT_TYPE_DEST_ID   0x03

◆ ENOCEAN3_FILT_TYPE_R_ORG [1/2]

#define ENOCEAN3_FILT_TYPE_R_ORG   0x01

◆ ENOCEAN3_FILT_TYPE_R_ORG [2/2]

#define ENOCEAN3_FILT_TYPE_R_ORG   0x01

◆ ENOCEAN3_FILT_TYPE_RSSI [1/2]

#define ENOCEAN3_FILT_TYPE_RSSI   0x02

◆ ENOCEAN3_FILT_TYPE_RSSI [2/2]

#define ENOCEAN3_FILT_TYPE_RSSI   0x02

◆ ENOCEAN3_FILT_TYPE_SOURCE_ID [1/2]

#define ENOCEAN3_FILT_TYPE_SOURCE_ID   0x00

◆ ENOCEAN3_FILT_TYPE_SOURCE_ID [2/2]

#define ENOCEAN3_FILT_TYPE_SOURCE_ID   0x00

◆ ENOCEAN3_HEADER_SIZE [1/2]

#define ENOCEAN3_HEADER_SIZE   0x04

◆ ENOCEAN3_HEADER_SIZE [2/2]

#define ENOCEAN3_HEADER_SIZE   0x04

◆ ENOCEAN3_INVALID_PACKET_SIZE [1/2]

#define ENOCEAN3_INVALID_PACKET_SIZE   0x01

◆ ENOCEAN3_INVALID_PACKET_SIZE [2/2]

#define ENOCEAN3_INVALID_PACKET_SIZE   0x01

◆ ENOCEAN3_MAX_BUFF_SIZE [1/2]

#define ENOCEAN3_MAX_BUFF_SIZE   256

◆ ENOCEAN3_MAX_BUFF_SIZE [2/2]

#define ENOCEAN3_MAX_BUFF_SIZE   256

◆ ENOCEAN3_PACK_TYPE_COMMON_COMMAND [1/2]

#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND   0x05

◆ ENOCEAN3_PACK_TYPE_COMMON_COMMAND [2/2]

#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND   0x05

◆ ENOCEAN3_PACK_TYPE_EVENT [1/2]

#define ENOCEAN3_PACK_TYPE_EVENT   0x04

◆ ENOCEAN3_PACK_TYPE_EVENT [2/2]

#define ENOCEAN3_PACK_TYPE_EVENT   0x04

◆ ENOCEAN3_RESPONSE_NOT_READY [1/2]

#define ENOCEAN3_RESPONSE_NOT_READY   0x00

◆ ENOCEAN3_RESPONSE_NOT_READY [2/2]

#define ENOCEAN3_RESPONSE_NOT_READY   0x00

◆ ENOCEAN3_RESPONSE_READY [1/2]

#define ENOCEAN3_RESPONSE_READY   0x01

◆ ENOCEAN3_RESPONSE_READY [2/2]

#define ENOCEAN3_RESPONSE_READY   0x01

◆ ENOCEAN3_RPT_ALL_TELEG [1/2]

#define ENOCEAN3_RPT_ALL_TELEG   0x01

◆ ENOCEAN3_RPT_ALL_TELEG [2/2]

#define ENOCEAN3_RPT_ALL_TELEG   0x01

◆ ENOCEAN3_RPT_LEVEL_OFF [1/2]

#define ENOCEAN3_RPT_LEVEL_OFF   0x00

◆ ENOCEAN3_RPT_LEVEL_OFF [2/2]

#define ENOCEAN3_RPT_LEVEL_OFF   0x00

◆ ENOCEAN3_RPT_LEVEL_ONE [1/2]

#define ENOCEAN3_RPT_LEVEL_ONE   0x01

◆ ENOCEAN3_RPT_LEVEL_ONE [2/2]

#define ENOCEAN3_RPT_LEVEL_ONE   0x01

◆ ENOCEAN3_RPT_LEVEL_TWO [1/2]

#define ENOCEAN3_RPT_LEVEL_TWO   0x02

◆ ENOCEAN3_RPT_LEVEL_TWO [2/2]

#define ENOCEAN3_RPT_LEVEL_TWO   0x02

◆ ENOCEAN3_RPT_OFF [1/2]

#define ENOCEAN3_RPT_OFF   0x00

◆ ENOCEAN3_RPT_OFF [2/2]

#define ENOCEAN3_RPT_OFF   0x00

◆ ENOCEAN3_RPT_SELECTIVE [1/2]

#define ENOCEAN3_RPT_SELECTIVE   0x02

◆ ENOCEAN3_RPT_SELECTIVE [2/2]

#define ENOCEAN3_RPT_SELECTIVE   0x02

◆ ENOCEAN3_RSSI_LEVEL_100_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG   0x2E

◆ ENOCEAN3_RSSI_LEVEL_100_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG   0x2E

◆ ENOCEAN3_RSSI_LEVEL_90_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG   0x38

◆ ENOCEAN3_RSSI_LEVEL_90_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG   0x38

◆ ENOCEAN3_RSSI_LEVEL_91_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG   0x37

◆ ENOCEAN3_RSSI_LEVEL_91_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG   0x37

◆ ENOCEAN3_RSSI_LEVEL_92_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG   0x36

◆ ENOCEAN3_RSSI_LEVEL_92_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG   0x36

◆ ENOCEAN3_RSSI_LEVEL_93_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG   0x35

◆ ENOCEAN3_RSSI_LEVEL_93_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG   0x35

◆ ENOCEAN3_RSSI_LEVEL_94_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG   0x34

◆ ENOCEAN3_RSSI_LEVEL_94_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG   0x34

◆ ENOCEAN3_RSSI_LEVEL_95_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG   0x33

◆ ENOCEAN3_RSSI_LEVEL_95_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG   0x33

◆ ENOCEAN3_RSSI_LEVEL_96_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG   0x32

◆ ENOCEAN3_RSSI_LEVEL_96_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG   0x32

◆ ENOCEAN3_RSSI_LEVEL_97_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG   0x31

◆ ENOCEAN3_RSSI_LEVEL_97_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG   0x31

◆ ENOCEAN3_RSSI_LEVEL_98_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG   0x30

◆ ENOCEAN3_RSSI_LEVEL_98_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG   0x30

◆ ENOCEAN3_RSSI_LEVEL_99_DBM_NEG [1/2]

#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG   0x2F

◆ ENOCEAN3_RSSI_LEVEL_99_DBM_NEG [2/2]

#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG   0x2F

◆ ENOCEAN3_SYNC_BYTE [1/2]

#define ENOCEAN3_SYNC_BYTE   0x55

◆ ENOCEAN3_SYNC_BYTE [2/2]

#define ENOCEAN3_SYNC_BYTE   0x55

◆ ENOCEAN3_UART_RX_NOT_READY [1/2]

#define ENOCEAN3_UART_RX_NOT_READY   0x00

◆ ENOCEAN3_UART_RX_NOT_READY [2/2]

#define ENOCEAN3_UART_RX_NOT_READY   0x00

◆ ENOCEAN3_UART_RX_READY [1/2]

#define ENOCEAN3_UART_RX_READY   0x01

◆ ENOCEAN3_UART_RX_READY [2/2]

#define ENOCEAN3_UART_RX_READY   0x01