enocean4  2.0.0.0
enocean4.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN4_H
36 #define ENOCEAN4_H
37 
38 #include "drv_digital_out.h"
39 #include "drv_digital_in.h"
40 #include "drv_uart.h"
41 
42 
43 // -------------------------------------------------------------- PUBLIC MACROS
53 #define ENOCEAN4_MAP_MIKROBUS( cfg, mikrobus ) \
54  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
55  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX ); \
56  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST )
57 
64 #define ENOCEAN4_RETVAL uint8_t
65 
66 #define ENOCEAN4_OK 0x00
67 #define ENOCEAN4_INIT_ERROR 0xFF
68 
74 #define DRV_RX_BUFFER_SIZE 500
75 #define DRV_TX_BUFFER_SIZE 100
76 
79 #define ENOCEAN4_SYNC_BYTE 0x55
80 #define ENOCEAN4_MAX_BUFF_SIZE 256
81 #define ENOCEAN4_HEADER_SIZE 0x04
82 #define ENOCEAN4_BUFF_EMPTY 0x00
83 
84 #define ENOCEAN4_RESPONSE_READY 0x01
85 #define ENOCEAN4_RESPONSE_NOT_READY 0x00
86 #define ENOCEAN4_UART_RX_NOT_READY 0x00
87 #define ENOCEAN4_OK 0x00
88 #define ENOCEAN4_INVALID_PACKET_SIZE 0xFC
89 #define ENOCEAN4_CRC8D_ERROR 0xFD
90 #define ENOCEAN4_CRC8H_ERROR 0xFE
91 #define ENOCEAN4_SYNC_BYTE_ERROR 0xFF
92 
93 #define ENOCEAN4_PACK_TYPE_RADIO_ERP1 0x01
94 #define ENOCEAN4_PACK_TYPE_RESPONSE 0x02
95 #define ENOCEAN4_PACK_TYPE_RADIO_SUB_TEL 0x03
96 #define ENOCEAN4_PACK_TYPE_EVENT 0x04
97 #define ENOCEAN4_PACK_TYPE_COMMON_CMD 0x05
98 #define ENOCEAN4_PACK_TYPE_SMART_ACK_CMD 0x06
99 #define ENOCEAN4_PACK_TYPE_REMOTE_MAN_CMD 0x07
100 #define ENOCEAN4_PACK_TYPE_RADIO_MSG 0x09
101 #define ENOCEAN4_PACK_TYPE_RADIO_ERP2 0x0A
102 #define ENOCEAN4_PACK_TYPE_RADIO_802_15_4 0x10
103 #define ENOCEAN4_PACK_TYPE_CMD_2_4 0x11
104 #define ENOCEAN4_RORG_VLD 0xD2
105 #define ENOCEAN4_RORG_ADT 0xA6
106 #define ENOCEAN4_RORG_4BS 0xA5
107 #define ENOCEAN4_RET_OK 0x00
108 #define ENOCEAN4_RET_ERROR 0x01
109 #define ENOCEAN4_RET_NOT_SUPPORTED 0x02
110 #define ENOCEAN4_RET_WRONG_PARAM 0x03
111 #define ENOCEAN4_RET_OP_DENIED 0x04
112 #define ENOCEAN4_RET_LOCK_SET 0x05
113 #define ENOCEAN4_RET_BUFF_TO_SMALL 0x06
114 #define ENOCEAN4_RET_NO_FREE_BUFF 0x07
115 
116 #define ENOCEAN4_EVENT_SA_RECLAIM_NOT_SUCCESSFUL 0x01
117 #define ENOCEAN4_EVENT_SA_CONFIRM_LEARN 0x02
118 #define ENOCEAN4_EVENT_SA_LEARN_ACK 0x03
119 #define ENOCEAN4_EVENT_CO_READY 0x04
120 #define ENOCEAN4_EVENT_CO_EVENT_SECUREDEVICES 0x05
121 #define ENOCEAN4_EVENT_CO_DUTYCYCLE_LIMIT 0x06
122 #define ENOCEAN4_EVENT_CO_TRANSMIT_FAILED 0x07
123 #define ENOCEAN4_CMD_CO_WR_SLEEP 0x01
124 #define ENOCEAN4_CMD_CO_WR_RESET 0x02
125 #define ENOCEAN4_CMD_CO_RD_VERSION 0x03
126 #define ENOCEAN4_CMD_CO_RD_SYS_LOG 0x04
127 #define ENOCEAN4_CMD_CO_WR_SYS_LOG 0x05
128 #define ENOCEAN4_CMD_CO_WR_BIST 0x06
129 #define ENOCEAN4_CMD_CO_WR_IDBASE 0x07
130 #define ENOCEAN4_CMD_CO_RD_IDBASE 0x08
131 #define ENOCEAN4_CMD_CO_WR_REPEATER 0x09
132 #define ENOCEAN4_CMD_CO_RD_REPEATER 0x0A
133 #define ENOCEAN4_CMD_CO_WR_FILTER_ADD 0x0B
134 #define ENOCEAN4_CMD_CO_WR_FILTER_DEL 0x0C
135 #define ENOCEAN4_CMD_CO_WR_FILTER_DEL_ALL 0x0D
136 #define ENOCEAN4_CMD_CO_WR_FILTER_ENABLE 0x0E
137 #define ENOCEAN4_CMD_CO_RD_FILTER 0x0F
138 #define ENOCEAN4_CMD_CO_WR_WAIT_MATURITY 0x10
139 #define ENOCEAN4_CMD_CO_WR_SUBTEL 0x11
140 #define ENOCEAN4_CMD_CO_WR_MEM 0x12
141 #define ENOCEAN4_CMD_CO_RD_MEM 0x13
142 #define ENOCEAN4_CMD_CO_RD_MEM_ADDRESS 0x14
143 #define ENOCEAN4_CMD_CO_RD_SECURITY 0x15
144 #define ENOCEAN4_CMD_CO_WR_SECURITY 0x16
145 #define ENOCEAN4_CMD_CO_WR_LEARNMODE 0x17
146 #define ENOCEAN4_CMD_CO_RD_LEARNMODE 0x18
147 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD 0x19
148 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_DEL 0x1A
149 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_INDEX 0x1B
150 #define ENOCEAN4_CMD_CO_WR_MODE 0x1C
151 #define ENOCEAN4_CMD_CO_RD_NUMSECUREDEVICES 0x1D
152 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_ID 0x1E
153 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD_PSK 0x1F
154 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_SENDTEACHIN 0x20
155 #define ENOCEAN4_CMD_CO_WR_TEMPORARY_RLC_WINDOW 0x21
156 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_PSK 0x22
157 #define ENOCEAN4_CMD_CO_RD_DUTYCYCLE_LIMIT 0x23
158 #define ENOCEAN4_CMD_CO_SET_BAUDRATE 0x24
159 #define ENOCEAN4_CMD_CO_GET_FREQUENCY_INFO 0x25
160 #define ENOCEAN4_CMD_CO_GET_STEPCODE 0x27
161 #define ENOCEAN4_CMD_CO_WR_REMAN_CODE 0x2E
162 #define ENOCEAN4_CMD_CO_WR_STARTUP_DELAY 0x2F
163 #define ENOCEAN4_CMD_CO_WR_REMAN_REPEATING 0x30
164 #define ENOCEAN4_CMD_CO_RD_REMAN_REPEATING 0x31
165 #define ENOCEAN4_CMD_CO_SET_NOISETHRESHOLD 0x32
166 #define ENOCEAN4_CMD_CO_GET_NOISETHRESHOLD 0x33
167 #define ENOCEAN4_SA_WR_LEARNMODE 0x01
168 #define ENOCEAN4_SA_RD_LEARNMODE 0x02
169 #define ENOCEAN4_SA_WR_LEARNCONFIRM 0x03
170 #define ENOCEAN4_SA_WR_CLIENTLEARNRQ 0x04
171 #define ENOCEAN4_SA_WR_RESET 0x05
172 #define ENOCEAN4_SA_RD_LEARNEDCLIENTS 0x06
173 #define ENOCEAN4_SA_WR_RECLAIMS 0x07
174 #define ENOCEAN4_SA_WR_POSTMASTER 0x08
175 #define ENOCEAN4_SA_RD_MAILBOX_STATUS 0x09
176 #define ENOCEAN4_SA_DEL_MAILBOX 0x0A
177 #define ENOCEAN4_R820_RD_CHANNEL 0x02
178 #define ENOCEAN4_R802_WR_CHANNEL 0x01
179 
180 #define ENOCEAN4_57600_BAUDRATE 0x00
181 #define ENOCEAN4_115200_BAUDRATE 0x01
182 #define ENOCEAN4_230400_BAUDRATE 0x02
183 #define ENOCEAN4_460800_BAUDRATE 0x03
184 #define ENOCEAN4_COMPATIBLE_MODE_ERP1 0x00
185 #define ENOCEAN4_ADVANCED_MODE_ERP2 0x01
186 #define ENOCEAN4_ENABLE 0x01
187 #define ENOCEAN4_DISABLE 0x00
188 #define ENOCEAN4_FILTER_TYPE_DEV_ID 0x00
189 #define ENOCEAN4_FILTER_TYPE_RORG 0x01
190 #define ENOCEAN4_FILTER_TYPE_DBM 0x02
191 #define ENOCEAN4_FILTER_TYPE_DEST_ID 0x03
192 #define ENOCEAN4_BLOCK_RADIO_INTER 0x00
193 #define ENOCEAN4_APPLY_RADIO_INTER 0x80
194 #define ENOCEAN4_BLOCK_FILTERED_RPT 0x40
195 #define ENOCEAN4_APPLY_FILTERED_RPT 0xC0
196 #define ENOCEAN4_RPT_OFF 0x00
197 #define ENOCEAN4_RPT_ON_ALL 0x01
198 #define ENOCEAN4_RPT_ON_FILTERED 0x02
199 #define ENOCEAN4_RPT_LEVEL_1 0x01
200 #define ENOCEAN4_RPT_LEVEL_2 0x02
201  // End group macro
203 // --------------------------------------------------------------- PUBLIC TYPES
208 typedef struct {
209 
210  uint16_t data_length;
211  uint8_t opt_length;
212  uint8_t packet_type;
213  uint8_t data_buff[ 256 ];
214 
216 
217 typedef void ( *enocean4_hdl_t )( enocean4_packet_t*, uint8_t* );
221 typedef struct
222 {
223  // Output pins
224 
225  digital_out_t rst;
226 
227  // Modules
228 
229  uart_t uart;
230 
231  char uart_rx_buffer[ DRV_RX_BUFFER_SIZE ];
232  char uart_tx_buffer[ DRV_TX_BUFFER_SIZE ];
233 
235  uint8_t response_ready;
236  uint8_t rx_dat[ 270 ];
237 
238 } enocean4_t;
239 
243 typedef struct
244 {
245  // Communication gpio pins
246 
247  pin_name_t rx_pin;
248  pin_name_t tx_pin;
249 
250  // Additional gpio pins
251 
252  pin_name_t rst;
253 
254  // static variable
255 
256  uint32_t baud_rate; // Clock speed.
258  uart_data_bits_t data_bit; // Data bits.
259  uart_parity_t parity_bit; // Parity bit.
260  uart_stop_bits_t stop_bit; // Stop bits.
261 
262 
264 
268 typedef uint8_t enocean4_error_t;
269  // End types group
271 
272 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
273 
279 #ifdef __cplusplus
280 extern "C"{
281 #endif
282 
292 
301 
309 void enocean4_set_rst_pin ( enocean4_t *ctx, uint8_t state );
310 
319 void enocean4_generic_write ( enocean4_t *ctx, char *data_buf, uint16_t len );
320 
330 int32_t enocean4_generic_read ( enocean4_t *ctx, char *data_buf, uint16_t max_len );
331 
341 void enocean4_response_handler_set( enocean4_t *ctx, void ( *handler )( enocean4_packet_t*, uint8_t* ) );
342 
351 
360 uint8_t enocean4_process ( enocean4_t *ctx );
361 
371 
380 
393 
394 #ifdef __cplusplus
395 }
396 #endif
397 #endif // _ENOCEAN4_H_
398  // End public_function group
401 
402 // ------------------------------------------------------------------------- END
enocean4_response_ready
uint8_t enocean4_response_ready(enocean4_t *ctx)
Response Ready Check function.
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocean4.h:74
enocean4_cfg_t::rst
pin_name_t rst
Definition: enocean4.h:252
enocean4_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocean4.h:248
enocean4_t::rst
digital_out_t rst
Definition: enocean4.h:225
enocean4_uart_isr
void enocean4_uart_isr(enocean4_t *ctx)
UART Interrupt Routine function.
enocean4_t::driver_hdl
enocean4_hdl_t driver_hdl
Definition: enocean4.h:234
enocean4_cfg_t
Click configuration structure definition.
Definition: enocean4.h:244
enocean4_packet_t::opt_length
uint8_t opt_length
Definition: enocean4.h:211
enocean4_process
uint8_t enocean4_process(enocean4_t *ctx)
Response Proccesing function.
enocean4_error_t
uint8_t enocean4_error_t
Error type.
Definition: enocean4.h:268
enocean4_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocean4.h:247
enocean4_packet_t
Definition: enocean4.h:208
enocean4_packet_t::packet_type
uint8_t packet_type
Definition: enocean4.h:212
enocean4_cfg_t::uart_blocking
bool uart_blocking
Definition: enocean4.h:257
enocean4_hdl_t
void(* enocean4_hdl_t)(enocean4_packet_t *, uint8_t *)
Definition: enocean4.h:217
enocean4_cfg_setup
void enocean4_cfg_setup(enocean4_cfg_t *cfg)
Config Object Initialization function.
enocean4_t::uart
uart_t uart
Definition: enocean4.h:229
enocean4_init
ENOCEAN4_RETVAL enocean4_init(enocean4_t *ctx, enocean4_cfg_t *cfg)
Initialization function.
enocean4_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocean4.h:259
enocean4_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocean4.h:260
enocean4_generic_read
int32_t enocean4_generic_read(enocean4_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocean4_set_rst_pin
void enocean4_set_rst_pin(enocean4_t *ctx, uint8_t state)
Set RST ( reset ) pin state.
enocean4_generic_write
void enocean4_generic_write(enocean4_t *ctx, char *data_buf, uint16_t len)
Generic write function.
enocean4_send_packet
uint8_t enocean4_send_packet(enocean4_t *ctx, enocean4_packet_t *packet)
Packet Send function.
DRV_TX_BUFFER_SIZE
#define DRV_TX_BUFFER_SIZE
Definition: enocean4.h:75
enocean4_packet_t::data_length
uint16_t data_length
Definition: enocean4.h:210
enocean4_t::response_ready
uint8_t response_ready
Definition: enocean4.h:235
enocean4_response_handler_set
void enocean4_response_handler_set(enocean4_t *ctx, void(*handler)(enocean4_packet_t *, uint8_t *))
Handler Set function.
ENOCEAN4_RETVAL
#define ENOCEAN4_RETVAL
Definition: enocean4.h:64
enocean4_reset
void enocean4_reset(enocean4_t *ctx)
Reset function.
enocean4_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocean4.h:258
enocean4_t
Click ctx object definition.
Definition: enocean4.h:222
enocean4_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocean4.h:256