enocean4  2.0.0.0
enocean4.h
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1 /*
2  * MikroSDK - MikroE Software Development Kit
3  * Copyright© 2020 MikroElektronika d.o.o.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
7  * files (the "Software"), to deal in the Software without restriction,
8  * including without limitation the rights to use, copy, modify, merge,
9  * publish, distribute, sublicense, and/or sell copies of the Software,
10  * and to permit persons to whom the Software is furnished to do so,
11  * subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22  * OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
33 // ----------------------------------------------------------------------------
34 
35 #ifndef ENOCEAN4_H
36 #define ENOCEAN4_H
37 
38 #include "mikrosdk_version.h"
39 
40 #ifdef __GNUC__
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
43 #else
44 #include "delays.h"
45 #endif
46 #endif
47 
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_uart.h"
51 
52 
53 // -------------------------------------------------------------- PUBLIC MACROS
63 #define ENOCEAN4_MAP_MIKROBUS( cfg, mikrobus ) \
64  cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
65  cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX ); \
66  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST )
67 
74 #define ENOCEAN4_RETVAL uint8_t
75 
76 #define ENOCEAN4_OK 0x00
77 #define ENOCEAN4_INIT_ERROR 0xFF
78 
84 #define DRV_RX_BUFFER_SIZE 500
85 #define DRV_TX_BUFFER_SIZE 100
86 
89 #define ENOCEAN4_SYNC_BYTE 0x55
90 #define ENOCEAN4_MAX_BUFF_SIZE 256
91 #define ENOCEAN4_HEADER_SIZE 0x04
92 #define ENOCEAN4_BUFF_EMPTY 0x00
93 
94 #define ENOCEAN4_RESPONSE_READY 0x01
95 #define ENOCEAN4_RESPONSE_NOT_READY 0x00
96 #define ENOCEAN4_UART_RX_NOT_READY 0x00
97 #define ENOCEAN4_OK 0x00
98 #define ENOCEAN4_INVALID_PACKET_SIZE 0xFC
99 #define ENOCEAN4_CRC8D_ERROR 0xFD
100 #define ENOCEAN4_CRC8H_ERROR 0xFE
101 #define ENOCEAN4_SYNC_BYTE_ERROR 0xFF
102 
103 #define ENOCEAN4_PACK_TYPE_RADIO_ERP1 0x01
104 #define ENOCEAN4_PACK_TYPE_RESPONSE 0x02
105 #define ENOCEAN4_PACK_TYPE_RADIO_SUB_TEL 0x03
106 #define ENOCEAN4_PACK_TYPE_EVENT 0x04
107 #define ENOCEAN4_PACK_TYPE_COMMON_CMD 0x05
108 #define ENOCEAN4_PACK_TYPE_SMART_ACK_CMD 0x06
109 #define ENOCEAN4_PACK_TYPE_REMOTE_MAN_CMD 0x07
110 #define ENOCEAN4_PACK_TYPE_RADIO_MSG 0x09
111 #define ENOCEAN4_PACK_TYPE_RADIO_ERP2 0x0A
112 #define ENOCEAN4_PACK_TYPE_RADIO_802_15_4 0x10
113 #define ENOCEAN4_PACK_TYPE_CMD_2_4 0x11
114 #define ENOCEAN4_RORG_VLD 0xD2
115 #define ENOCEAN4_RORG_ADT 0xA6
116 #define ENOCEAN4_RORG_4BS 0xA5
117 #define ENOCEAN4_RET_OK 0x00
118 #define ENOCEAN4_RET_ERROR 0x01
119 #define ENOCEAN4_RET_NOT_SUPPORTED 0x02
120 #define ENOCEAN4_RET_WRONG_PARAM 0x03
121 #define ENOCEAN4_RET_OP_DENIED 0x04
122 #define ENOCEAN4_RET_LOCK_SET 0x05
123 #define ENOCEAN4_RET_BUFF_TO_SMALL 0x06
124 #define ENOCEAN4_RET_NO_FREE_BUFF 0x07
125 
126 #define ENOCEAN4_EVENT_SA_RECLAIM_NOT_SUCCESSFUL 0x01
127 #define ENOCEAN4_EVENT_SA_CONFIRM_LEARN 0x02
128 #define ENOCEAN4_EVENT_SA_LEARN_ACK 0x03
129 #define ENOCEAN4_EVENT_CO_READY 0x04
130 #define ENOCEAN4_EVENT_CO_EVENT_SECUREDEVICES 0x05
131 #define ENOCEAN4_EVENT_CO_DUTYCYCLE_LIMIT 0x06
132 #define ENOCEAN4_EVENT_CO_TRANSMIT_FAILED 0x07
133 #define ENOCEAN4_CMD_CO_WR_SLEEP 0x01
134 #define ENOCEAN4_CMD_CO_WR_RESET 0x02
135 #define ENOCEAN4_CMD_CO_RD_VERSION 0x03
136 #define ENOCEAN4_CMD_CO_RD_SYS_LOG 0x04
137 #define ENOCEAN4_CMD_CO_WR_SYS_LOG 0x05
138 #define ENOCEAN4_CMD_CO_WR_BIST 0x06
139 #define ENOCEAN4_CMD_CO_WR_IDBASE 0x07
140 #define ENOCEAN4_CMD_CO_RD_IDBASE 0x08
141 #define ENOCEAN4_CMD_CO_WR_REPEATER 0x09
142 #define ENOCEAN4_CMD_CO_RD_REPEATER 0x0A
143 #define ENOCEAN4_CMD_CO_WR_FILTER_ADD 0x0B
144 #define ENOCEAN4_CMD_CO_WR_FILTER_DEL 0x0C
145 #define ENOCEAN4_CMD_CO_WR_FILTER_DEL_ALL 0x0D
146 #define ENOCEAN4_CMD_CO_WR_FILTER_ENABLE 0x0E
147 #define ENOCEAN4_CMD_CO_RD_FILTER 0x0F
148 #define ENOCEAN4_CMD_CO_WR_WAIT_MATURITY 0x10
149 #define ENOCEAN4_CMD_CO_WR_SUBTEL 0x11
150 #define ENOCEAN4_CMD_CO_WR_MEM 0x12
151 #define ENOCEAN4_CMD_CO_RD_MEM 0x13
152 #define ENOCEAN4_CMD_CO_RD_MEM_ADDRESS 0x14
153 #define ENOCEAN4_CMD_CO_RD_SECURITY 0x15
154 #define ENOCEAN4_CMD_CO_WR_SECURITY 0x16
155 #define ENOCEAN4_CMD_CO_WR_LEARNMODE 0x17
156 #define ENOCEAN4_CMD_CO_RD_LEARNMODE 0x18
157 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD 0x19
158 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_DEL 0x1A
159 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_INDEX 0x1B
160 #define ENOCEAN4_CMD_CO_WR_MODE 0x1C
161 #define ENOCEAN4_CMD_CO_RD_NUMSECUREDEVICES 0x1D
162 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_ID 0x1E
163 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD_PSK 0x1F
164 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_SENDTEACHIN 0x20
165 #define ENOCEAN4_CMD_CO_WR_TEMPORARY_RLC_WINDOW 0x21
166 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_PSK 0x22
167 #define ENOCEAN4_CMD_CO_RD_DUTYCYCLE_LIMIT 0x23
168 #define ENOCEAN4_CMD_CO_SET_BAUDRATE 0x24
169 #define ENOCEAN4_CMD_CO_GET_FREQUENCY_INFO 0x25
170 #define ENOCEAN4_CMD_CO_GET_STEPCODE 0x27
171 #define ENOCEAN4_CMD_CO_WR_REMAN_CODE 0x2E
172 #define ENOCEAN4_CMD_CO_WR_STARTUP_DELAY 0x2F
173 #define ENOCEAN4_CMD_CO_WR_REMAN_REPEATING 0x30
174 #define ENOCEAN4_CMD_CO_RD_REMAN_REPEATING 0x31
175 #define ENOCEAN4_CMD_CO_SET_NOISETHRESHOLD 0x32
176 #define ENOCEAN4_CMD_CO_GET_NOISETHRESHOLD 0x33
177 #define ENOCEAN4_SA_WR_LEARNMODE 0x01
178 #define ENOCEAN4_SA_RD_LEARNMODE 0x02
179 #define ENOCEAN4_SA_WR_LEARNCONFIRM 0x03
180 #define ENOCEAN4_SA_WR_CLIENTLEARNRQ 0x04
181 #define ENOCEAN4_SA_WR_RESET 0x05
182 #define ENOCEAN4_SA_RD_LEARNEDCLIENTS 0x06
183 #define ENOCEAN4_SA_WR_RECLAIMS 0x07
184 #define ENOCEAN4_SA_WR_POSTMASTER 0x08
185 #define ENOCEAN4_SA_RD_MAILBOX_STATUS 0x09
186 #define ENOCEAN4_SA_DEL_MAILBOX 0x0A
187 #define ENOCEAN4_R820_RD_CHANNEL 0x02
188 #define ENOCEAN4_R802_WR_CHANNEL 0x01
189 
190 #define ENOCEAN4_57600_BAUDRATE 0x00
191 #define ENOCEAN4_115200_BAUDRATE 0x01
192 #define ENOCEAN4_230400_BAUDRATE 0x02
193 #define ENOCEAN4_460800_BAUDRATE 0x03
194 #define ENOCEAN4_COMPATIBLE_MODE_ERP1 0x00
195 #define ENOCEAN4_ADVANCED_MODE_ERP2 0x01
196 #define ENOCEAN4_ENABLE 0x01
197 #define ENOCEAN4_DISABLE 0x00
198 #define ENOCEAN4_FILTER_TYPE_DEV_ID 0x00
199 #define ENOCEAN4_FILTER_TYPE_RORG 0x01
200 #define ENOCEAN4_FILTER_TYPE_DBM 0x02
201 #define ENOCEAN4_FILTER_TYPE_DEST_ID 0x03
202 #define ENOCEAN4_BLOCK_RADIO_INTER 0x00
203 #define ENOCEAN4_APPLY_RADIO_INTER 0x80
204 #define ENOCEAN4_BLOCK_FILTERED_RPT 0x40
205 #define ENOCEAN4_APPLY_FILTERED_RPT 0xC0
206 #define ENOCEAN4_RPT_OFF 0x00
207 #define ENOCEAN4_RPT_ON_ALL 0x01
208 #define ENOCEAN4_RPT_ON_FILTERED 0x02
209 #define ENOCEAN4_RPT_LEVEL_1 0x01
210 #define ENOCEAN4_RPT_LEVEL_2 0x02
211  // End group macro
213 // --------------------------------------------------------------- PUBLIC TYPES
218 typedef struct {
219 
220  uint16_t data_length;
221  uint8_t opt_length;
222  uint8_t packet_type;
223  uint8_t data_buff[ 256 ];
224 
226 
227 typedef void ( *enocean4_hdl_t )( enocean4_packet_t*, uint8_t* );
231 typedef struct
232 {
233  // Output pins
234 
235  digital_out_t rst;
236 
237  // Modules
238 
239  uart_t uart;
240 
241  char uart_rx_buffer[ DRV_RX_BUFFER_SIZE ];
242  char uart_tx_buffer[ DRV_TX_BUFFER_SIZE ];
243 
245  uint8_t response_ready;
246  uint8_t rx_dat[ 270 ];
247 
248 } enocean4_t;
249 
253 typedef struct
254 {
255  // Communication gpio pins
256 
257  pin_name_t rx_pin;
258  pin_name_t tx_pin;
259 
260  // Additional gpio pins
261 
262  pin_name_t rst;
263 
264  // static variable
265 
266  uint32_t baud_rate; // Clock speed.
268  uart_data_bits_t data_bit; // Data bits.
269  uart_parity_t parity_bit; // Parity bit.
270  uart_stop_bits_t stop_bit; // Stop bits.
271 
272 
274 
278 typedef uint8_t enocean4_error_t;
279  // End types group
281 
282 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
283 
289 #ifdef __cplusplus
290 extern "C"{
291 #endif
292 
302 
311 
319 void enocean4_set_rst_pin ( enocean4_t *ctx, uint8_t state );
320 
329 void enocean4_generic_write ( enocean4_t *ctx, char *data_buf, uint16_t len );
330 
340 int32_t enocean4_generic_read ( enocean4_t *ctx, char *data_buf, uint16_t max_len );
341 
351 void enocean4_response_handler_set( enocean4_t *ctx, void ( *handler )( enocean4_packet_t*, uint8_t* ) );
352 
361 
370 uint8_t enocean4_process ( enocean4_t *ctx );
371 
381 
390 
403 
404 #ifdef __cplusplus
405 }
406 #endif
407 #endif // _ENOCEAN4_H_
408  // End public_function group
411 
412 // ------------------------------------------------------------------------- END
enocean4_response_ready
uint8_t enocean4_response_ready(enocean4_t *ctx)
Response Ready Check function.
DRV_RX_BUFFER_SIZE
#define DRV_RX_BUFFER_SIZE
Definition: enocean4.h:84
enocean4_cfg_t::rst
pin_name_t rst
Definition: enocean4.h:262
enocean4_cfg_t::tx_pin
pin_name_t tx_pin
Definition: enocean4.h:258
enocean4_t::rst
digital_out_t rst
Definition: enocean4.h:235
enocean4_uart_isr
void enocean4_uart_isr(enocean4_t *ctx)
UART Interrupt Routine function.
enocean4_t::driver_hdl
enocean4_hdl_t driver_hdl
Definition: enocean4.h:244
enocean4_cfg_t
Click configuration structure definition.
Definition: enocean4.h:254
enocean4_packet_t::opt_length
uint8_t opt_length
Definition: enocean4.h:221
enocean4_process
uint8_t enocean4_process(enocean4_t *ctx)
Response Proccesing function.
enocean4_error_t
uint8_t enocean4_error_t
Error type.
Definition: enocean4.h:278
enocean4_cfg_t::rx_pin
pin_name_t rx_pin
Definition: enocean4.h:257
enocean4_packet_t
Definition: enocean4.h:218
enocean4_packet_t::packet_type
uint8_t packet_type
Definition: enocean4.h:222
enocean4_cfg_t::uart_blocking
bool uart_blocking
Definition: enocean4.h:267
enocean4_hdl_t
void(* enocean4_hdl_t)(enocean4_packet_t *, uint8_t *)
Definition: enocean4.h:227
enocean4_cfg_setup
void enocean4_cfg_setup(enocean4_cfg_t *cfg)
Config Object Initialization function.
enocean4_t::uart
uart_t uart
Definition: enocean4.h:239
enocean4_init
ENOCEAN4_RETVAL enocean4_init(enocean4_t *ctx, enocean4_cfg_t *cfg)
Initialization function.
enocean4_cfg_t::parity_bit
uart_parity_t parity_bit
Definition: enocean4.h:269
enocean4_cfg_t::stop_bit
uart_stop_bits_t stop_bit
Definition: enocean4.h:270
enocean4_generic_read
int32_t enocean4_generic_read(enocean4_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
enocean4_set_rst_pin
void enocean4_set_rst_pin(enocean4_t *ctx, uint8_t state)
Set RST ( reset ) pin state.
enocean4_generic_write
void enocean4_generic_write(enocean4_t *ctx, char *data_buf, uint16_t len)
Generic write function.
enocean4_send_packet
uint8_t enocean4_send_packet(enocean4_t *ctx, enocean4_packet_t *packet)
Packet Send function.
DRV_TX_BUFFER_SIZE
#define DRV_TX_BUFFER_SIZE
Definition: enocean4.h:85
enocean4_packet_t::data_length
uint16_t data_length
Definition: enocean4.h:220
enocean4_t::response_ready
uint8_t response_ready
Definition: enocean4.h:245
enocean4_response_handler_set
void enocean4_response_handler_set(enocean4_t *ctx, void(*handler)(enocean4_packet_t *, uint8_t *))
Handler Set function.
ENOCEAN4_RETVAL
#define ENOCEAN4_RETVAL
Definition: enocean4.h:74
enocean4_reset
void enocean4_reset(enocean4_t *ctx)
Reset function.
enocean4_cfg_t::data_bit
uart_data_bits_t data_bit
Definition: enocean4.h:268
enocean4_t
Click ctx object definition.
Definition: enocean4.h:232
enocean4_cfg_t::baud_rate
uint32_t baud_rate
Definition: enocean4.h:266