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42 #ifdef PREINIT_SUPPORTED
46 #ifdef MikroCCoreVersion
47 #if MikroCCoreVersion >= 1
52 #include "drv_digital_out.h"
53 #include "drv_digital_in.h"
67 #define ENOCEAN4_MAP_MIKROBUS( cfg, mikrobus ) \
68 cfg.tx_pin = MIKROBUS( mikrobus, MIKROBUS_TX ); \
69 cfg.rx_pin = MIKROBUS( mikrobus, MIKROBUS_RX ); \
70 cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST )
78 #define ENOCEAN4_RETVAL uint8_t
80 #define ENOCEAN4_OK 0x00
81 #define ENOCEAN4_INIT_ERROR 0xFF
88 #define DRV_RX_BUFFER_SIZE 500
89 #define DRV_TX_BUFFER_SIZE 100
93 #define ENOCEAN4_SYNC_BYTE 0x55
94 #define ENOCEAN4_MAX_BUFF_SIZE 256
95 #define ENOCEAN4_HEADER_SIZE 0x04
96 #define ENOCEAN4_BUFF_EMPTY 0x00
98 #define ENOCEAN4_RESPONSE_READY 0x01
99 #define ENOCEAN4_RESPONSE_NOT_READY 0x00
100 #define ENOCEAN4_UART_RX_NOT_READY 0x00
101 #define ENOCEAN4_OK 0x00
102 #define ENOCEAN4_INVALID_PACKET_SIZE 0xFC
103 #define ENOCEAN4_CRC8D_ERROR 0xFD
104 #define ENOCEAN4_CRC8H_ERROR 0xFE
105 #define ENOCEAN4_SYNC_BYTE_ERROR 0xFF
107 #define ENOCEAN4_PACK_TYPE_RADIO_ERP1 0x01
108 #define ENOCEAN4_PACK_TYPE_RESPONSE 0x02
109 #define ENOCEAN4_PACK_TYPE_RADIO_SUB_TEL 0x03
110 #define ENOCEAN4_PACK_TYPE_EVENT 0x04
111 #define ENOCEAN4_PACK_TYPE_COMMON_CMD 0x05
112 #define ENOCEAN4_PACK_TYPE_SMART_ACK_CMD 0x06
113 #define ENOCEAN4_PACK_TYPE_REMOTE_MAN_CMD 0x07
114 #define ENOCEAN4_PACK_TYPE_RADIO_MSG 0x09
115 #define ENOCEAN4_PACK_TYPE_RADIO_ERP2 0x0A
116 #define ENOCEAN4_PACK_TYPE_RADIO_802_15_4 0x10
117 #define ENOCEAN4_PACK_TYPE_CMD_2_4 0x11
118 #define ENOCEAN4_RORG_VLD 0xD2
119 #define ENOCEAN4_RORG_ADT 0xA6
120 #define ENOCEAN4_RORG_4BS 0xA5
121 #define ENOCEAN4_RET_OK 0x00
122 #define ENOCEAN4_RET_ERROR 0x01
123 #define ENOCEAN4_RET_NOT_SUPPORTED 0x02
124 #define ENOCEAN4_RET_WRONG_PARAM 0x03
125 #define ENOCEAN4_RET_OP_DENIED 0x04
126 #define ENOCEAN4_RET_LOCK_SET 0x05
127 #define ENOCEAN4_RET_BUFF_TO_SMALL 0x06
128 #define ENOCEAN4_RET_NO_FREE_BUFF 0x07
130 #define ENOCEAN4_EVENT_SA_RECLAIM_NOT_SUCCESSFUL 0x01
131 #define ENOCEAN4_EVENT_SA_CONFIRM_LEARN 0x02
132 #define ENOCEAN4_EVENT_SA_LEARN_ACK 0x03
133 #define ENOCEAN4_EVENT_CO_READY 0x04
134 #define ENOCEAN4_EVENT_CO_EVENT_SECUREDEVICES 0x05
135 #define ENOCEAN4_EVENT_CO_DUTYCYCLE_LIMIT 0x06
136 #define ENOCEAN4_EVENT_CO_TRANSMIT_FAILED 0x07
137 #define ENOCEAN4_CMD_CO_WR_SLEEP 0x01
138 #define ENOCEAN4_CMD_CO_WR_RESET 0x02
139 #define ENOCEAN4_CMD_CO_RD_VERSION 0x03
140 #define ENOCEAN4_CMD_CO_RD_SYS_LOG 0x04
141 #define ENOCEAN4_CMD_CO_WR_SYS_LOG 0x05
142 #define ENOCEAN4_CMD_CO_WR_BIST 0x06
143 #define ENOCEAN4_CMD_CO_WR_IDBASE 0x07
144 #define ENOCEAN4_CMD_CO_RD_IDBASE 0x08
145 #define ENOCEAN4_CMD_CO_WR_REPEATER 0x09
146 #define ENOCEAN4_CMD_CO_RD_REPEATER 0x0A
147 #define ENOCEAN4_CMD_CO_WR_FILTER_ADD 0x0B
148 #define ENOCEAN4_CMD_CO_WR_FILTER_DEL 0x0C
149 #define ENOCEAN4_CMD_CO_WR_FILTER_DEL_ALL 0x0D
150 #define ENOCEAN4_CMD_CO_WR_FILTER_ENABLE 0x0E
151 #define ENOCEAN4_CMD_CO_RD_FILTER 0x0F
152 #define ENOCEAN4_CMD_CO_WR_WAIT_MATURITY 0x10
153 #define ENOCEAN4_CMD_CO_WR_SUBTEL 0x11
154 #define ENOCEAN4_CMD_CO_WR_MEM 0x12
155 #define ENOCEAN4_CMD_CO_RD_MEM 0x13
156 #define ENOCEAN4_CMD_CO_RD_MEM_ADDRESS 0x14
157 #define ENOCEAN4_CMD_CO_RD_SECURITY 0x15
158 #define ENOCEAN4_CMD_CO_WR_SECURITY 0x16
159 #define ENOCEAN4_CMD_CO_WR_LEARNMODE 0x17
160 #define ENOCEAN4_CMD_CO_RD_LEARNMODE 0x18
161 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD 0x19
162 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_DEL 0x1A
163 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_INDEX 0x1B
164 #define ENOCEAN4_CMD_CO_WR_MODE 0x1C
165 #define ENOCEAN4_CMD_CO_RD_NUMSECUREDEVICES 0x1D
166 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_ID 0x1E
167 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD_PSK 0x1F
168 #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_SENDTEACHIN 0x20
169 #define ENOCEAN4_CMD_CO_WR_TEMPORARY_RLC_WINDOW 0x21
170 #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_PSK 0x22
171 #define ENOCEAN4_CMD_CO_RD_DUTYCYCLE_LIMIT 0x23
172 #define ENOCEAN4_CMD_CO_SET_BAUDRATE 0x24
173 #define ENOCEAN4_CMD_CO_GET_FREQUENCY_INFO 0x25
174 #define ENOCEAN4_CMD_CO_GET_STEPCODE 0x27
175 #define ENOCEAN4_CMD_CO_WR_REMAN_CODE 0x2E
176 #define ENOCEAN4_CMD_CO_WR_STARTUP_DELAY 0x2F
177 #define ENOCEAN4_CMD_CO_WR_REMAN_REPEATING 0x30
178 #define ENOCEAN4_CMD_CO_RD_REMAN_REPEATING 0x31
179 #define ENOCEAN4_CMD_CO_SET_NOISETHRESHOLD 0x32
180 #define ENOCEAN4_CMD_CO_GET_NOISETHRESHOLD 0x33
181 #define ENOCEAN4_SA_WR_LEARNMODE 0x01
182 #define ENOCEAN4_SA_RD_LEARNMODE 0x02
183 #define ENOCEAN4_SA_WR_LEARNCONFIRM 0x03
184 #define ENOCEAN4_SA_WR_CLIENTLEARNRQ 0x04
185 #define ENOCEAN4_SA_WR_RESET 0x05
186 #define ENOCEAN4_SA_RD_LEARNEDCLIENTS 0x06
187 #define ENOCEAN4_SA_WR_RECLAIMS 0x07
188 #define ENOCEAN4_SA_WR_POSTMASTER 0x08
189 #define ENOCEAN4_SA_RD_MAILBOX_STATUS 0x09
190 #define ENOCEAN4_SA_DEL_MAILBOX 0x0A
191 #define ENOCEAN4_R820_RD_CHANNEL 0x02
192 #define ENOCEAN4_R802_WR_CHANNEL 0x01
194 #define ENOCEAN4_57600_BAUDRATE 0x00
195 #define ENOCEAN4_115200_BAUDRATE 0x01
196 #define ENOCEAN4_230400_BAUDRATE 0x02
197 #define ENOCEAN4_460800_BAUDRATE 0x03
198 #define ENOCEAN4_COMPATIBLE_MODE_ERP1 0x00
199 #define ENOCEAN4_ADVANCED_MODE_ERP2 0x01
200 #define ENOCEAN4_ENABLE 0x01
201 #define ENOCEAN4_DISABLE 0x00
202 #define ENOCEAN4_FILTER_TYPE_DEV_ID 0x00
203 #define ENOCEAN4_FILTER_TYPE_RORG 0x01
204 #define ENOCEAN4_FILTER_TYPE_DBM 0x02
205 #define ENOCEAN4_FILTER_TYPE_DEST_ID 0x03
206 #define ENOCEAN4_BLOCK_RADIO_INTER 0x00
207 #define ENOCEAN4_APPLY_RADIO_INTER 0x80
208 #define ENOCEAN4_BLOCK_FILTERED_RPT 0x40
209 #define ENOCEAN4_APPLY_FILTERED_RPT 0xC0
210 #define ENOCEAN4_RPT_OFF 0x00
211 #define ENOCEAN4_RPT_ON_ALL 0x01
212 #define ENOCEAN4_RPT_ON_FILTERED 0x02
213 #define ENOCEAN4_RPT_LEVEL_1 0x01
214 #define ENOCEAN4_RPT_LEVEL_2 0x02
227 uint8_t data_buff[ 256 ];
250 uint8_t rx_dat[ 270 ];
411 #endif // _ENOCEAN4_H_
uint8_t enocean4_response_ready(enocean4_t *ctx)
Response Ready Check function.
#define DRV_RX_BUFFER_SIZE
Definition: enocean4.h:88
pin_name_t rst
Definition: enocean4.h:266
pin_name_t tx_pin
Definition: enocean4.h:262
digital_out_t rst
Definition: enocean4.h:239
void enocean4_uart_isr(enocean4_t *ctx)
UART Interrupt Routine function.
enocean4_hdl_t driver_hdl
Definition: enocean4.h:248
Click configuration structure definition.
Definition: enocean4.h:258
uint8_t opt_length
Definition: enocean4.h:225
uint8_t enocean4_process(enocean4_t *ctx)
Response Proccesing function.
uint8_t enocean4_error_t
Error type.
Definition: enocean4.h:282
pin_name_t rx_pin
Definition: enocean4.h:261
Definition: enocean4.h:222
uint8_t packet_type
Definition: enocean4.h:226
bool uart_blocking
Definition: enocean4.h:271
void(* enocean4_hdl_t)(enocean4_packet_t *, uint8_t *)
Definition: enocean4.h:231
void enocean4_cfg_setup(enocean4_cfg_t *cfg)
Config Object Initialization function.
uart_t uart
Definition: enocean4.h:243
ENOCEAN4_RETVAL enocean4_init(enocean4_t *ctx, enocean4_cfg_t *cfg)
Initialization function.
uart_parity_t parity_bit
Definition: enocean4.h:273
uart_stop_bits_t stop_bit
Definition: enocean4.h:274
int32_t enocean4_generic_read(enocean4_t *ctx, char *data_buf, uint16_t max_len)
Generic read function.
void enocean4_set_rst_pin(enocean4_t *ctx, uint8_t state)
Set RST ( reset ) pin state.
void enocean4_generic_write(enocean4_t *ctx, char *data_buf, uint16_t len)
Generic write function.
uint8_t enocean4_send_packet(enocean4_t *ctx, enocean4_packet_t *packet)
Packet Send function.
#define DRV_TX_BUFFER_SIZE
Definition: enocean4.h:89
uint16_t data_length
Definition: enocean4.h:224
uint8_t response_ready
Definition: enocean4.h:249
void enocean4_response_handler_set(enocean4_t *ctx, void(*handler)(enocean4_packet_t *, uint8_t *))
Handler Set function.
#define ENOCEAN4_RETVAL
Definition: enocean4.h:78
void enocean4_reset(enocean4_t *ctx)
Reset function.
uart_data_bits_t data_bit
Definition: enocean4.h:272
Click ctx object definition.
Definition: enocean4.h:236
uint32_t baud_rate
Definition: enocean4.h:270