38#include "drv_digital_out.h"
39#include "drv_digital_in.h"
40#include "drv_i2c_master.h"
52#define CLOCKGEN_MAP_MIKROBUS( cfg, mikrobus ) \
53 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
54 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA )
61#define CLOCKGEN_RETVAL uint8_t
63#define CLOCKGEN_OK 0x00
64#define CLOCKGEN_INIT_ERROR 0xFF
71#define CLOCKGEN_SLAVE_ADDRESS 0x60
78#define CLOCKGEN_REG_DEV_STATUS 0
79#define CLOCKGEN_REG_INT_STATUS_STICKY 1
80#define CLOCKGEN_REG_INT_STATUS_MASK 2
81#define CLOCKGEN_REG_OUTPUT_ENABLE_CTRL 3
82#define CLOCKGEN_REG_OEB_EN_CTRL_MASK 9
83#define CLOCKGEN_REG_PLL_IN_SRC 15
84#define CLOCKGEN_REG_CLK0_CTRL 16
85#define CLOCKGEN_REG_CLK1_CTRL 17
86#define CLOCKGEN_REG_CLK2_CTRL 18
87#define CLOCKGEN_REG_CLK3_CTRL 19
88#define CLOCKGEN_REG_CLK4_CTRL 20
89#define CLOCKGEN_REG_CLK5_CTRL 21
90#define CLOCKGEN_REG_CLK6_CTRL 22
91#define CLOCKGEN_REG_CLK7_CTRL 23
92#define CLOCKGEN_REG_CLK3_0_DIS_STATE 24
93#define CLOCKGEN_REG_CLK7_4_DIS_STATE 25
100#define CLOCKGEN_REG_MULTI_NA_PARAM3_B15_8 26
101#define CLOCKGEN_REG_MULTI_NA_PARAM3_B7_0 27
102#define CLOCKGEN_REG_MULTI_NA_PARAM1_B17_16 28
103#define CLOCKGEN_REG_MULTI_NA_PARAM1_B15_8 29
104#define CLOCKGEN_REG_MULTI_NA_PARAM1_B7_0 30
105#define CLOCKGEN_REG_MULTI_NA_PARAM3_2_B19_16 31
106#define CLOCKGEN_REG_MULTI_NA_PARAM2_B15_8 32
107#define CLOCKGEN_REG_MULTI_NA_PARAM2_B7_0 33
114#define CLOCKGEN_REG_MULTI_NB_PARAM3_B15_8 34
115#define CLOCKGEN_REG_MULTI_NB_PARAM3_B7_0 35
116#define CLOCKGEN_REG_MULTI_NB_PARAM1_B17_16 36
117#define CLOCKGEN_REG_MULTI_NB_PARAM1_B15_8 37
118#define CLOCKGEN_REG_MULTI_NB_PARAM1_B7_0 38
119#define CLOCKGEN_REG_MULTI_NB_PARAM3_2_B19_16 39
120#define CLOCKGEN_REG_MULTI_NB_PARAM2_B15_8 40
121#define CLOCKGEN_REG_MULTI_NB_PARAM2_B7_0 41
128#define CLOCKGEN_REG_MULTI_0_PARAM3_B15_8 42
129#define CLOCKGEN_REG_MULTI_0_PARAM3_B7_0 43
130#define CLOCKGEN_REG_MULTI_0_PARAM1_B17_16_DIVS 44
131#define CLOCKGEN_REG_MULTI_0_PARAM1_B15_8 45
132#define CLOCKGEN_REG_MULTI_0_PARAM1_B7_0 46
133#define CLOCKGEN_REG_MULTI_0_PARAM3_2_B19_16 47
134#define CLOCKGEN_REG_MULTI_0_PARAM2_B15_8 48
135#define CLOCKGEN_REG_MULTI_0_PARAM2_B7_0 49
142#define CLOCKGEN_REG_MULTI_1_PARAM3_B15_8 50
143#define CLOCKGEN_REG_MULTI_1_PARAM3_B7_0 51
144#define CLOCKGEN_REG_MULTI_1_PARAM1_B17_16_DIVS 52
145#define CLOCKGEN_REG_MULTI_1_PARAM1_B15_8 53
146#define CLOCKGEN_REG_MULTI_1_PARAM1_B7_0 54
147#define CLOCKGEN_REG_MULTI_1_PARAM3_2_B19_16 55
148#define CLOCKGEN_REG_MULTI_1_PARAM2_B15_8 56
149#define CLOCKGEN_REG_MULTI_1_PARAM2_B7_0 57
156#define CLOCKGEN_REG_MULTI_2_PARAM3_B15_8 58
157#define CLOCKGEN_REG_MULTI_2_PARAM3_B7_0 59
158#define CLOCKGEN_REG_MULTI_2_PARAM1_B17_16_DIVS 60
159#define CLOCKGEN_REG_MULTI_2_PARAM1_B15_8 61
160#define CLOCKGEN_REG_MULTI_2_PARAM1_B7_0 62
161#define CLOCKGEN_REG_MULTI_2_PARAM3_2_B19_16 63
162#define CLOCKGEN_REG_MULTI_2_PARAM2_B15_8 64
163#define CLOCKGEN_REG_MULTI_2_PARAM2_B7_0 65
170#define CLOCKGEN_REG_MULTI_3_PARAM3_B15_8 66
171#define CLOCKGEN_REG_MULTI_3_PARAM3_B7_0 67
172#define CLOCKGEN_REG_MULTI_3_PARAM1_B17_16_DIVS 68
173#define CLOCKGEN_REG_MULTI_3_PARAM1_B15_8 69
174#define CLOCKGEN_REG_MULTI_3_PARAM1_B7_0 70
175#define CLOCKGEN_REG_MULTI_3_PARAM3_2_B19_16 71
176#define CLOCKGEN_REG_MULTI_3_PARAM2_B15_8 72
177#define CLOCKGEN_REG_MULTI_3_PARAM2_B7_0 73
184#define CLOCKGEN_REG_MULTI_4_PARAM3_B15_8 74
185#define CLOCKGEN_REG_MULTI_4_PARAM3_B7_0 75
186#define CLOCKGEN_REG_MULTI_4_PARAM1_B17_16_DIVS 76
187#define CLOCKGEN_REG_MULTI_4_PARAM1_B15_8 77
188#define CLOCKGEN_REG_MULTI_4_PARAM1_B7_0 78
189#define CLOCKGEN_REG_MULTI_4_PARAM3_2_B19_16 79
190#define CLOCKGEN_REG_MULTI_4_PARAM2_B15_8 80
191#define CLOCKGEN_REG_MULTI_4_PARAM2_B7_0 81
198#define CLOCKGEN_REG_MULTI_5_PARAM3_B15_8 82
199#define CLOCKGEN_REG_MULTI_5_PARAM3_B7_0 83
200#define CLOCKGEN_REG_MULTI_5_PARAM1_B17_16_DIVS 84
201#define CLOCKGEN_REG_MULTI_5_PARAM1_B15_8 85
202#define CLOCKGEN_REG_MULTI_5_PARAM1_B7_0 86
203#define CLOCKGEN_REG_MULTI_5_PARAM3_2_B19_16 87
204#define CLOCKGEN_REG_MULTI_5_PARAM2_B15_8 88
205#define CLOCKGEN_REG_MULTI_5_PARAM2_B7_0 89
212#define CLOCKGEN_REG_MULTI_6_PARAM3_B15_8 90
213#define CLOCKGEN_REG_MULTI_6_PARAM3_B7_0 91
214#define CLOCKGEN_REG_MULTI_6_PARAM1_B17_16_DIVS 92
215#define CLOCKGEN_REG_MULTI_6_PARAM1_B15_8 93
216#define CLOCKGEN_REG_MULTI_6_PARAM1_B7_0 94
217#define CLOCKGEN_REG_MULTI_6_PARAM3_2_B19_16 95
218#define CLOCKGEN_REG_MULTI_6_PARAM2_B15_8 96
219#define CLOCKGEN_REG_MULTI_6_PARAM2_B7_0 97
226#define CLOCKGEN_REG_MULTI_7_PARAM3_B15_8 98
227#define CLOCKGEN_REG_MULTI_7_PARAM3_B7_0 99
228#define CLOCKGEN_REG_MULTI_7_PARAM1_B17_16_DIVS 100
229#define CLOCKGEN_REG_MULTI_7_PARAM1_B15_8 101
230#define CLOCKGEN_REG_MULTI_7_PARAM1_B7_0 102
231#define CLOCKGEN_REG_MULTI_7_PARAM3_2_B19_16 103
232#define CLOCKGEN_REG_MULTI_7_PARAM2_B15_8 104
233#define CLOCKGEN_REG_MULTI_7_PARAM2_B7_0 105
240#define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM2_EN_B14_8 149
241#define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM2_B7_0 150
242#define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_MODE_B14_8 151
243#define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_B7_0 152
244#define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM1_B7_0 153
245#define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_B11_8_UP_DWN 154
246#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_DOWN_PLL_A 155
247#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM2_B14_8 156
248#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM2_B7_0 157
249#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM3_B14_8 158
250#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM3_B7_0 159
251#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM1_B7_0 160
252#define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM1_B11_8 161
259#define CLOCKGEN_REG_VCXO_PARAM_B7_0 162
260#define CLOCKGEN_REG_VCXO_PARAM_B15_8 163
261#define CLOCKGEN_REG_VCXO_PARAM_B21_16 164
268#define CLOCKGEN_REG_CLK0_INIT_OFFSET 165
269#define CLOCKGEN_REG_CLK1_INIT_OFFSET 166
270#define CLOCKGEN_REG_CLK2_INIT_OFFSET 167
277#define CLOCKGEN_REG_PLL_RST 177
278#define CLOCKGEN_REG_CRYSTAL_INTERNAL_CL 183
279#define CLOCKGEN_REG_FANOUT_EN 187
286#define CLOCKGEN_CLOCK_0 0
287#define CLOCKGEN_CLOCK_1 1
288#define CLOCKGEN_CLOCK_2 2
289#define CLOCKGEN_CLOCK_3 3
290#define CLOCKGEN_CLOCK_4 4
291#define CLOCKGEN_CLOCK_5 5
292#define CLOCKGEN_CLOCK_6 6
293#define CLOCKGEN_CLOCK_7 7
294#define CLOCKGEN_DISABLE_ALL_CLK 8
301#define CLOCKGEN_CLK_CTRL 16
303#define CLOCKGEN_PLLA 0xFF
304#define CLOCKGEN_PLLB 0xDF
306#define CLOCKGEN_RESET_PLLA 0x20
307#define CLOCKGEN_RESET_PLLB 0x80
309#define CLOCKGEN_PLL_PARAMS 0xFA
310#define CLOCKGEN_CLK_PARAMS 0xFB
312#define CLOCKGEN_PARAM_DIV_4_EN 0x3
313#define CLOCKGEN_PARAM_DIV_OTHER 0x0
320#define CLOCKGEN_PARAM_DIV_1 0x0
321#define CLOCKGEN_PARAM_DIV_2 0x1
322#define CLOCKGEN_PARAM_DIV_4 0x2
323#define CLOCKGEN_PARAM_DIV_8 0x3
324#define CLOCKGEN_PARAM_DIV_16 0x4
325#define CLOCKGEN_PARAM_DIV_32 0x5
326#define CLOCKGEN_PARAM_DIV_64 0x6
327#define CLOCKGEN_PARAM_DIV_128 0x7
334#define CLOCKGEN_PLL_INPUT_XO 0
335#define CLOCKGEN_PLL_INPUT_CLKIN 1
337#define CLOCKGEN_FREQ_MULTY 100
344#define CLOCKGEN_DIS_STATE_LOW 0
345#define CLOCKGEN_DIS_STATE_HIGH 1
346#define CLOCKGEN_DIS_STATE_HIGH_IMP 2
347#define CLOCKGEN_DIS_STATE_NEVER_DIS 3
354#define CLOCKGEN_PARAMS_MACRO 8
356#define CLOCKGEN_DISIABLE_STATE_SHIFT 2
358#define CLOCKGEN_XTAL 25000000
359#define CLOCKGEN_MAX_FREQ CLOCKGEN_XTAL * 32
#define CLOCKGEN_RETVAL
Definition: clockgen.h:61
void clockgen_setup_pll(clockgen_t *ctx, uint8_t pll, uint8_t mult, uint32_t num)
Function for setting pll.
void clockgen_get_params(clockgen_t *ctx, uint8_t clk_pll_num, clockgen_params_t *param_group)
Function for getting clock pll-s.
void clockgen_default_cfg(clockgen_t *ctx)
Click Default Configuration function.
CLOCKGEN_RETVAL clockgen_init(clockgen_t *ctx, clockgen_cfg_t *cfg)
Initialization function.
void clockgen_generic_read(clockgen_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
void clockgen_ctrl_clk(clockgen_t *ctx, uint8_t clk_num, uint8_t ctrl_data)
Function enabling specific clock.
void clockgen_set_disable_state(clockgen_t *ctx, uint8_t clk_num, uint8_t disable_state)
Function for setting clock disabling state.
void clockgen_set_frequency(clockgen_t *ctx, uint8_t clk_num, uint8_t pll_num, uint32_t freq)
Function for setting clock frequency on specific clock.
void clockgen_cfg_setup(clockgen_cfg_t *cfg)
Config Object Initialization function.
void clockgen_set_params(clockgen_t *ctx, uint8_t clk_pll_num, clockgen_params_t *param_group)
Function for setting clock pll-s.
void clockgen_generic_write(clockgen_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
void clockgen_enable_clk(clockgen_t *ctx, uint8_t clk_num)
Function enabling specific clock.
void clockgen_set_clk_pll(clockgen_t *ctx, uint8_t clk_num, uint8_t pll_sel)
Function for setting clock pll-s.
void clockgen_setup_multisyinth(clockgen_t *ctx, uint8_t clk_num, uint32_t divider, uint32_t num)
Function for setting clock divider.
Click configuration structure definition.
Definition: clockgen.h:392
uint32_t i2c_speed
Definition: clockgen.h:400
pin_name_t scl
Definition: clockgen.h:395
pin_name_t sda
Definition: clockgen.h:396
uint8_t i2c_address
Definition: clockgen.h:401
Structure for setting clock parameters.
Definition: clockgen.h:409
uint8_t div4
Definition: clockgen.h:413
uint32_t p2
Definition: clockgen.h:411
uint8_t div_val
Definition: clockgen.h:414
uint32_t p3
Definition: clockgen.h:412
uint32_t p1
Definition: clockgen.h:410
Click ctx object definition.
Definition: clockgen.h:372
uint32_t denom
Definition: clockgen.h:383
uint8_t factor
Definition: clockgen.h:384
i2c_master_t i2c
Definition: clockgen.h:375
uint8_t slave_address
Definition: clockgen.h:379