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38 #include "mikrosdk_version.h"
41 #if mikroSDK_GET_VERSION < 20800ul
42 #include "rcu_delays.h"
48 #include "drv_digital_out.h"
49 #include "drv_digital_in.h"
50 #include "drv_i2c_master.h"
62 #define CLOCKGEN_MAP_MIKROBUS( cfg, mikrobus ) \
63 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
64 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA )
71 #define CLOCKGEN_RETVAL uint8_t
73 #define CLOCKGEN_OK 0x00
74 #define CLOCKGEN_INIT_ERROR 0xFF
81 #define CLOCKGEN_SLAVE_ADDRESS 0x60
88 #define CLOCKGEN_REG_DEV_STATUS 0
89 #define CLOCKGEN_REG_INT_STATUS_STICKY 1
90 #define CLOCKGEN_REG_INT_STATUS_MASK 2
91 #define CLOCKGEN_REG_OUTPUT_ENABLE_CTRL 3
92 #define CLOCKGEN_REG_OEB_EN_CTRL_MASK 9
93 #define CLOCKGEN_REG_PLL_IN_SRC 15
94 #define CLOCKGEN_REG_CLK0_CTRL 16
95 #define CLOCKGEN_REG_CLK1_CTRL 17
96 #define CLOCKGEN_REG_CLK2_CTRL 18
97 #define CLOCKGEN_REG_CLK3_CTRL 19
98 #define CLOCKGEN_REG_CLK4_CTRL 20
99 #define CLOCKGEN_REG_CLK5_CTRL 21
100 #define CLOCKGEN_REG_CLK6_CTRL 22
101 #define CLOCKGEN_REG_CLK7_CTRL 23
102 #define CLOCKGEN_REG_CLK3_0_DIS_STATE 24
103 #define CLOCKGEN_REG_CLK7_4_DIS_STATE 25
110 #define CLOCKGEN_REG_MULTI_NA_PARAM3_B15_8 26
111 #define CLOCKGEN_REG_MULTI_NA_PARAM3_B7_0 27
112 #define CLOCKGEN_REG_MULTI_NA_PARAM1_B17_16 28
113 #define CLOCKGEN_REG_MULTI_NA_PARAM1_B15_8 29
114 #define CLOCKGEN_REG_MULTI_NA_PARAM1_B7_0 30
115 #define CLOCKGEN_REG_MULTI_NA_PARAM3_2_B19_16 31
116 #define CLOCKGEN_REG_MULTI_NA_PARAM2_B15_8 32
117 #define CLOCKGEN_REG_MULTI_NA_PARAM2_B7_0 33
124 #define CLOCKGEN_REG_MULTI_NB_PARAM3_B15_8 34
125 #define CLOCKGEN_REG_MULTI_NB_PARAM3_B7_0 35
126 #define CLOCKGEN_REG_MULTI_NB_PARAM1_B17_16 36
127 #define CLOCKGEN_REG_MULTI_NB_PARAM1_B15_8 37
128 #define CLOCKGEN_REG_MULTI_NB_PARAM1_B7_0 38
129 #define CLOCKGEN_REG_MULTI_NB_PARAM3_2_B19_16 39
130 #define CLOCKGEN_REG_MULTI_NB_PARAM2_B15_8 40
131 #define CLOCKGEN_REG_MULTI_NB_PARAM2_B7_0 41
138 #define CLOCKGEN_REG_MULTI_0_PARAM3_B15_8 42
139 #define CLOCKGEN_REG_MULTI_0_PARAM3_B7_0 43
140 #define CLOCKGEN_REG_MULTI_0_PARAM1_B17_16_DIVS 44
141 #define CLOCKGEN_REG_MULTI_0_PARAM1_B15_8 45
142 #define CLOCKGEN_REG_MULTI_0_PARAM1_B7_0 46
143 #define CLOCKGEN_REG_MULTI_0_PARAM3_2_B19_16 47
144 #define CLOCKGEN_REG_MULTI_0_PARAM2_B15_8 48
145 #define CLOCKGEN_REG_MULTI_0_PARAM2_B7_0 49
152 #define CLOCKGEN_REG_MULTI_1_PARAM3_B15_8 50
153 #define CLOCKGEN_REG_MULTI_1_PARAM3_B7_0 51
154 #define CLOCKGEN_REG_MULTI_1_PARAM1_B17_16_DIVS 52
155 #define CLOCKGEN_REG_MULTI_1_PARAM1_B15_8 53
156 #define CLOCKGEN_REG_MULTI_1_PARAM1_B7_0 54
157 #define CLOCKGEN_REG_MULTI_1_PARAM3_2_B19_16 55
158 #define CLOCKGEN_REG_MULTI_1_PARAM2_B15_8 56
159 #define CLOCKGEN_REG_MULTI_1_PARAM2_B7_0 57
166 #define CLOCKGEN_REG_MULTI_2_PARAM3_B15_8 58
167 #define CLOCKGEN_REG_MULTI_2_PARAM3_B7_0 59
168 #define CLOCKGEN_REG_MULTI_2_PARAM1_B17_16_DIVS 60
169 #define CLOCKGEN_REG_MULTI_2_PARAM1_B15_8 61
170 #define CLOCKGEN_REG_MULTI_2_PARAM1_B7_0 62
171 #define CLOCKGEN_REG_MULTI_2_PARAM3_2_B19_16 63
172 #define CLOCKGEN_REG_MULTI_2_PARAM2_B15_8 64
173 #define CLOCKGEN_REG_MULTI_2_PARAM2_B7_0 65
180 #define CLOCKGEN_REG_MULTI_3_PARAM3_B15_8 66
181 #define CLOCKGEN_REG_MULTI_3_PARAM3_B7_0 67
182 #define CLOCKGEN_REG_MULTI_3_PARAM1_B17_16_DIVS 68
183 #define CLOCKGEN_REG_MULTI_3_PARAM1_B15_8 69
184 #define CLOCKGEN_REG_MULTI_3_PARAM1_B7_0 70
185 #define CLOCKGEN_REG_MULTI_3_PARAM3_2_B19_16 71
186 #define CLOCKGEN_REG_MULTI_3_PARAM2_B15_8 72
187 #define CLOCKGEN_REG_MULTI_3_PARAM2_B7_0 73
194 #define CLOCKGEN_REG_MULTI_4_PARAM3_B15_8 74
195 #define CLOCKGEN_REG_MULTI_4_PARAM3_B7_0 75
196 #define CLOCKGEN_REG_MULTI_4_PARAM1_B17_16_DIVS 76
197 #define CLOCKGEN_REG_MULTI_4_PARAM1_B15_8 77
198 #define CLOCKGEN_REG_MULTI_4_PARAM1_B7_0 78
199 #define CLOCKGEN_REG_MULTI_4_PARAM3_2_B19_16 79
200 #define CLOCKGEN_REG_MULTI_4_PARAM2_B15_8 80
201 #define CLOCKGEN_REG_MULTI_4_PARAM2_B7_0 81
208 #define CLOCKGEN_REG_MULTI_5_PARAM3_B15_8 82
209 #define CLOCKGEN_REG_MULTI_5_PARAM3_B7_0 83
210 #define CLOCKGEN_REG_MULTI_5_PARAM1_B17_16_DIVS 84
211 #define CLOCKGEN_REG_MULTI_5_PARAM1_B15_8 85
212 #define CLOCKGEN_REG_MULTI_5_PARAM1_B7_0 86
213 #define CLOCKGEN_REG_MULTI_5_PARAM3_2_B19_16 87
214 #define CLOCKGEN_REG_MULTI_5_PARAM2_B15_8 88
215 #define CLOCKGEN_REG_MULTI_5_PARAM2_B7_0 89
222 #define CLOCKGEN_REG_MULTI_6_PARAM3_B15_8 90
223 #define CLOCKGEN_REG_MULTI_6_PARAM3_B7_0 91
224 #define CLOCKGEN_REG_MULTI_6_PARAM1_B17_16_DIVS 92
225 #define CLOCKGEN_REG_MULTI_6_PARAM1_B15_8 93
226 #define CLOCKGEN_REG_MULTI_6_PARAM1_B7_0 94
227 #define CLOCKGEN_REG_MULTI_6_PARAM3_2_B19_16 95
228 #define CLOCKGEN_REG_MULTI_6_PARAM2_B15_8 96
229 #define CLOCKGEN_REG_MULTI_6_PARAM2_B7_0 97
236 #define CLOCKGEN_REG_MULTI_7_PARAM3_B15_8 98
237 #define CLOCKGEN_REG_MULTI_7_PARAM3_B7_0 99
238 #define CLOCKGEN_REG_MULTI_7_PARAM1_B17_16_DIVS 100
239 #define CLOCKGEN_REG_MULTI_7_PARAM1_B15_8 101
240 #define CLOCKGEN_REG_MULTI_7_PARAM1_B7_0 102
241 #define CLOCKGEN_REG_MULTI_7_PARAM3_2_B19_16 103
242 #define CLOCKGEN_REG_MULTI_7_PARAM2_B15_8 104
243 #define CLOCKGEN_REG_MULTI_7_PARAM2_B7_0 105
250 #define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM2_EN_B14_8 149
251 #define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM2_B7_0 150
252 #define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_MODE_B14_8 151
253 #define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_B7_0 152
254 #define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM1_B7_0 153
255 #define CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_B11_8_UP_DWN 154
256 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_DOWN_PLL_A 155
257 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM2_B14_8 156
258 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM2_B7_0 157
259 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM3_B14_8 158
260 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM3_B7_0 159
261 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM1_B7_0 160
262 #define CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM1_B11_8 161
269 #define CLOCKGEN_REG_VCXO_PARAM_B7_0 162
270 #define CLOCKGEN_REG_VCXO_PARAM_B15_8 163
271 #define CLOCKGEN_REG_VCXO_PARAM_B21_16 164
278 #define CLOCKGEN_REG_CLK0_INIT_OFFSET 165
279 #define CLOCKGEN_REG_CLK1_INIT_OFFSET 166
280 #define CLOCKGEN_REG_CLK2_INIT_OFFSET 167
287 #define CLOCKGEN_REG_PLL_RST 177
288 #define CLOCKGEN_REG_CRYSTAL_INTERNAL_CL 183
289 #define CLOCKGEN_REG_FANOUT_EN 187
296 #define CLOCKGEN_CLOCK_0 0
297 #define CLOCKGEN_CLOCK_1 1
298 #define CLOCKGEN_CLOCK_2 2
299 #define CLOCKGEN_CLOCK_3 3
300 #define CLOCKGEN_CLOCK_4 4
301 #define CLOCKGEN_CLOCK_5 5
302 #define CLOCKGEN_CLOCK_6 6
303 #define CLOCKGEN_CLOCK_7 7
304 #define CLOCKGEN_DISABLE_ALL_CLK 8
311 #define CLOCKGEN_CLK_CTRL 16
313 #define CLOCKGEN_PLLA 0xFF
314 #define CLOCKGEN_PLLB 0xDF
316 #define CLOCKGEN_RESET_PLLA 0x20
317 #define CLOCKGEN_RESET_PLLB 0x80
319 #define CLOCKGEN_PLL_PARAMS 0xFA
320 #define CLOCKGEN_CLK_PARAMS 0xFB
322 #define CLOCKGEN_PARAM_DIV_4_EN 0x3
323 #define CLOCKGEN_PARAM_DIV_OTHER 0x0
330 #define CLOCKGEN_PARAM_DIV_1 0x0
331 #define CLOCKGEN_PARAM_DIV_2 0x1
332 #define CLOCKGEN_PARAM_DIV_4 0x2
333 #define CLOCKGEN_PARAM_DIV_8 0x3
334 #define CLOCKGEN_PARAM_DIV_16 0x4
335 #define CLOCKGEN_PARAM_DIV_32 0x5
336 #define CLOCKGEN_PARAM_DIV_64 0x6
337 #define CLOCKGEN_PARAM_DIV_128 0x7
344 #define CLOCKGEN_PLL_INPUT_XO 0
345 #define CLOCKGEN_PLL_INPUT_CLKIN 1
347 #define CLOCKGEN_FREQ_MULTY 100
354 #define CLOCKGEN_DIS_STATE_LOW 0
355 #define CLOCKGEN_DIS_STATE_HIGH 1
356 #define CLOCKGEN_DIS_STATE_HIGH_IMP 2
357 #define CLOCKGEN_DIS_STATE_NEVER_DIS 3
364 #define CLOCKGEN_PARAMS_MACRO 8
366 #define CLOCKGEN_DISIABLE_STATE_SHIFT 2
368 #define CLOCKGEN_XTAL 25000000
369 #define CLOCKGEN_MAX_FREQ CLOCKGEN_XTAL * 32
601 #endif // _CLOCKGEN_H_
pin_name_t scl
Definition: clockgen.h:405
uint32_t p1
Definition: clockgen.h:420
void clockgen_set_frequency(clockgen_t *ctx, uint8_t clk_num, uint8_t pll_num, uint32_t freq)
Function for setting clock frequency on specific clock.
void clockgen_ctrl_clk(clockgen_t *ctx, uint8_t clk_num, uint8_t ctrl_data)
Function enabling specific clock.
uint8_t slave_address
Definition: clockgen.h:389
void clockgen_setup_pll(clockgen_t *ctx, uint8_t pll, uint8_t mult, uint32_t num)
Function for setting pll.
void clockgen_setup_multisyinth(clockgen_t *ctx, uint8_t clk_num, uint32_t divider, uint32_t num)
Function for setting clock divider.
uint32_t p3
Definition: clockgen.h:422
uint32_t denom
Definition: clockgen.h:393
Structure for setting clock parameters.
Definition: clockgen.h:419
i2c_master_t i2c
Definition: clockgen.h:385
void clockgen_default_cfg(clockgen_t *ctx)
Click Default Configuration function.
pin_name_t sda
Definition: clockgen.h:406
uint8_t i2c_address
Definition: clockgen.h:411
Click configuration structure definition.
Definition: clockgen.h:402
CLOCKGEN_RETVAL clockgen_init(clockgen_t *ctx, clockgen_cfg_t *cfg)
Initialization function.
uint8_t factor
Definition: clockgen.h:394
void clockgen_generic_write(clockgen_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.
void clockgen_set_disable_state(clockgen_t *ctx, uint8_t clk_num, uint8_t disable_state)
Function for setting clock disabling state.
uint8_t div_val
Definition: clockgen.h:424
#define CLOCKGEN_RETVAL
Definition: clockgen.h:71
void clockgen_get_params(clockgen_t *ctx, uint8_t clk_pll_num, clockgen_params_t *param_group)
Function for getting clock pll-s.
void clockgen_cfg_setup(clockgen_cfg_t *cfg)
Config Object Initialization function.
uint32_t p2
Definition: clockgen.h:421
uint32_t i2c_speed
Definition: clockgen.h:410
void clockgen_generic_read(clockgen_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.
void clockgen_enable_clk(clockgen_t *ctx, uint8_t clk_num)
Function enabling specific clock.
Click ctx object definition.
Definition: clockgen.h:382
uint8_t div4
Definition: clockgen.h:423
void clockgen_set_params(clockgen_t *ctx, uint8_t clk_pll_num, clockgen_params_t *param_group)
Function for setting clock pll-s.
void clockgen_set_clk_pll(clockgen_t *ctx, uint8_t clk_num, uint8_t pll_sel)
Function for setting clock pll-s.