tdc  2.0.0.0
tdc.h
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22 
28 #ifndef TDC_H
29 #define TDC_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_spi_master.h"
38 
59 #define TDC_REG_ADR_CONFIG1 0x00
60 #define TDC_REG_ADR_CONFIG2 0x01
61 #define TDC_REG_ADR_INT_STATUS 0x02
62 #define TDC_REG_ADR_INT_MASK 0x03
63 #define TDC_REG_ADR_COARSE_CNTR_OVF_H 0x04
64 #define TDC_REG_ADR_COARSE_CNTR_OVF_L 0x05
65 #define TDC_REG_ADR_CLOCK_CNTR_OVF_H 0x06
66 #define TDC_REG_ADR_CLOCK_CNTR_OVF_L 0x07
67 #define TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_H 0x08
68 #define TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_L 0x09
69 #define TDC_REG_ADR_TIME1 0x10
70 #define TDC_REG_ADR_CLOCK_COUNT1 0x11
71 #define TDC_REG_ADR_TIME2 0x12
72 #define TDC_REG_ADR_CLOCK_COUNT2 0x13
73 #define TDC_REG_ADR_TIME3 0x14
74 #define TDC_REG_ADR_CLOCK_COUNT3 0x15
75 #define TDC_REG_ADR_TIME4 0x16
76 #define TDC_REG_ADR_CLOCK_COUNT4 0x17
77 #define TDC_REG_ADR_TIME5 0x18
78 #define TDC_REG_ADR_CLOCK_COUNT5 0x19
79 #define TDC_REG_ADR_CLOCK_COUNTX(num) (TDC_REG_ADR_CLOCK_COUNT1+2*((num)-1))
80 #define TDC_REG_ADR_TIME6 0x1A
81 #define TDC_REG_ADR_TIMEX(num) (TDC_REG_ADR_TIME1+2*((num)-1))
82 #define TDC_REG_ADR_CALIBRATION1 0x1B
83 #define TDC_REG_ADR_CALIBRATION2 0x1C
84 #define TDC_REG_DEFAULTS_CONFIG2 0x40
85 #define TDC_REG_DEFAULTS_INT_MASK 0x07
86 
87 #define TDC_REG_SHIFT_CONFIG1_FORCE_CAL 7
88 #define TDC_REG_SHIFT_CONFIG1_PARITY_EN 6
89 #define TDC_REG_SHIFT_CONFIG1_TRIGG_EDGE 5
90 #define TDC_REG_SHIFT_CONFIG1_STOP_EDGE 4
91 #define TDC_REG_SHIFT_CONFIG1_START_EDGE 3
92 #define TDC_REG_SHIFT_CONFIG1_MEAS_MODE 1
93 #define TDC_REG_SHIFT_CONFIG1_START_MEAS 0
94 
95 #define TDC_REG_VAL_CONFIG1_MEAS_MODE_MIN 1
96 #define TDC_REG_VAL_CONFIG1_MEAS_MODE_MAX 2
97 #define TDC_REG_VAL_CONFIG1_MEAS_MODE(num) ((num)-1)
98 
99 
100 #define TDC_REG_SHIFT_CONFIG2_CALIBRATION2_PERIODS 6
101 #define TDC_REG_SHIFT_CONFIG2_AVG_CYCLES 3
102 #define TDC_REG_SHIFT_CONFIG2_NUM_STOP 0
103 
104 #define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_2 0
105 #define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_10 1
106 #define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_20 2
107 #define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_40 3
108 
109 #define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL 0
110 #define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN 1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL
111 #define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL 7
112 #define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX 1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL
113 
114 #define TDC_REG_VAL_CONFIG2_NUM_STOP(num) ((num)-1)
115 #define TDC_REG_VAL_CONFIG2_NUM_STOP_MAX 5
116 
117 #define TDC_REG_SHIFT_INT_STATUS_MEAS_COMPLETE_FLAG 4
118 #define TDC_REG_SHIFT_INT_STATUS_MEAS_STARTED_FLAG 3
119 #define TDC_REG_SHIFT_INT_STATUS_CLOCK_CNTR_OVF_INT 2
120 #define TDC_REG_SHIFT_INT_STATUS_COARSE_CNTR_OVF_INT 1
121 #define TDC_REG_SHIFT_INT_STATUS_NEW_MEAS_INT 0
122 
123 #define TDC_REG_SHIFT_INT_MASK_CLOCK_CNTR_OVF_MASK 2
124 #define TDC_REG_SHIFT_INT_MASK_COARSE_CNTR_OVF_MASK 1
125 #define TDC_REG_SHIFT_INT_MASK_NEW_MEAS_MASK 0
126  // tdc_reg
128 
143 #define TDC_CLOCK_FREQ_HZ 8000000
144 #define TDC_RING_OSC_FREQ_KHZ 8000
145 #define TDC_RING_OSC_FREQ_MHZ TDC_RING_OSC_FREQ_KHZ/1000
146 #define PS_PER_K_SEC 1000000000
147 #define US_PER_K_SEC 1000000
148 #define PS_PER_PIC32_SEC 878000
149 #define PS_PER_PIC_SEC 160000
150 #define TDC_CLOCK_FREQ_HZ_PS_PER_PIC_SEC 0.05
151 #define TDC_CLOCK_FREQ_HZ_PS_PER_ARM_SEC 14.745
152 
153 #define TDC_MCU_CLOCK_MODE_168_MHZ 0
154 #define TDC_MCU_CLOCK_MODE_80_MHZ 1
155 #define TDC_MCU_CLOCK_MODE_64_MHZ 2
156  // tdc_set
158 
173 #define TDC_MAP_MIKROBUS( cfg, mikrobus ) \
174  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
175  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
176  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
177  cfg.oen = MIKROBUS( mikrobus, MIKROBUS_AN ); \
178  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
179  cfg.en = MIKROBUS( mikrobus, MIKROBUS_RST ); \
180  cfg.trg = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
181  cfg.stop = MIKROBUS( mikrobus, MIKROBUS_CS ); \
182  cfg.start = MIKROBUS( mikrobus, MIKROBUS_RST ); \
183  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
184  // tdc_map // tdc
187 
192 typedef struct
193 {
194  // Output pins
195  digital_out_t oen;
196  digital_out_t en;
197  digital_out_t stop;
198  digital_out_t start;
200  // Input pins
201  digital_in_t trg;
202  digital_in_t int_pin;
204  // Modules
205  spi_master_t spi;
207  pin_name_t chip_select;
209 } tdc_t;
210 
215 typedef struct
216 {
217  // Communication gpio pins
218  pin_name_t miso;
219  pin_name_t mosi;
220  pin_name_t sck;
221  pin_name_t cs;
223  // Additional gpio pins
224  pin_name_t oen;
225  pin_name_t en;
226  pin_name_t trg;
227  pin_name_t stop;
228  pin_name_t start;
229  pin_name_t int_pin;
231  // static variable
232  uint32_t spi_speed;
233  spi_master_mode_t spi_mode;
234  spi_master_chip_select_polarity_t cs_polarity;
236 } tdc_cfg_t;
237 
242 typedef enum
243 {
244  TDC_OK = 0,
245  TDC_ERROR = -1
246 
248 
264 void tdc_cfg_setup ( tdc_cfg_t *cfg );
265 
280 err_t tdc_init ( tdc_t *ctx, tdc_cfg_t *cfg );
281 
295 err_t tdc_default_cfg ( tdc_t *ctx );
296 
312 err_t tdc_generic_write ( tdc_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
313 
329 err_t tdc_generic_read ( tdc_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
330 
345 err_t tdc_generic_write_byte ( tdc_t *ctx, uint8_t reg, uint8_t data_in );
346 
361 err_t tdc_generic_read_byte ( tdc_t *ctx, uint8_t reg, uint8_t *data_out );
362 
374 void tdc_gen_pulse ( tdc_t *ctx, uint32_t u_sec, uint8_t n_stops );
375 
387 void tdc_start_measurement ( tdc_t *ctx );
388 
401 void tdc_setup_overflow ( tdc_t *ctx, uint32_t overflow_ps );
402 
420 err_t tdc_setup_measurement ( tdc_t *ctx, uint8_t cal_periods, uint8_t avg_cycles, uint8_t num_stops, uint8_t mode );
421 
440 err_t tdc_get_measurement ( tdc_t *ctx, uint8_t clock_mode, uint8_t measure_num_stop, uint32_t *time, uint32_t *clock_countn, uint32_t *tof );
441 
453 uint8_t tdc_get_interrupt ( tdc_t *ctx );
454 
466 uint8_t tdc_get_trg ( tdc_t *ctx );
467 
468 #ifdef __cplusplus
469 }
470 #endif
471 #endif // TDC_H
472  // tdc
474 
475 // ------------------------------------------------------------------------ END
tdc_get_interrupt
uint8_t tdc_get_interrupt(tdc_t *ctx)
TDC get interrupt function.
tdc_return_value_t
tdc_return_value_t
TDC Click return value data.
Definition: tdc.h:241
TDC_ERROR
Definition: tdc.h:244
tdc_generic_write_byte
err_t tdc_generic_write_byte(tdc_t *ctx, uint8_t reg, uint8_t data_in)
TDC data write byte function.
tdc_generic_write
err_t tdc_generic_write(tdc_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
TDC data writing function.
tdc_generic_read_byte
err_t tdc_generic_read_byte(tdc_t *ctx, uint8_t reg, uint8_t *data_out)
TDC data read function.
tdc_generic_read
err_t tdc_generic_read(tdc_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
TDC data reading function.
tdc_setup_measurement
err_t tdc_setup_measurement(tdc_t *ctx, uint8_t cal_periods, uint8_t avg_cycles, uint8_t num_stops, uint8_t mode)
TDC setup measurement function.
tdc_get_trg
uint8_t tdc_get_trg(tdc_t *ctx)
TDC get trigger signal function.
tdc_cfg_t
TDC Click configuration object.
Definition: tdc.h:214
tdc_cfg_setup
void tdc_cfg_setup(tdc_cfg_t *cfg)
TDC configuration object setup function.
tdc_t
TDC Click context object.
Definition: tdc.h:191
TDC_OK
Definition: tdc.h:243
tdc_init
err_t tdc_init(tdc_t *ctx, tdc_cfg_t *cfg)
TDC initialization function.
tdc_get_measurement
err_t tdc_get_measurement(tdc_t *ctx, uint8_t clock_mode, uint8_t measure_num_stop, uint32_t *time, uint32_t *clock_countn, uint32_t *tof)
TDC get measurement function.
tdc_default_cfg
err_t tdc_default_cfg(tdc_t *ctx)
TDC default configuration function.
tdc_setup_overflow
void tdc_setup_overflow(tdc_t *ctx, uint32_t overflow_ps)
TDC setup overflow function.
tdc_start_measurement
void tdc_start_measurement(tdc_t *ctx)
TDC start measurement function.
tdc_gen_pulse
void tdc_gen_pulse(tdc_t *ctx, uint32_t u_sec, uint8_t n_stops)
TDC pulse generation function.