nvsram  2.0.0.0
nvsram.h
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22 
28 #ifndef NVSRAM_H
29 #define NVSRAM_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "mikrosdk_version.h"
36 
37 #ifdef __GNUC__
38 #if mikroSDK_GET_VERSION < 20800ul
39 #include "rcu_delays.h"
40 #else
41 #include "delays.h"
42 #endif
43 #endif
44 
45 #include "drv_digital_out.h"
46 #include "drv_digital_in.h"
47 #include "drv_i2c_master.h"
48 
69 #define NVSRAM_MEM_CTL_REG 0x00
70 #define NVSRAM_SERIAL_NUM_REG_1 0x01
71 #define NVSRAM_SERIAL_NUM_REG_2 0x02
72 #define NVSRAM_SERIAL_NUM_REG_3 0x03
73 #define NVSRAM_SERIAL_NUM_REG_4 0x04
74 #define NVSRAM_SERIAL_NUM_REG_5 0x05
75 #define NVSRAM_SERIAL_NUM_REG_6 0x06
76 #define NVSRAM_SERIAL_NUM_REG_7 0x07
77 #define NVSRAM_SERIAL_NUM_REG_8 0x08
78 #define NVSRAM_DEV_ID_REG_1 0x09
79 #define NVSRAM_DEV_ID_REG_2 0x0A
80 #define NVSRAM_DEV_ID_REG_3 0x0B
81 #define NVSRAM_DEV_ID_REG_4 0x0C
82 #define NVSRAM_CMD_REG 0xAA
83  // nvsram_reg
85 
100 #define NVSRAM_I2C_MEM_SEL 0x50
101 
106 #define NVSRAM_CMD_STORE 0x3C
107 #define NVSRAM_CMD_RECALL 0x60
108 #define NVSRAM_CMD_ASENB 0x59
109 #define NVSRAM_CMD_ASDISB 0x19
110 #define NVSRAM_CMD_SLEEP 0xB9
111 
116 #define NVSRAM_BP_NONE 0x00
117 #define NVSRAM_BP_QUARTER 0x04
118 #define NVSRAM_BP_HALF 0x08
119 #define NVSRAM_BP_ALL 0x0C
120 #define NVSRAM_NO_SNL 0x00
121 #define NVSRAM_SNL 0x40
122 
127 #define NVSRAM_WRITE_MEMORY_DISABLE 0x00
128 #define NVSRAM_WRITE_MEMORY_ENABLE 0x01
129 
134 #define NVSRAM_I2C_SLAVE_ADDR_0 0x18
135 #define NVSRAM_I2C_SLAVE_ADDR_1 0x1A
136 #define NVSRAM_I2C_SLAVE_ADDR_2 0x1C
137 #define NVSRAM_I2C_SLAVE_ADDR_3 0x1E
138  // nvsram_set
140 
155 #define NVSRAM_MAP_MIKROBUS( cfg, mikrobus ) \
156  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
157  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
158  cfg.wp = MIKROBUS( mikrobus, MIKROBUS_PWM )
159  // nvsram_map // nvsram
162 
167 typedef struct
168 {
169  // Output pins
170  digital_out_t wp;
172  // Modules
173  i2c_master_t i2c;
175  // I2C slave address
176  uint8_t slave_address;
178 } nvsram_t;
179 
184 typedef struct
185 {
186  pin_name_t scl;
187  pin_name_t sda;
189  pin_name_t wp;
191  uint32_t i2c_speed;
192  uint8_t i2c_address;
194 } nvsram_cfg_t;
195 
200 typedef enum
201 {
203  NVSRAM_ERROR = -1
204 
206 
223 
238 err_t nvsram_init ( nvsram_t *ctx, nvsram_cfg_t *cfg );
239 
255 err_t nvsram_generic_write ( nvsram_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
256 
272 err_t nvsram_generic_read ( nvsram_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
273 
287 void nvsram_reg_write ( nvsram_t *ctx, uint8_t reg, uint8_t tx_data );
288 
301 uint8_t nvsram_reg_read ( nvsram_t *ctx, uint8_t reg );
302 
318 void nvsram_burst_reg_write ( nvsram_t *ctx, uint8_t reg, uint8_t *p_tx_data, uint8_t n_bytes );
319 
335 void nvsram_burst_reg_read ( nvsram_t *ctx, uint8_t reg, uint8_t *p_rx_data, uint8_t n_bytes );
336 
349 void nvsram_send_cmd ( nvsram_t *ctx, uint8_t cmd );
350 
362 uint32_t nvsram_read_dev_id ( nvsram_t *ctx );
363 
379 void nvsram_memory_write ( nvsram_t *ctx, uint32_t mem_adr, uint8_t *p_tx_data, uint16_t n_bytes );
380 
396 void nvsram_memory_read ( nvsram_t *ctx, uint32_t mem_adr, uint8_t *p_rx_data, uint16_t n_bytes );
397 
410 void nvsram_enable_memory_write ( nvsram_t *ctx, uint8_t en_wr_mem );
411 
412 #ifdef __cplusplus
413 }
414 #endif
415 #endif // NVSRAM_H
416  // nvsram
418 
419 // ------------------------------------------------------------------------ END
nvsram_generic_read
err_t nvsram_generic_read(nvsram_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len)
nvSRAM I2C reading function.
nvsram_cfg_t::i2c_address
uint8_t i2c_address
Definition: nvsram.h:192
nvsram_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: nvsram.h:191
nvsram_init
err_t nvsram_init(nvsram_t *ctx, nvsram_cfg_t *cfg)
nvSRAM initialization function.
nvsram_burst_reg_read
void nvsram_burst_reg_read(nvsram_t *ctx, uint8_t reg, uint8_t *p_rx_data, uint8_t n_bytes)
Burst register read function.
nvsram_enable_memory_write
void nvsram_enable_memory_write(nvsram_t *ctx, uint8_t en_wr_mem)
Enable memory write function.
nvsram_burst_reg_write
void nvsram_burst_reg_write(nvsram_t *ctx, uint8_t reg, uint8_t *p_tx_data, uint8_t n_bytes)
Burst register write function.
nvsram_t
nvSRAM Click context object.
Definition: nvsram.h:168
NVSRAM_OK
@ NVSRAM_OK
Definition: nvsram.h:202
nvsram_reg_read
uint8_t nvsram_reg_read(nvsram_t *ctx, uint8_t reg)
Generic read the byte of data function.
nvsram_generic_write
err_t nvsram_generic_write(nvsram_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len)
nvSRAM I2C writing function.
nvsram_memory_write
void nvsram_memory_write(nvsram_t *ctx, uint32_t mem_adr, uint8_t *p_tx_data, uint16_t n_bytes)
Write memory function.
NVSRAM_ERROR
@ NVSRAM_ERROR
Definition: nvsram.h:203
nvsram_memory_read
void nvsram_memory_read(nvsram_t *ctx, uint32_t mem_adr, uint8_t *p_rx_data, uint16_t n_bytes)
Read memory function.
nvsram_cfg_t
nvSRAM Click configuration object.
Definition: nvsram.h:185
nvsram_t::wp
digital_out_t wp
Definition: nvsram.h:170
nvsram_t::slave_address
uint8_t slave_address
Definition: nvsram.h:176
nvsram_cfg_t::scl
pin_name_t scl
Definition: nvsram.h:186
nvsram_return_value_t
nvsram_return_value_t
nvSRAM Click return value data.
Definition: nvsram.h:201
nvsram_reg_write
void nvsram_reg_write(nvsram_t *ctx, uint8_t reg, uint8_t tx_data)
Generic write the byte of data function.
nvsram_cfg_t::sda
pin_name_t sda
Definition: nvsram.h:187
nvsram_send_cmd
void nvsram_send_cmd(nvsram_t *ctx, uint8_t cmd)
Send command function.
nvsram_cfg_setup
void nvsram_cfg_setup(nvsram_cfg_t *cfg)
nvSRAM configuration object setup function.
nvsram_t::i2c
i2c_master_t i2c
Definition: nvsram.h:173
nvsram_read_dev_id
uint32_t nvsram_read_dev_id(nvsram_t *ctx)
Read device ID function.
nvsram_cfg_t::wp
pin_name_t wp
Definition: nvsram.h:189