nvsram2  2.0.0.0
nvsram2.h
Go to the documentation of this file.
1 /****************************************************************************
2 ** Copyright (C) 2020 MikroElektronika d.o.o.
3 ** Contact: https://www.mikroe.com/contact
4 **
5 ** Permission is hereby granted, free of charge, to any person obtaining a copy
6 ** of this software and associated documentation files (the "Software"), to deal
7 ** in the Software without restriction, including without limitation the rights
8 ** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 ** copies of the Software, and to permit persons to whom the Software is
10 ** furnished to do so, subject to the following conditions:
11 ** The above copyright notice and this permission notice shall be
12 ** included in all copies or substantial portions of the Software.
13 **
14 ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 ** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 ** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17 ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
18 ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
19 ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 ** USE OR OTHER DEALINGS IN THE SOFTWARE.
21 ****************************************************************************/
22 
28 #ifndef NVSRAM2_H
29 #define NVSRAM2_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_spi_master.h"
38 
64 #define NVSRAM2_STATUS_RDSR 0x05
65 #define NVSRAM2_STATUS_FRDSR 0x0A
66 #define NVSRAM2_STATUS_WRSR 0x01
67 #define NVSRAM2_STATUS_WREN 0x06
68 #define NVSRAM2_STATUS_WRDI 0x04
69 
74 #define NVSRAM2_SRAM_READ 0x03
75 #define NVSRAM2_SRAM_FREAD 0x0B
76 #define NVSRAM2_SRAM_WRITE 0x02
77 
82 #define NVSRAM2_SPEC_NV_STORE 0x3C
83 #define NVSRAM2_SPEC_NV_RECALL 0x60
84 #define NVSRAM2_SPEC_NV_ASENB 0x59
85 #define NVSRAM2_SPEC_NV_ASDISB 0x19
86 
91 #define NVSRAM2_SPEC_SLEEP 0xB9
92 #define NVSRAM2_SPEC_WRSN 0xC2
93 #define NVSRAM2_SPEC_RDSN 0xC3
94 #define NVSRAM2_SPEC_FRDSN 0xC9
95 #define NVSRAM2_SPEC_RDID 0x9F
96 #define NVSRAM2_SPEC_FRDID 0x99
97 
102 #define NVSRAM2_STATUS_RDY 0x01
103 #define NVSRAM2_STATUS_WEN 0x02
104 #define NVSRAM2_STATUS_BP0 0x04
105 #define NVSRAM2_STATUS_BP1 0x08
106 #define NVSRAM2_STATUS_SNL 0x40
107 #define NVSRAM2_STATUS_WPEN 0x80
108 
109 #define NVSRAM2_HOLD_ENABLE 0x00
110 #define NVSRAM2_HOLD_DISABLE 0x01
111 
112 #define NVSRAM2_DUMMY_BYTE 0x00
113  // nvsram2_set
114 
129 #define NVSRAM2_MAP_MIKROBUS( cfg, mikrobus ) \
130  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
131  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
132  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
133  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
134  cfg.hld = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
135 
136  // nvsram2_map // nvsram2
138 
143 typedef struct
144 {
145  // Output pins
146 
147  digital_out_t hld;
149  // Modules
150 
151  spi_master_t spi;
153  pin_name_t chip_select;
155 } nvsram2_t;
156 
161 typedef struct
162 {
163  // Communication gpio pins
164 
165  pin_name_t miso;
166  pin_name_t mosi;
167  pin_name_t sck;
168  pin_name_t cs;
170  // Additional gpio pins
171 
172  pin_name_t hld;
174  // static variable
175 
176  uint32_t spi_speed;
177  spi_master_mode_t spi_mode;
178  spi_master_chip_select_polarity_t cs_polarity;
180 } nvsram2_cfg_t;
181 
186 typedef enum
187 {
189  NVSRAM2_ERROR = -1
190 
192 
209 
224 err_t nvsram2_init ( nvsram2_t *ctx, nvsram2_cfg_t *cfg );
225 
240 
256 err_t nvsram2_generic_write ( nvsram2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
257 
273 err_t nvsram2_generic_read ( nvsram2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
274 
287 void nvsram2_hold ( nvsram2_t *ctx, uint8_t en_hold );
288 
301 void nvsram2_set_cmd ( nvsram2_t *ctx, uint8_t cmd );
302 
315 
328 
341 void nvsram2_write_status ( nvsram2_t *ctx, uint8_t data_byte );
342 
357 void nvsram2_burst_read ( nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_rx_data, uint8_t n_bytes );
358 
373 void nvsram2_burst_write ( nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_tx_data, uint8_t n_bytes );
374 
386 uint32_t nvsram2_read_id ( nvsram2_t *ctx );
387 
388 #ifdef __cplusplus
389 }
390 #endif
391 #endif // NVSRAM2_H
392  // nvsram2
394 
395 // ------------------------------------------------------------------------ END
nvsram2_burst_write
void nvsram2_burst_write(nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_tx_data, uint8_t n_bytes)
nvSRAM 2 burst write function.
nvsram2_read_status
uint8_t nvsram2_read_status(nvsram2_t *ctx)
nvSRAM 2 read status register function.
nvsram2_cfg_t::spi_speed
uint32_t spi_speed
Definition: nvsram2.h:176
nvsram2_generic_read
err_t nvsram2_generic_read(nvsram2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
nvSRAM 2 data reading function.
nvsram2_write_status
void nvsram2_write_status(nvsram2_t *ctx, uint8_t data_byte)
nvSRAM 2 write status register function.
nvsram2_cfg_t::miso
pin_name_t miso
Definition: nvsram2.h:165
nvsram2_set_cmd
void nvsram2_set_cmd(nvsram2_t *ctx, uint8_t cmd)
nvSRAM 2 send command function.
nvsram2_t::chip_select
pin_name_t chip_select
Definition: nvsram2.h:153
nvsram2_t::spi
spi_master_t spi
Definition: nvsram2.h:151
nvsram2_cfg_setup
void nvsram2_cfg_setup(nvsram2_cfg_t *cfg)
nvSRAM 2 configuration object setup function.
nvsram2_cfg_t::mosi
pin_name_t mosi
Definition: nvsram2.h:166
nvsram2_t
nvSRAM 2 Click context object.
Definition: nvsram2.h:144
nvsram2_fast_read_status
uint8_t nvsram2_fast_read_status(nvsram2_t *ctx)
nvSRAM 2 fast read status register function.
nvsram2_read_id
uint32_t nvsram2_read_id(nvsram2_t *ctx)
nvSRAM 2 read ID function.
NVSRAM2_ERROR
@ NVSRAM2_ERROR
Definition: nvsram2.h:189
nvsram2_cfg_t::hld
pin_name_t hld
Definition: nvsram2.h:172
nvsram2_t::hld
digital_out_t hld
Definition: nvsram2.h:147
nvsram2_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: nvsram2.h:177
nvsram2_init
err_t nvsram2_init(nvsram2_t *ctx, nvsram2_cfg_t *cfg)
nvSRAM 2 initialization function.
NVSRAM2_OK
@ NVSRAM2_OK
Definition: nvsram2.h:188
nvsram2_default_cfg
err_t nvsram2_default_cfg(nvsram2_t *ctx)
nvSRAM 2 default configuration function.
nvsram2_cfg_t::cs
pin_name_t cs
Definition: nvsram2.h:168
nvsram2_return_value_t
nvsram2_return_value_t
nvSRAM 2 Click return value data.
Definition: nvsram2.h:187
nvsram2_cfg_t
nvSRAM 2 Click configuration object.
Definition: nvsram2.h:162
nvsram2_cfg_t::sck
pin_name_t sck
Definition: nvsram2.h:167
nvsram2_hold
void nvsram2_hold(nvsram2_t *ctx, uint8_t en_hold)
nvSRAM 2 data enable hold operation function.
nvsram2_burst_read
void nvsram2_burst_read(nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_rx_data, uint8_t n_bytes)
nvSRAM 2 burst read function.
nvsram2_generic_write
err_t nvsram2_generic_write(nvsram2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
nvSRAM 2 data writing function.
nvsram2_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: nvsram2.h:178