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39 #ifdef PREINIT_SUPPORTED
43 #ifdef MikroCCoreVersion
44 #if MikroCCoreVersion >= 1
49 #include "drv_digital_out.h"
50 #include "drv_digital_in.h"
51 #include "drv_spi_master.h"
78 #define NVSRAM2_STATUS_RDSR 0x05
79 #define NVSRAM2_STATUS_FRDSR 0x0A
80 #define NVSRAM2_STATUS_WRSR 0x01
81 #define NVSRAM2_STATUS_WREN 0x06
82 #define NVSRAM2_STATUS_WRDI 0x04
88 #define NVSRAM2_SRAM_READ 0x03
89 #define NVSRAM2_SRAM_FREAD 0x0B
90 #define NVSRAM2_SRAM_WRITE 0x02
96 #define NVSRAM2_SPEC_NV_STORE 0x3C
97 #define NVSRAM2_SPEC_NV_RECALL 0x60
98 #define NVSRAM2_SPEC_NV_ASENB 0x59
99 #define NVSRAM2_SPEC_NV_ASDISB 0x19
105 #define NVSRAM2_SPEC_SLEEP 0xB9
106 #define NVSRAM2_SPEC_WRSN 0xC2
107 #define NVSRAM2_SPEC_RDSN 0xC3
108 #define NVSRAM2_SPEC_FRDSN 0xC9
109 #define NVSRAM2_SPEC_RDID 0x9F
110 #define NVSRAM2_SPEC_FRDID 0x99
116 #define NVSRAM2_STATUS_RDY 0x01
117 #define NVSRAM2_STATUS_WEN 0x02
118 #define NVSRAM2_STATUS_BP0 0x04
119 #define NVSRAM2_STATUS_BP1 0x08
120 #define NVSRAM2_STATUS_SNL 0x40
121 #define NVSRAM2_STATUS_WPEN 0x80
123 #define NVSRAM2_HOLD_ENABLE 0x00
124 #define NVSRAM2_HOLD_DISABLE 0x01
126 #define NVSRAM2_DUMMY_BYTE 0x00
143 #define NVSRAM2_MAP_MIKROBUS( cfg, mikrobus ) \
144 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
145 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
146 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
147 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
148 cfg.hld = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
void nvsram2_burst_write(nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_tx_data, uint8_t n_bytes)
nvSRAM 2 burst write function.
uint8_t nvsram2_read_status(nvsram2_t *ctx)
nvSRAM 2 read status register function.
uint32_t spi_speed
Definition: nvsram2.h:190
err_t nvsram2_generic_read(nvsram2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
nvSRAM 2 data reading function.
void nvsram2_write_status(nvsram2_t *ctx, uint8_t data_byte)
nvSRAM 2 write status register function.
pin_name_t miso
Definition: nvsram2.h:179
void nvsram2_set_cmd(nvsram2_t *ctx, uint8_t cmd)
nvSRAM 2 send command function.
pin_name_t chip_select
Definition: nvsram2.h:167
spi_master_t spi
Definition: nvsram2.h:165
void nvsram2_cfg_setup(nvsram2_cfg_t *cfg)
nvSRAM 2 configuration object setup function.
pin_name_t mosi
Definition: nvsram2.h:180
nvSRAM 2 Click context object.
Definition: nvsram2.h:158
uint8_t nvsram2_fast_read_status(nvsram2_t *ctx)
nvSRAM 2 fast read status register function.
uint32_t nvsram2_read_id(nvsram2_t *ctx)
nvSRAM 2 read ID function.
@ NVSRAM2_ERROR
Definition: nvsram2.h:203
pin_name_t hld
Definition: nvsram2.h:186
digital_out_t hld
Definition: nvsram2.h:161
spi_master_mode_t spi_mode
Definition: nvsram2.h:191
err_t nvsram2_init(nvsram2_t *ctx, nvsram2_cfg_t *cfg)
nvSRAM 2 initialization function.
@ NVSRAM2_OK
Definition: nvsram2.h:202
err_t nvsram2_default_cfg(nvsram2_t *ctx)
nvSRAM 2 default configuration function.
pin_name_t cs
Definition: nvsram2.h:182
nvsram2_return_value_t
nvSRAM 2 Click return value data.
Definition: nvsram2.h:201
nvSRAM 2 Click configuration object.
Definition: nvsram2.h:176
pin_name_t sck
Definition: nvsram2.h:181
void nvsram2_hold(nvsram2_t *ctx, uint8_t en_hold)
nvSRAM 2 data enable hold operation function.
void nvsram2_burst_read(nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_rx_data, uint8_t n_bytes)
nvSRAM 2 burst read function.
err_t nvsram2_generic_write(nvsram2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
nvSRAM 2 data writing function.
spi_master_chip_select_polarity_t cs_polarity
Definition: nvsram2.h:192