ccrf3 2.0.0.0
ccrf3.h
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3** Contact: https://www.mikroe.com/contact
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22
28#ifndef CCRF3_H
29#define CCRF3_H
30
31#ifdef __cplusplus
32extern "C"{
33#endif
34
35#include "drv_digital_out.h"
36#include "drv_digital_in.h"
37#include "drv_spi_master.h"
38#include "spi_specifics.h"
39
65#define CCRF3_IOCFG3 0x0000
66#define CCRF3_IOCFG2 0x0001
67#define CCRF3_IOCFG1 0x0002
68#define CCRF3_IOCFG0 0x0003
69#define CCRF3_SYNC3 0x0004
70#define CCRF3_SYNC2 0x0005
71#define CCRF3_SYNC1 0x0006
72#define CCRF3_SYNC0 0x0007
73#define CCRF3_SYNC_CFG1 0x0008
74#define CCRF3_SYNC_CFG0 0x0009
75#define CCRF3_DEVIATION_M 0x000A
76#define CCRF3_MODCFG_DEV_E 0x000B
77#define CCRF3_DCFILT_CFG 0x000C
78#define CCRF3_PREAMBLE_CFG1 0x000D
79#define CCRF3_PREAMBLE_CFG0 0x000E
80#define CCRF3_FREQ_IF_CFG 0x000F
81#define CCRF3_IQIC 0x0010
82#define CCRF3_CHAN_BW 0x0011
83#define CCRF3_MDMCFG1 0x0012
84#define CCRF3_MDMCFG0 0x0013
85#define CCRF3_SYMBOL_RATE2 0x0014
86#define CCRF3_SYMBOL_RATE1 0x0015
87#define CCRF3_SYMBOL_RATE0 0x0016
88#define CCRF3_AGC_REF 0x0017
89#define CCRF3_AGC_CS_THR 0x0018
90#define CCRF3_AGC_GAIN_ADJUST 0x0019
91#define CCRF3_AGC_CFG3 0x001A
92#define CCRF3_AGC_CFG2 0x001B
93#define CCRF3_AGC_CFG1 0x001C
94#define CCRF3_AGC_CFG0 0x001D
95#define CCRF3_FIFO_CFG 0x001E
96#define CCRF3_DEV_ADDR 0x001F
97#define CCRF3_SETTLING_CFG 0x0020
98#define CCRF3_FS_CFG 0x0021
99#define CCRF3_WOR_CFG1 0x0022
100#define CCRF3_WOR_CFG0 0x0023
101#define CCRF3_WOR_EVENT0_MSB 0x0024
102#define CCRF3_WOR_EVENT0_LSB 0x0025
103#define CCRF3_PKT_CFG2 0x0026
104#define CCRF3_PKT_CFG1 0x0027
105#define CCRF3_PKT_CFG0 0x0028
106#define CCRF3_RFEND_CFG1 0x0029
107#define CCRF3_RFEND_CFG0 0x002A
108#define CCRF3_PA_CFG2 0x002B
109#define CCRF3_PA_CFG1 0x002C
110#define CCRF3_PA_CFG0 0x002D
111#define CCRF3_PKT_LEN 0x002E
112
117#define CCRF3_IF_MIX_CFG 0x2F00
118#define CCRF3_FREQOFF_CFG 0x2F01
119#define CCRF3_TOC_CFG 0x2F02
120#define CCRF3_MARC_SPARE 0x2F03
121#define CCRF3_ECG_CFG 0x2F04
122#define CCRF3_CFM_DATA_CFG 0x2F05
123#define CCRF3_EXT_CTRL 0x2F06
124#define CCRF3_RCCAL_FINE 0x2F07
125#define CCRF3_RCCAL_COARSE 0x2F08
126#define CCRF3_RCCAL_OFFSET 0x2F09
127#define CCRF3_FREQOFF1 0x2F0A
128#define CCRF3_FREQOFF0 0x2F0B
129#define CCRF3_FREQ2 0x2F0C
130#define CCRF3_FREQ1 0x2F0D
131#define CCRF3_FREQ0 0x2F0E
132#define CCRF3_IF_ADC2 0x2F0F
133#define CCRF3_IF_ADC1 0x2F10
134#define CCRF3_IF_ADC0 0x2F11
135#define CCRF3_FS_DIG1 0x2F12
136#define CCRF3_FS_DIG0 0x2F13
137#define CCRF3_FS_CAL3 0x2F14
138#define CCRF3_FS_CAL2 0x2F15
139#define CCRF3_FS_CAL1 0x2F16
140#define CCRF3_FS_CAL0 0x2F17
141#define CCRF3_FS_CHP 0x2F18
142#define CCRF3_FS_DIVTWO 0x2F19
143#define CCRF3_FS_DSM1 0x2F1A
144#define CCRF3_FS_DSM0 0x2F1B
145#define CCRF3_FS_DVC1 0x2F1C
146#define CCRF3_FS_DVC0 0x2F1D
147#define CCRF3_FS_LBI 0x2F1E
148#define CCRF3_FS_PFD 0x2F1F
149#define CCRF3_FS_PRE 0x2F20
150#define CCRF3_FS_REG_DIV_CML 0x2F21
151#define CCRF3_FS_SPARE 0x2F22
152#define CCRF3_FS_VCO4 0x2F23
153#define CCRF3_FS_VCO3 0x2F24
154#define CCRF3_FS_VCO2 0x2F25
155#define CCRF3_FS_VCO1 0x2F26
156#define CCRF3_FS_VCO0 0x2F27
157#define CCRF3_GBIAS6 0x2F28
158#define CCRF3_GBIAS5 0x2F29
159#define CCRF3_GBIAS4 0x2F2A
160#define CCRF3_GBIAS3 0x2F2B
161#define CCRF3_GBIAS2 0x2F2C
162#define CCRF3_GBIAS1 0x2F2D
163#define CCRF3_GBIAS0 0x2F2E
164#define CCRF3_IFAMP 0x2F2F
165#define CCRF3_LNA 0x2F30
166#define CCRF3_RXMIX 0x2F31
167#define CCRF3_XOSC5 0x2F32
168#define CCRF3_XOSC4 0x2F33
169#define CCRF3_XOSC3 0x2F34
170#define CCRF3_XOSC2 0x2F35
171#define CCRF3_XOSC1 0x2F36
172#define CCRF3_XOSC0 0x2F37
173#define CCRF3_ANALOG_SPARE 0x2F38
174#define CCRF3_PA_CFG3 0x2F39
175#define CCRF3_IRQ0M 0x2F3F
176#define CCRF3_IRQ0F 0x2F40
177
182#define CCRF3_WOR_TIME1 0x2F64
183#define CCRF3_WOR_TIME0 0x2F65
184#define CCRF3_WOR_CAPTURE1 0x2F66
185#define CCRF3_WOR_CAPTURE0 0x2F67
186#define CCRF3_BIST 0x2F68
187#define CCRF3_DCFILTOFFSET_I1 0x2F69
188#define CCRF3_DCFILTOFFSET_I0 0x2F6A
189#define CCRF3_DCFILTOFFSET_Q1 0x2F6B
190#define CCRF3_DCFILTOFFSET_Q0 0x2F6C
191#define CCRF3_IQIE_I1 0x2F6D
192#define CCRF3_IQIE_I0 0x2F6E
193#define CCRF3_IQIE_Q1 0x2F6F
194#define CCRF3_IQIE_Q0 0x2F70
195#define CCRF3_RSSI1 0x2F71
196#define CCRF3_RSSI0 0x2F72
197#define CCRF3_MARCSTATE 0x2F73
198#define CCRF3_LQI_VAL 0x2F74
199#define CCRF3_PQT_SYNC_ERR 0x2F75
200#define CCRF3_DEM_STATUS 0x2F76
201#define CCRF3_FREQOFF_EST1 0x2F77
202#define CCRF3_FREQOFF_EST0 0x2F78
203#define CCRF3_AGC_GAIN3 0x2F79
204#define CCRF3_AGC_GAIN2 0x2F7A
205#define CCRF3_AGC_GAIN1 0x2F7B
206#define CCRF3_AGC_GAIN0 0x2F7C
207#define CCRF3_CFM_RX_DATA_OUT 0x2F7D
208#define CCRF3_CFM_TX_DATA_IN 0x2F7E
209#define CCRF3_ASK_SOFT_RX_DATA 0x2F7F
210#define CCRF3_RNDGEN 0x2F80
211#define CCRF3_MAGN2 0x2F81
212#define CCRF3_MAGN1 0x2F82
213#define CCRF3_MAGN0 0x2F83
214#define CCRF3_ANG1 0x2F84
215#define CCRF3_ANG0 0x2F85
216#define CCRF3_CHFILT_I2 0x2F86
217#define CCRF3_CHFILT_I1 0x2F87
218#define CCRF3_CHFILT_I0 0x2F88
219#define CCRF3_CHFILT_Q2 0x2F89
220#define CCRF3_CHFILT_Q1 0x2F8A
221#define CCRF3_CHFILT_Q0 0x2F8B
222#define CCRF3_GPIO_STATUS 0x2F8C
223#define CCRF3_FSCAL_CTRL 0x2F8D
224#define CCRF3_PHASE_ADJUST 0x2F8E
225#define CCRF3_PARTNUMBER 0x2F8F
226#define CCRF3_PARTVERSION 0x2F90
227#define CCRF3_SERIAL_STATUS 0x2F91
228#define CCRF3_MODEM_STATUS1 0x2F92
229#define CCRF3_MODEM_STATUS0 0x2F93
230#define CCRF3_MARC_STATUS1 0x2F94
231#define CCRF3_MARC_STATUS0 0x2F95
232#define CCRF3_PA_IFAMP_TEST 0x2F96
233#define CCRF3_FSRF_TEST 0x2F97
234#define CCRF3_PRE_TEST 0x2F98
235#define CCRF3_PRE_OVR 0x2F99
236#define CCRF3_ADC_TEST 0x2F9A
237#define CCRF3_DVC_TEST 0x2F9B
238#define CCRF3_ATEST 0x2F9C
239#define CCRF3_ATEST_LVDS 0x2F9D
240#define CCRF3_ATEST_MODE 0x2F9E
241#define CCRF3_XOSC_TEST1 0x2F9F
242#define CCRF3_XOSC_TEST0 0x2FA0
243
244#define CCRF3_RXFIRST 0x2FD2
245#define CCRF3_TXFIRST 0x2FD3
246#define CCRF3_RXLAST 0x2FD4
247#define CCRF3_TXLAST 0x2FD5
248#define CCRF3_NUM_TXBYTES 0x2FD6
249#define CCRF3_NUM_RXBYTES 0x2FD7
250#define CCRF3_FIFO_NUM_TXBYTES 0x2FD8
251#define CCRF3_FIFO_NUM_RXBYTES 0x2FD9
252 // ccrf3_reg
254
269#define CCRF3_STATUS_CHIP_RDYN_BM 0x80
270#define CCRF3_STATUS_STATE_BM 0x70
271#define CCRF3_STATUS_FIFO_BYTES_AVA_BM 0x0F
272
273#define CCRF3_STATUS_ERROR 0x00
274#define CCRF3_STATUS_OK 0x01
275
276#define CCRF3_IDLE_MODE 0x01
277#define CCRF3_TX_MODE 0x02
278#define CCRF3_RX_MODE 0x03
279
284#define CCRF3_SINGLE_TXFIFO 0x003F
285#define CCRF3_BURST_TXFIFO 0x007F
286#define CCRF3_SINGLE_RXFIFO 0x00BF
287#define CCRF3_BURST_RXFIFO 0x00FF
288
289#define CCRF3_LQI_CRC_OK_BM 0x80
290#define CCRF3_LQI_EST_BM 0x7F
291
296#define CCRF3_SRES 0x30
297#define CCRF3_SFSTXON 0x31
298#define CCRF3_SXOFF 0x32
299#define CCRF3_SCAL 0x33
300#define CCRF3_SRX 0x34
301#define CCRF3_STX 0x35
302#define CCRF3_SIDLE 0x36
303#define CCRF3_SWOR 0x38
304#define CCRF3_SPWD 0x39
305#define CCRF3_SFRX 0x3A
306#define CCRF3_SFTX 0x3B
307#define CCRF3_SWORRST 0x3C
308#define CCRF3_SNOP 0x3D
309#define CCRF3_AFC 0x37
310
315#define CCRF3_STATE_IDLE 0x00
316#define CCRF3_STATE_RX 0x10
317#define CCRF3_STATE_TX 0x20
318#define CCRF3_STATE_FSTXON 0x30
319#define CCRF3_STATE_CALIBRATE 0x40
320#define CCRF3_STATE_SETTLING 0x50
321#define CCRF3_STATE_RXFIFO_ERROR 0x60
322#define CCRF3_STATE_TXFIFO_ERROR 0x70
323
324#define CCRF3_RADIO_BURST_ACCESS 0x40
325#define CCRF3_RADIO_SINGLE_ACCESS 0x00
326#define CCRF3_RADIO_READ_ACCESS 0x80
327#define CCRF3_RADIO_WRITE_ACCESS 0x00
328
329
338#define CCRF3_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
339#define CCRF3_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
340 // ccrf3_set
342
357#define CCRF3_MAP_MIKROBUS( cfg, mikrobus ) \
358 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
359 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
360 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
361 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
362 cfg.gp0 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
363 cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
364 cfg.gp2 = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
365 cfg.gp3 = MIKROBUS( mikrobus, MIKROBUS_INT )
366 // ccrf3_map // ccrf3
369
374typedef struct
375{
376 // Output pins
377 digital_out_t cs;
378 digital_out_t rst;
380 // Input pins
381 digital_in_t gp0;
382 digital_in_t gp2;
383 digital_in_t gp3;
384 digital_in_t miso;
386 // Modules
387 spi_master_t spi;
389 pin_name_t chip_select;
392} ccrf3_t;
393
398typedef struct
399{
400 // Communication gpio pins
401 pin_name_t miso;
402 pin_name_t mosi;
403 pin_name_t sck;
404 pin_name_t cs;
406 // Additional gpio pins
407 pin_name_t gp0;
408 pin_name_t rst;
409 pin_name_t gp2;
410 pin_name_t gp3;
412 // static variable
413 uint32_t spi_speed;
414 spi_master_mode_t spi_mode;
415 spi_master_chip_select_polarity_t cs_polarity;
418
423typedef enum
424{
426 CCRF3_ERROR = -1
427
429
446
461err_t ccrf3_init ( ccrf3_t *ctx, ccrf3_cfg_t *cfg );
462
477
488
498uint8_t ccrf3_cmd_strobe ( ccrf3_t *ctx, uint8_t cmd );
499
511void ccrf3_read_write_burst_single ( ccrf3_t *ctx, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes );
512
525uint8_t ccrf3_8bit_reg_access ( ccrf3_t *ctx, char access_type, uint8_t reg_address, uint8_t *rw_data,
526 uint16_t n_bytes );
527
541uint8_t ccrf3_16bit_reg_access ( ccrf3_t *ctx, uint8_t access_type, uint8_t ext_address,
542 uint8_t reg_address, uint8_t *rw_data, uint8_t n_bytes );
543
555err_t ccrf3_read_reg ( ccrf3_t *ctx, uint16_t reg_address, uint8_t *read_data, uint8_t n_bytes );
556
568uint8_t ccrf3_write_reg ( ccrf3_t *ctx, uint16_t reg_address, uint8_t *write_data, uint8_t n_bytes );
569
580uint8_t ccrf3_write_reg_single( ccrf3_t *ctx, uint16_t reg_address, uint8_t write_data );
581
592uint8_t ccrf3_write_tx_fifo ( ccrf3_t *ctx, uint8_t *write_data, uint8_t n_bytes );
593
604uint8_t ccrf3_read_rx_fifo ( ccrf3_t *ctx, uint8_t *read_data, uint8_t n_bytes );
605
615
625
635
644uint8_t ccrf3_read_gp0 ( ccrf3_t *ctx );
645
654uint8_t ccrf3_read_gp2 ( ccrf3_t *ctx );
655
664uint8_t ccrf3_read_gp3 ( ccrf3_t *ctx );
665
676void ccrf3_send_tx_data ( ccrf3_t *ctx, uint8_t *tx_data, uint8_t n_bytes );
677
687uint8_t ccrf3_receive_rx_data ( ccrf3_t *ctx, uint8_t *rx_data );
688
689#ifdef __cplusplus
690}
691#endif
692#endif // CCRF3_H
693 // ccrf3
695
696// ------------------------------------------------------------------------ END
ccrf3_return_value_t
ccRF 3 Click return value data.
Definition: ccrf3.h:424
@ CCRF3_ERROR
Definition: ccrf3.h:426
@ CCRF3_OK
Definition: ccrf3.h:425
uint8_t ccrf3_write_reg_single(ccrf3_t *ctx, uint16_t reg_address, uint8_t write_data)
Write one byte data function.
uint8_t ccrf3_8bit_reg_access(ccrf3_t *ctx, char access_type, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes)
Access 8-bit register function.
uint8_t ccrf3_read_gp3(ccrf3_t *ctx)
Read state of GP3 pin function.
uint8_t ccrf3_cmd_strobe(ccrf3_t *ctx, uint8_t cmd)
Set command strobe function.
uint8_t ccrf3_read_gp2(ccrf3_t *ctx)
Read state of GP2 pin function.
void ccrf3_send_tx_data(ccrf3_t *ctx, uint8_t *tx_data, uint8_t n_bytes)
Send TX data function.
void ccrf3_read_write_burst_single(ccrf3_t *ctx, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes)
Read or write burst single function.
void ccrf3_hw_reset(ccrf3_t *ctx)
Hardware reset function.
uint8_t ccrf3_16bit_reg_access(ccrf3_t *ctx, uint8_t access_type, uint8_t ext_address, uint8_t reg_address, uint8_t *rw_data, uint8_t n_bytes)
Access 16-bit register function.
uint8_t ccrf3_read_gp0(ccrf3_t *ctx)
Read state of GP0 pin function.
void ccrf3_set_tx_mode(ccrf3_t *ctx)
Set TX mode function.
err_t ccrf3_read_reg(ccrf3_t *ctx, uint16_t reg_address, uint8_t *read_data, uint8_t n_bytes)
Read the byte of data function.
void ccrf3_set_rx_mode(ccrf3_t *ctx)
Set RX mode function.
err_t ccrf3_init(ccrf3_t *ctx, ccrf3_cfg_t *cfg)
ccRF 3 initialization function.
void ccrf3_manual_calibration(ccrf3_t *ctx)
Manual calibration function.
err_t ccrf3_default_cfg(ccrf3_t *ctx)
ccRF 3 default configuration function.
uint8_t ccrf3_write_reg(ccrf3_t *ctx, uint16_t reg_address, uint8_t *write_data, uint8_t n_bytes)
Write sequential data function.
uint8_t ccrf3_write_tx_fifo(ccrf3_t *ctx, uint8_t *write_data, uint8_t n_bytes)
Write TX FIFO register function.
uint8_t ccrf3_receive_rx_data(ccrf3_t *ctx, uint8_t *rx_data)
Receive RX data function.
void ccrf3_cfg_setup(ccrf3_cfg_t *cfg)
ccRF 3 configuration object setup function.
uint8_t ccrf3_read_rx_fifo(ccrf3_t *ctx, uint8_t *read_data, uint8_t n_bytes)
Read RX FIFO register function.
This file contains SPI specific macros, functions, etc.
ccRF 3 Click configuration object.
Definition: ccrf3.h:399
pin_name_t gp0
Definition: ccrf3.h:407
pin_name_t gp2
Definition: ccrf3.h:409
pin_name_t gp3
Definition: ccrf3.h:410
spi_master_chip_select_polarity_t cs_polarity
Definition: ccrf3.h:415
pin_name_t sck
Definition: ccrf3.h:403
spi_master_mode_t spi_mode
Definition: ccrf3.h:414
pin_name_t mosi
Definition: ccrf3.h:402
uint32_t spi_speed
Definition: ccrf3.h:413
pin_name_t miso
Definition: ccrf3.h:401
pin_name_t rst
Definition: ccrf3.h:408
pin_name_t cs
Definition: ccrf3.h:404
ccRF 3 Click context object.
Definition: ccrf3.h:375
digital_out_t cs
Definition: ccrf3.h:377
spi_master_t spi
Definition: ccrf3.h:387
digital_in_t miso
Definition: ccrf3.h:384
uint16_t packet_counter
Definition: ccrf3.h:391
digital_in_t gp2
Definition: ccrf3.h:382
digital_in_t gp0
Definition: ccrf3.h:381
digital_in_t gp3
Definition: ccrf3.h:383
digital_out_t rst
Definition: ccrf3.h:378
pin_name_t chip_select
Definition: ccrf3.h:389