ecg2  2.0.0.0
ecg2.h
Go to the documentation of this file.
1 /****************************************************************************
2 ** Copyright (C) 2020 MikroElektronika d.o.o.
3 ** Contact: https://www.mikroe.com/contact
4 **
5 ** Permission is hereby granted, free of charge, to any person obtaining a copy
6 ** of this software and associated documentation files (the "Software"), to deal
7 ** in the Software without restriction, including without limitation the rights
8 ** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 ** copies of the Software, and to permit persons to whom the Software is
10 ** furnished to do so, subject to the following conditions:
11 ** The above copyright notice and this permission notice shall be
12 ** included in all copies or substantial portions of the Software.
13 **
14 ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 ** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 ** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17 ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
18 ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
19 ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 ** USE OR OTHER DEALINGS IN THE SOFTWARE.
21 ****************************************************************************/
22 
28 #ifndef ECG2_H
29 #define ECG2_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_spi_master.h"
38 #include "spi_specifics.h"
39 #include "drv_analog_in.h"
40 
61 #define ECG2_ID_REG 0x00
62 #define ECG2_CONFIG1_REG 0x01
63 #define ECG2_CONFIG2_REG 0x02
64 #define ECG2_CONFIG3_REG 0x03
65 #define ECG2_LOFF_REG 0x04
66 #define ECG2_CH1SET_REG 0x05
67 #define ECG2_CH2SET_REG 0x06
68 #define ECG2_CH3SET_REG 0x07
69 #define ECG2_CH4SET_REG 0x08
70 #define ECG2_CH5SET_REG 0x09
71 #define ECG2_CH6SET_REG 0x0A
72 #define ECG2_CH7SET_REG 0x0B
73 #define ECG2_CH8SET_REG 0x0C
74 #define ECG2_RLD_SENSP_REG 0x0D
75 #define ECG2_RLD_SENSN_REG 0x0E
76 #define ECG2_LOFF_SENSP_REG 0x0F
77 #define ECG2_LOFF_SENSN_REG 0x10
78 #define ECG2_LOFF_FLIP_REG 0x11
79 #define ECG2_LOFF_STATP_REG 0x12
80 #define ECG2_LOFF_STATN_REG 0x13
81 #define ECG2_GPIO_REG 0x14
82 #define ECG2_PACE_REG 0x15
83 #define ECG2_CONFIG4_REG 0x17
84 #define ECG2_WCT1_REG 0x18
85 #define ECG2_WCT2_REG 0x19
86  // ecg2_reg
88 
108 #define ECG2_WAKEUP_CMD 0x02
109 #define ECG2_STANDBY_CMD 0x04
110 #define ECG2_RESET_CMD 0x06
111 #define ECG2_START_CONVERSION 0x08
112 #define ECG2_STOP_CONVERSION 0x0A
113 #define ECG2_ENABLE_READ_DATA_CONT_MODE 0x10
114 #define ECG2_STOP_DATA_CONT_MODE 0x11
115 #define ECG2_READ_DATA_CMD 0x12
116 #define ECG2_SPI_CMD_WRITE 0x40
117 #define ECG2_SPI_CMD_READ 0x20
118 
123 #define ECG2_CONFIG1_REG_DEFAULT_VAL 0x04
124 #define ECG2_CONFIG2_REG_DEFAULT_VAL 0x20
125 #define ECG2_CONFIG3_REG_DEFAULT_VAL 0x40
126 
131 #define ECG2_CFG_DAISY_ENABLE 0x00
132 #define ECG2_CFG_MULTI_READBACK 0x40
133 
138 #define ECG2_CFG_CLK_ENABLE 0x20
139 #define ECG2_CFG_CLK_DISABLE 0x00
140 
145 #define ECG2_CFG_DATA_SPEED_8K 0x00
146 #define ECG2_CFG_DATA_SPEED_4K 0x01
147 #define ECG2_CFG_DATA_SPEED_2K 0x02
148 #define ECG2_CFG_DATA_SPEED_1K 0x03
149 #define ECG2_CFG_DATA_SPEED_500 0x04
150 #define ECG2_CFG_DATA_SPEED_250 0x05
151 #define ECG2_CFG_DATA_SPEED_125 0x06
152 #define ECG2_CFG_DATA_SPEED_OFF 0x07
153 
158 #define ECG2_CFG_INT_TEST_EXT 0x10
159 #define ECG2_CFG_INT_TEST_INT 0x00
160 
165 #define ECG2_CFG_FREQ_F_DIV_2_TO_21 0x00
166 #define ECG2_CFG_FREQ_F_DIV_2_TO_20 0x01
167 #define ECG2_CFG_FREQ_NOT_USED 0x02
168 #define ECG2_CFG_FREQ_AT_DC 0x03
169 
174 #define ECG2_CFG_AMPLITUDE_NEGATIVE_1 0x00
175 #define ECG2_CFG_AMPLITUDE_NEGATIVE_2 0x01
176 
181 #define ECG2_CFG_ENABLE_INT_BUFFER 0x80
182 #define ECG2_CFG_DISABLE_INT_BUFFER 0x00
183 
184 #define ECG2_CFG_REFBUF_ENABLE 0x80
185 #define ECG2_CFG_REFBUF_DISABLE 0x00
186 
187 #define ECG2_CFG_INTERNAL_RLDREF 0x08
188 #define ECG2_CFG_EXTERNAL_RLDREF 0x00
189 
190 #define ECG2_CFG_RLD_ENABLE 0x0C
191 #define ECG2_CFG_RLD_DISABLE 0x00
192 
193 #define ECG2_CFG_RLD_SENSE_ENABLE 0x02
194 #define ECG2_CFG_RLD_SENSE_DISABLE 0x00
195 
196 #define ECG2_CFG_RLD_NOT_CONNECTED 0x01
197 #define ECG2_CFG_RLD_CONNECTED 0x00
198 
203 #define ECG2_CFG_VREF_2V4 0x00
204 #define ECG2_CFG_VREF_4V 0x20
205 
210 #define ECG2_CFG_COMPARATOR_P_95 0x00
211 #define ECG2_CFG_COMPARATOR_P_92_5 0x20
212 #define ECG2_CFG_COMPARATOR_P_90 0x40
213 #define ECG2_CFG_COMPARATOR_P_87_5 0x60
214 #define ECG2_CFG_COMPARATOR_P_85 0x80
215 #define ECG2_CFG_COMPARATOR_P_80 0xA0
216 #define ECG2_CFG_COMPARATOR_P_75 0xC0
217 #define ECG2_CFG_COMPARATOR_P_70 0xE0
218 
223 #define ECG2_CFG_COMPARATOR_N_5 0x00
224 #define ECG2_CFG_COMPARATOR_N_7_5 0x20
225 #define ECG2_CFG_COMPARATOR_N_10 0x40
226 #define ECG2_CFG_COMPARATOR_N_12_5 0x60
227 #define ECG2_CFG_COMPARATOR_N_15 0x80
228 #define ECG2_CFG_COMPARATOR_N_20 0xA0
229 #define ECG2_CFG_COMPARATOR_N_25 0xC0
230 #define ECG2_CFG_COMPARATOR_N_30 0xE0
231 
236 #define ECG2_CFG_VLEAD_OFF 0x00
237 #define ECG2_CFG_VLEAD_EN 0x10
238 
239 #define ECG2_CFG_ILEAD_OFF_4nA 0x00
240 #define ECG2_CFG_ILEAD_OFF_8nA 0x04
241 #define ECG2_CFG_ILEAD_OFF_12nA 0x08
242 #define ECG2_CFG_ILEAD_OFF_16nA 0x0C
243 
244 #define ECG2_CFG_FLEAD_OFF_AC_OFF 0x01
245 #define ECG2_CFG_FLEAD_OFF_NOT_USED 0x02
246 #define ECG2_CFG_FLEAD_OFF_DC_OFF 0x03
247 
252 #define ECG2_CFG_NORMAL_MODE 0x00
253 #define ECG2_CFG_POWER_DOWN 0x80
254 
259 #define ECG2_CFG_PGA_GAIN_6 0x00
260 #define ECG2_CFG_PGA_GAIN_1 0x01
261 #define ECG2_CFG_PGA_GAIN_2 0x02
262 #define ECG2_CFG_PGA_GAIN_3 0x03
263 #define ECG2_CFG_PGA_GAIN_4 0x04
264 #define ECG2_CFG_PGA_GAIN_8 0x05
265 #define ECG2_CFG_PGA_GAIN_12 0x06
266 
271 #define ECG2_CFG_MUX_NORMAL_ELECTRODE 0x00
272 #define ECG2_CFG_MUX_SHORTED_INPUT 0x01
273 #define ECG2_CFG_MUX_RLD_MEASURMENTS 0x02
274 #define ECG2_CFG_MUX_MVDD_MEASURMENTS 0x03
275 #define ECG2_CFG_MUX_TEMPERATURE_SENSOR 0x04
276 #define ECG2_CFG_MUX_TEST_SIGNAL 0x05
277 #define ECG2_CFG_MUX_RLD_DRP 0x06
278 #define ECG2_CFG_MUX_RLD_DRN 0x07
279 
284 #define ECG2_CHANNEL_ODD_CHANNEL_1 0x00
285 #define ECG2_CHANNEL_ODD_CHANNEL_3 0x01
286 #define ECG2_CHANNEL_ODD_CHANNEL_5 0x02
287 #define ECG2_CHANNEL_ODD_CHANNEL_7 0x03
288 
289 #define ECG2_CHANNEL_EVEN_CHANNEL_2 0x00
290 #define ECG2_CHANNEL_EVEN_CHANNEL_4 0x01
291 #define ECG2_CHANNEL_EVEN_CHANNEL_6 0x02
292 #define ECG2_CHANNEL_EVEN_CHANNEL_8 0x03
293 
294 #define ECG2_CHANNEL_ENABLE 0x01
295 #define ECG2_CHANNEL_DISABLE 0x00
296 
297 #define ECG2_DATA_READY 0x01
298 
306 #define ECG2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
307 #define ECG2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
308  // ecg2_set
310 
325 #define ECG2_MAP_MIKROBUS( cfg, mikrobus ) \
326  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
327  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
328  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
329  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
330  cfg.an = MIKROBUS( mikrobus, MIKROBUS_AN ); \
331  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
332  cfg.pwd = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
333  cfg.drd = MIKROBUS( mikrobus, MIKROBUS_INT )
334  // ecg2_map // ecg2
337 
342 typedef struct
343 {
344  // Output pins
345  digital_out_t rst;
346  digital_out_t pwd;
348  // Input pins
349  digital_in_t drd;
351  // Modules
352  spi_master_t spi;
354  pin_name_t chip_select;
356  analog_in_t adc;
358 } ecg2_t;
359 
364 typedef struct
365 {
366  // Communication gpio pins
367  pin_name_t miso;
368  pin_name_t mosi;
369  pin_name_t sck;
370  pin_name_t cs;
372  // Additional gpio pins
373  pin_name_t an;
374  pin_name_t rst;
375  pin_name_t pwd;
376  pin_name_t drd;
378  // static variable
379  uint32_t spi_speed;
380  spi_master_mode_t spi_mode;
381  spi_master_chip_select_polarity_t cs_polarity;
383  analog_in_resolution_t resolution;
384  float vref;
386 } ecg2_cfg_t;
387 
392 typedef enum
393 {
394  ECG2_OK = 0,
395  ECG2_ERROR = -1
396 
398 
415 
429 err_t ecg2_init ( ecg2_t *ctx, ecg2_cfg_t *cfg );
430 
444 err_t ecg2_default_cfg ( ecg2_t *ctx );
445 
460 err_t ecg2_generic_write ( ecg2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
461 
476 err_t ecg2_generic_read ( ecg2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
477 
489 err_t ecg2_read_an_pin_value ( ecg2_t *ctx, uint16_t *data_out );
490 
504 err_t ecg2_write_register ( ecg2_t *ctx, uint8_t reg, uint8_t data_in );
505 
519 err_t ecg2_read_register ( ecg2_t *ctx, uint8_t reg, uint8_t *data_out );
520 
535 err_t ecg2_multi_write ( ecg2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
536 
551 err_t ecg2_multi_read ( ecg2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
552 
564 err_t ecg2_send_command ( ecg2_t *ctx, uint8_t command );
565 
573 void ecg2_hw_reset ( ecg2_t *ctx );
574 
582 uint8_t ecg2_get_device_id( ecg2_t *ctx );
583 
595 err_t ecg2_configure_channel ( ecg2_t *ctx, uint8_t channel, uint8_t enable, uint8_t pga_gain,
596  int8_t channel_input);
597 
606 void ecg2_right_leg_positive_drive_set ( ecg2_t *ctx, uint8_t data_in );
607 
616 void ecg2_right_leg_negative_drive_set ( ecg2_t *ctx, uint8_t data_in );
617 
626 void ecg2_lead_off_positive_channel_select ( ecg2_t *ctx, uint8_t data_in );
627 
636 void ecg2_lead_off_negative_channel_select ( ecg2_t *ctx, uint8_t data_in );
637 
646 void ecg2_lead_off_current_direction_select ( ecg2_t *ctx, uint8_t data_in );
647 
657 err_t ecg2_pace_detect_even_channels_select ( ecg2_t *ctx, uint8_t select );
658 
668 err_t ecg2_pace_detect_odd_channels_select ( ecg2_t *ctx, uint8_t select );
669 
678 void ecg2_wilson_center_terminal_configure ( ecg2_t *ctx, uint16_t set );
679 
687 uint8_t ecg2_data_ready ( ecg2_t *ctx );
688 
701 err_t ecg2_read_data ( ecg2_t *ctx, uint8_t *data_out, uint8_t len );
702 
715 err_t ecg2_read_channel_data ( ecg2_t *ctx, uint8_t channel, uint16_t *data_out );
716 
717 #ifdef __cplusplus
718 }
719 #endif
720 #endif // ECG2_H
721  // ecg2
723 
724 // ------------------------------------------------------------------------ END
ecg2_init
err_t ecg2_init(ecg2_t *ctx, ecg2_cfg_t *cfg)
ECG 2 initialization function.
ecg2_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: ecg2.h:381
ecg2_lead_off_current_direction_select
void ecg2_lead_off_current_direction_select(ecg2_t *ctx, uint8_t data_in)
ECG 2 lead off current direction drive settings function.
ecg2_read_data
err_t ecg2_read_data(ecg2_t *ctx, uint8_t *data_out, uint8_t len)
ECG 2 read ADC data function.
ecg2_t::drd
digital_in_t drd
Definition: ecg2.h:349
ecg2_get_device_id
uint8_t ecg2_get_device_id(ecg2_t *ctx)
ECG 2 get device id function.
ecg2_cfg_t::vref
float vref
Definition: ecg2.h:384
ecg2_cfg_t::mosi
pin_name_t mosi
Definition: ecg2.h:368
ecg2_t::pwd
digital_out_t pwd
Definition: ecg2.h:346
ecg2_right_leg_positive_drive_set
void ecg2_right_leg_positive_drive_set(ecg2_t *ctx, uint8_t data_in)
ECG 2 right leg positive drive settings function.
ecg2_generic_write
err_t ecg2_generic_write(ecg2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
ECG 2 data writing function.
ecg2_configure_channel
err_t ecg2_configure_channel(ecg2_t *ctx, uint8_t channel, uint8_t enable, uint8_t pga_gain, int8_t channel_input)
ECG 2 configure channel function.
ecg2_write_register
err_t ecg2_write_register(ecg2_t *ctx, uint8_t reg, uint8_t data_in)
ECG 2 register data write function.
ecg2_cfg_t::miso
pin_name_t miso
Definition: ecg2.h:367
ecg2_generic_read
err_t ecg2_generic_read(ecg2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
ECG 2 data reading function.
ecg2_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: ecg2.h:380
spi_specifics.h
This file contains SPI specific macros, functions, etc.
ecg2_t
ECG 2 Click context object.
Definition: ecg2.h:343
ecg2_t::chip_select
pin_name_t chip_select
Definition: ecg2.h:354
ecg2_pace_detect_even_channels_select
err_t ecg2_pace_detect_even_channels_select(ecg2_t *ctx, uint8_t select)
ECG 2 pace detect even chanels drive settings function.
ecg2_cfg_t
ECG 2 Click configuration object.
Definition: ecg2.h:365
ecg2_pace_detect_odd_channels_select
err_t ecg2_pace_detect_odd_channels_select(ecg2_t *ctx, uint8_t select)
ECG 2 pace detect odd chanels drive settings function.
ecg2_wilson_center_terminal_configure
void ecg2_wilson_center_terminal_configure(ecg2_t *ctx, uint16_t set)
ECG 2 right leg positive drive settings function.
ecg2_t::spi
spi_master_t spi
Definition: ecg2.h:352
ecg2_t::rst
digital_out_t rst
Definition: ecg2.h:345
ecg2_lead_off_negative_channel_select
void ecg2_lead_off_negative_channel_select(ecg2_t *ctx, uint8_t data_in)
ECG 2 lead off negative drive settings function.
ecg2_read_register
err_t ecg2_read_register(ecg2_t *ctx, uint8_t reg, uint8_t *data_out)
ECG 2 register data reading function.
ecg2_cfg_t::drd
pin_name_t drd
Definition: ecg2.h:376
ecg2_cfg_t::pwd
pin_name_t pwd
Definition: ecg2.h:375
ecg2_cfg_setup
void ecg2_cfg_setup(ecg2_cfg_t *cfg)
ECG 2 configuration object setup function.
ecg2_cfg_t::sck
pin_name_t sck
Definition: ecg2.h:369
ecg2_read_an_pin_value
err_t ecg2_read_an_pin_value(ecg2_t *ctx, uint16_t *data_out)
ECG 2 read AN pin value function.
ecg2_data_ready
uint8_t ecg2_data_ready(ecg2_t *ctx)
ECG 2 is data ready function.
ecg2_return_value_t
ecg2_return_value_t
ECG 2 Click return value data.
Definition: ecg2.h:393
ecg2_hw_reset
void ecg2_hw_reset(ecg2_t *ctx)
ECG 2 hardware reset function.
ecg2_send_command
err_t ecg2_send_command(ecg2_t *ctx, uint8_t command)
ECG 2 send command function.
ecg2_cfg_t::cs
pin_name_t cs
Definition: ecg2.h:370
ecg2_default_cfg
err_t ecg2_default_cfg(ecg2_t *ctx)
ECG 2 default configuration function.
ecg2_right_leg_negative_drive_set
void ecg2_right_leg_negative_drive_set(ecg2_t *ctx, uint8_t data_in)
ECG 2 right leg negative drive settings function.
ecg2_lead_off_positive_channel_select
void ecg2_lead_off_positive_channel_select(ecg2_t *ctx, uint8_t data_in)
ECG 2 lead off positive drive settings function.
ecg2_read_channel_data
err_t ecg2_read_channel_data(ecg2_t *ctx, uint8_t channel, uint16_t *data_out)
ECG 2 read data channel function.
ECG2_ERROR
@ ECG2_ERROR
Definition: ecg2.h:395
ecg2_cfg_t::resolution
analog_in_resolution_t resolution
Definition: ecg2.h:383
ecg2_cfg_t::rst
pin_name_t rst
Definition: ecg2.h:374
ECG2_OK
@ ECG2_OK
Definition: ecg2.h:394
ecg2_multi_write
err_t ecg2_multi_write(ecg2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
ECG 2 data multi writing function.
ecg2_cfg_t::an
pin_name_t an
Definition: ecg2.h:373
ecg2_t::adc
analog_in_t adc
Definition: ecg2.h:356
ecg2_multi_read
err_t ecg2_multi_read(ecg2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
ECG 2 data multi reading function.
ecg2_cfg_t::spi_speed
uint32_t spi_speed
Definition: ecg2.h:379