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35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_spi_master.h"
60 #define FIXED_FILTER_ADDRESS
68 #define MCP251863_FIFO_08TO15_IMPLEMENTED
69 #define MCP251863_FIFO_16TO31_IMPLEMENTED
77 #define MCP251863_FILT_08TO15_IMPLEMENTED
78 #define MCP251863_FILT_16TO31_IMPLEMENTED
86 #define CAN_INTERNAL_OSC_PRESENT
94 #define CAN_RESTRICTED_MODE_PRESENT
102 #define CAN_TXQUEUE_IMPLEMENTED
111 #define USERADDRESS_TIMES_FOUR
115 #define N_MCP2518_CTRL_REGS 5
118 #define MCP251863_MAX_TXQUEUE_ATTEMPTS 50
119 #define MCP251863_TX_REQUEST_ID 0x300
120 #define MCP251863_TX_RESPONSE_ID 0x301
122 #define MCP251863_CRCBASE 0xFFFF
123 #define MCP251863_CRCUPPER 1
124 #define MCP251863_DRV_CANFDSPI_INDEX_0 0
125 #define MCP251863_SPI_DEFAULT_BUFFER_LENGTH 96
127 #define MCP251863_ISO_CRC 1
129 #define MCP251863_MAX_MSG_SIZE 76
131 #define MCP251863_MAX_DATA_BYTES 64
133 #define MCP251863_INS_RESET 0x00
134 #define MCP251863_INS_READ 0x03
135 #define MCP251863_INS_READ_CRC 0x0B
136 #define MCP251863_INS_WRITE 0x02
137 #define MCP251863_INS_WRITE_CRC 0x0A
138 #define MCP251863_INS_WRITE_SAFE 0x0C
141 #define MCP251863_FIFO_OFFSET ( 3 * 4 )
142 #define MCP251863_FILTER_OFFSET ( 2 * 4 )
144 #ifdef CAN_TXQUEUE_IMPLEMENTED
145 #define MCP251863_REG_CITXQCON 0x050
146 #define MCP251863_REG_CITXQSTA 0x054
147 #define MCP251863_REG_CITXQUA 0x058
150 #ifdef FIXED_FILTER_ADDRESS
151 #define MCP251863_REG_CIFLTCON 0x1D0
152 #define MCP251863_REG_CIFLTOBJ 0x1F0
153 #define MCP251863_REG_CIMASK 0x1F4
155 #define MCP251863_REG_CIFLTCON ( MCP251863_REG_CIFIFOCON + ( MCP251863_FIFO_OFFSET * MCP251863_FIFO_TOTAL_CHANNELS ) )
156 #define MCP251863_REG_CIFLTOBJ ( MCP251863_REG_CIFLTCON + MCP251863_FIFO_TOTAL_CHANNELS )
157 #define MCP251863_REG_CIMASK ( MCP251863_REG_CIFLTOBJ + 4 )
160 #define MCP251863_REG_OSC 0xE00
161 #define MCP251863_REG_IOCON 0xE04
162 #define MCP251863_REG_CRC 0xE08
163 #define MCP251863_REG_ECCCON 0xE0C
164 #define MCP251863_REG_ECCSTA 0xE10
166 #define MCP251863_RAM_SIZE 2048
167 #define MCP251863_RAMADDR_START 0x400
168 #define MCP251863_RAMADDR_END ( MCP251863_RAMADDR_START + MCP251863_RAM_SIZE )
170 #define MCP251863_LOW_POWER_MODE_EN 0x08
171 #define MCP251863_LOW_POWER_MODE_DIS 0x00
172 #define MCP251863_WAKEUP_INTERR_EN 0x40
174 #define MCP251863_REG_CICON 0x000
175 #define MCP251863_REG_CINBTCFG 0x004
176 #define MCP251863_REG_CIDBTCFG 0x008
177 #define MCP251863_REG_CITDC 0x00C
179 #define MCP251863_REG_CITBC 0x010
180 #define MCP251863_REG_CITSCON 0x014
181 #define MCP251863_REG_CIVEC 0x018
182 #define MCP251863_REG_CIINT 0x01C
183 #define MCP251863_REG_CIINTFLAG MCP251863_REG_CIINT
184 #define MCP251863_REG_CIINTENABLE ( MCP251863_REG_CIINT + 2 )
186 #define MCP251863_REG_CIRXIF 0x020
187 #define MCP251863_REG_CITXIF 0x024
188 #define MCP251863_REG_CIRXOVIF 0x028
189 #define MCP251863_REG_CITXATIF 0x02C
191 #define MCP251863_REG_CITXREQ 0x030
192 #define MCP251863_REG_CITREC 0x034
193 #define MCP251863_REG_CIBDIAG0 0x038
194 #define MCP251863_REG_CIBDIAG1 0x03C
196 #define MCP251863_REG_CITEFCON 0x040
197 #define MCP251863_REG_CITEFSTA 0x044
198 #define MCP251863_REG_CITEFUA 0x048
199 #define MCP251863_REG_CIFIFOBA 0x04C
201 #define MCP251863_REG_CIFIFOCON 0x050
202 #define MCP251863_REG_CIFIFOSTA 0x054
203 #define MCP251863_REG_CIFIFOUA 0x058
236 #define MCP251863_FIFO_CH0 0
237 #define MCP251863_FIFO_CH1 1
238 #define MCP251863_FIFO_CH2 2
239 #define MCP251863_FIFO_CH3 3
240 #define MCP251863_FIFO_CH4 4
241 #define MCP251863_FIFO_CH5 5
242 #define MCP251863_FIFO_CH6 6
243 #define MCP251863_FIFO_CH7 7
245 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
246 #define MCP251863_FIFO_CH8 8
247 #define MCP251863_FIFO_CH9 9
248 #define MCP251863_FIFO_CH10 10
249 #define MCP251863_FIFO_CH11 11
250 #define MCP251863_FIFO_CH12 12
251 #define MCP251863_FIFO_CH13 13
252 #define MCP251863_FIFO_CH14 14
253 #define MCP251863_FIFO_CH15 15
256 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
257 #define MCP251863_FIFO_CH16 16
258 #define MCP251863_FIFO_CH17 17
259 #define MCP251863_FIFO_CH18 18
260 #define MCP251863_FIFO_CH19 19
261 #define MCP251863_FIFO_CH20 20
262 #define MCP251863_FIFO_CH21 21
263 #define MCP251863_FIFO_CH22 22
264 #define MCP251863_FIFO_CH23 23
265 #define MCP251863_FIFO_CH24 24
266 #define MCP251863_FIFO_CH25 25
267 #define MCP251863_FIFO_CH26 26
268 #define MCP251863_FIFO_CH27 27
269 #define MCP251863_FIFO_CH28 28
270 #define MCP251863_FIFO_CH29 29
271 #define MCP251863_FIFO_CH30 30
272 #define MCP251863_FIFO_CH31 31
276 #define MCP251863_FIFO_TOTAL_CHANNELS 32
278 #ifdef CAN_TXQUEUE_IMPLEMENTED
279 #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1
280 #define CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0
282 #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH0
289 #define MCP251863_FILT0 0
290 #define MCP251863_FILT1 1
291 #define MCP251863_FILT2 2
292 #define MCP251863_FILT3 3
293 #define MCP251863_FILT4 4
294 #define MCP251863_FILT5 5
295 #define MCP251863_FILT6 6
296 #define MCP251863_FILT7 7
298 #ifdef MCP251863_FILT_08TO15_IMPLEMENTED
299 #define MCP251863_FILT8 8
300 #define MCP251863_FILT9 9
301 #define MCP251863_FILT10 10
302 #define MCP251863_FILT11 11
303 #define MCP251863_FILT12 12
304 #define MCP251863_FILT13 13
305 #define MCP251863_FILT14 14
306 #define MCP251863_FILT15 15
309 #ifdef MCP251863_FILT_16TO31_IMPLEMENTED
310 #define MCP251863_FILT16 16
311 #define MCP251863_FILT17 17
312 #define MCP251863_FILT18 18
313 #define MCP251863_FILT19 19
314 #define MCP251863_FILT20 20
315 #define MCP251863_FILT21 21
316 #define MCP251863_FILT22 22
317 #define MCP251863_FILT23 23
318 #define MCP251863_FILT24 24
319 #define MCP251863_FILT25 25
320 #define MCP251863_FILT26 26
321 #define MCP251863_FILT27 27
322 #define MCP251863_FILT28 28
323 #define MCP251863_FILT29 29
324 #define MCP251863_FILT30 30
325 #define MCP251863_FILT31 31
328 #define MCP251863_FILT_TOTAL 32
334 #define MCP251863_NORMAL_MODE 0x00
335 #define MCP251863_SLEEP_MODE 0x01
336 #define MCP251863_INT_LOOP_MODE 0x02
337 #define MCP251863_LISTEN_ONLY_MODE 0x03
338 #define MCP251863_CONFIG_MODE 0x04
339 #define MCP251863_EXT_LOOP_MODE 0x05
340 #define MCP251863_CLASSIC_MODE 0x06
341 #define MCP251863_RESTRICT_MODE 0x07
342 #define MCP251863_INVALID_MODE 0xFF
348 #define MCP251863_TXBWS_NO_DELAY 0
349 #define MCP251863_TXBWS_2 1
350 #define MCP251863_TXBWS_4 2
351 #define MCP251863_TXBWS_8 3
352 #define MCP251863_TXBWS_16 4
353 #define MCP251863_TXBWS_32 5
354 #define MCP251863_TXBWS_64 6
355 #define MCP251863_TXBWS_128 7
356 #define MCP251863_TXBWS_256 8
357 #define MCP251863_TXBWS_512 9
358 #define MCP251863_TXBWS_1024 10
359 #define MCP251863_TXBWS_2048 11
360 #define MCP251863_TXBWS_4096 12
366 #define MCP251863_WFT00 0
367 #define MCP251863_WFT01 1
368 #define MCP251863_WFT10 2
369 #define MCP251863_WFT11 3
375 #define MCP251863_DNET_FILT_DISABLE 0
376 #define MCP251863_DNET_FILT_SIZE_1_BIT 1
377 #define MCP251863_DNET_FILT_SIZE_2_BIT 2
378 #define MCP251863_DNET_FILT_SIZE_3_BIT 3
379 #define MCP251863_DNET_FILT_SIZE_4_BIT 4
380 #define MCP251863_DNET_FILT_SIZE_5_BIT 5
381 #define MCP251863_DNET_FILT_SIZE_6_BIT 6
382 #define MCP251863_DNET_FILT_SIZE_7_BIT 7
383 #define MCP251863_DNET_FILT_SIZE_8_BIT 8
384 #define MCP251863_DNET_FILT_SIZE_9_BIT 9
385 #define MCP251863_DNET_FILT_SIZE_10_BIT 10
386 #define MCP251863_DNET_FILT_SIZE_11_BIT 11
387 #define MCP251863_DNET_FILT_SIZE_12_BIT 12
388 #define MCP251863_DNET_FILT_SIZE_13_BIT 13
389 #define MCP251863_DNET_FILT_SIZE_14_BIT 14
390 #define MCP251863_DNET_FILT_SIZE_15_BIT 15
391 #define MCP251863_DNET_FILT_SIZE_16_BIT 16
392 #define MCP251863_DNET_FILT_SIZE_17_BIT 17
393 #define MCP251863_DNET_FILT_SIZE_18_BIT 18
399 #define MCP251863_PLSIZE_8 0
400 #define MCP251863_PLSIZE_12 1
401 #define MCP251863_PLSIZE_16 2
402 #define MCP251863_PLSIZE_20 3
403 #define MCP251863_PLSIZE_24 4
404 #define MCP251863_PLSIZE_32 5
405 #define MCP251863_PLSIZE_48 6
406 #define MCP251863_PLSIZE_64 7
412 #define MCP251863_DLC_0 0
413 #define MCP251863_DLC_1 1
414 #define MCP251863_DLC_2 2
415 #define MCP251863_DLC_3 3
416 #define MCP251863_DLC_4 4
417 #define MCP251863_DLC_5 5
418 #define MCP251863_DLC_6 6
419 #define MCP251863_DLC_7 7
420 #define MCP251863_DLC_8 8
421 #define MCP251863_DLC_12 9
422 #define MCP251863_DLC_16 10
423 #define MCP251863_DLC_20 11
424 #define MCP251863_DLC_24 12
425 #define MCP251863_DLC_32 13
426 #define MCP251863_DLC_48 14
427 #define MCP251863_DLC_64 15
433 #define MCP251863_RX_FIFO_EMPTY 0
434 #define MCP251863_RX_FIFO_STATUS_MASK 0x0F
435 #define MCP251863_RX_FIFO_NOT_EMPTY 0x01
436 #define MCP251863_RX_FIFO_HALF_FULL 0x02
437 #define MCP251863_RX_FIFO_FULL 0x04
438 #define MCP251863_RX_FIFO_OVERFLOW 0x08
444 #define MCP251863_TX_FIFO_FULL 0
445 #define MCP251863_TX_FIFO_STATUS_MASK 0x1F7
446 #define MCP251863_TX_FIFO_NOT_FULL 0x01
447 #define MCP251863_TX_FIFO_HALF_FULL 0x02
448 #define MCP251863_TX_FIFO_EMPTY 0x04
449 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10
450 #define MCP251863_TX_FIFO_ERROR 0x20
451 #define MCP251863_TX_FIFO_ARBITRATION_LOST 0x40
452 #define MCP251863_TX_FIFO_ABORTED 0x80
453 #define MCP251863_TX_FIFO_TRANSMITTING 0x100
459 #define MCP251863_TEF_FIFO_EMPTY 0
460 #define MCP251863_TEF_FIFO_STATUS_MASK 0x0F
461 #define MCP251863_TEF_FIFO_NOT_EMPTY 0x01
462 #define MCP251863_TEF_FIFO_HALF_FULL 0x02
463 #define MCP251863_TEF_FIFO_FULL 0x04
464 #define MCP251863_TEF_FIFO_OVERFLOW 0x08
470 #define MCP251863_TX_FIFO_NO_EVENT 0
471 #define MCP251863_TX_FIFO_ALL_EVENTS 0x17
472 #define MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01
473 #define MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02
474 #define MCP251863_TX_FIFO_EMPTY_EVENT 0x04
475 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10
477 #define MCP251863_RX_FIFO_NO_EVENT 0
478 #define MCP251863_RX_FIFO_ALL_EVENTS 0x0F
479 #define MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01
480 #define MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02
481 #define MCP251863_RX_FIFO_FULL_EVENT 0x04
482 #define MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08
484 #define MCP251863_TEF_FIFO_NO_EVENT 0
485 #define MCP251863_TEF_FIFO_ALL_EVENTS 0x0F
486 #define MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01
487 #define MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02
488 #define MCP251863_TEF_FIFO_FULL_EVENT 0x04
489 #define MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08
491 #define MCP251863_NO_EVENT 0
492 #define MCP251863_ALL_EVENTS 0xFF1F
493 #define MCP251863_TX_EVENT 0x0001
494 #define MCP251863_RX_EVENT 0x0002
495 #define MCP251863_TIME_BASE_COUNTER_EVENT 0x0004
496 #define MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008
497 #define MCP251863_TEF_EVENT 0x0010
499 #define MCP251863_RAM_ECC_EVENT 0x0100
500 #define MCP251863_SPI_CRC_EVENT 0x0200
501 #define MCP251863_TX_ATTEMPTS_EVENT 0x0400
502 #define MCP251863_RX_OVERFLOW_EVENT 0x0800
503 #define MCP251863_SYSTEM_ERROR_EVENT 0x1000
504 #define MCP251863_BUS_ERROR_EVENT 0x2000
505 #define MCP251863_BUS_WAKEUP_EVENT 0x4000
506 #define MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000
508 #define MCP251863_500K_1M 0
509 #define MCP251863_500K_2M 1
510 #define MCP251863_500K_3M 2
511 #define MCP251863_500K_4M 3
512 #define MCP251863_500K_5M 4
513 #define MCP251863_500K_6M7 5
514 #define MCP251863_500K_8M 6
515 #define MCP251863_500K_10M 7
516 #define MCP251863_250K_500K 8
517 #define MCP251863_250K_833K 9
518 #define MCP251863_250K_1M 10
519 #define MCP251863_250K_1M5 11
520 #define MCP251863_250K_2M 12
521 #define MCP251863_250K_3M 13
522 #define MCP251863_250K_4M 14
523 #define MCP251863_1000K_4M 15
524 #define MCP251863_1000K_8M 16
525 #define MCP251863_125K_500K 17
527 #define MCP251863_NBT_125K 0
528 #define MCP251863_NBT_250K 1
529 #define MCP251863_NBT_500K 2
530 #define MCP251863_NBT_1M 3
532 #define MCP251863_DBT_500K 0
533 #define MCP251863_DBT_833K 1
534 #define MCP251863_DBT_1M 2
535 #define MCP251863_DBT_1M5 3
536 #define MCP251863_DBT_2M 4
537 #define MCP251863_DBT_3M 5
538 #define MCP251863_DBT_4M 6
539 #define MCP251863_DBT_5M 7
540 #define MCP251863_DBT_6M7 8
541 #define MCP251863_DBT_8M 9
542 #define MCP251863_DBT_10M 10
544 #define MCP251863_SSP_MODE_OFF 0
545 #define MCP251863_SSP_MODE_MANUAL 1
546 #define MCP251863_SSP_MODE_AUTO 2
548 #define MCP251863_ERROR_FREE_STATE 0
549 #define MCP251863_ERROR_ALL 0x3F
550 #define MCP251863_TX_RX_WARNING_STATE 0x01
551 #define MCP251863_RX_WARNING_STATE 0x02
552 #define MCP251863_TX_WARNING_STATE 0x04
553 #define MCP251863_RX_BUS_PASSIVE_STATE 0x08
554 #define MCP251863_TX_BUS_PASSIVE_STATE 0x10
555 #define MCP251863_TX_BUS_OFF_STATE 0x20
557 #define MCP251863_TS_SOF 0x00
558 #define MCP251863_TS_EOF 0x01
559 #define MCP251863_TS_RES 0x02
561 #define MCP2518_ECC_NO_EVENT 0x00
562 #define MCP2518_ECC_ALL_EVENTS 0x06
563 #define MCP2518_ECC_SEC_EVENT 0x02
564 #define MCP2518_ECC_DED_EVENT 0x04
566 #define MCP251863_CRC_NO_EVENT 0x00
567 #define MCP251863_CRC_ALL_EVENTS 0x03
568 #define MCP251863_CRC_CRCERR_EVENT 0x01
569 #define MCP251863_CRC_FORMERR_EVENT 0x02
575 #define MCP251863_PIN_0 0
576 #define MCP251863_PIN_1 1
578 #define MCP251863_PINMODE_INT 0
579 #define MCP251863_PINMODE_GPIO 1
581 #define MCP251863_PINOUT 0
582 #define MCP251863_PININ 1
584 #define MCP251863_PINLOW 0
585 #define MCP251863_PINHIGH 1
587 #define MCP251863_PUSHPULL 0
588 #define MCP251863_OPENDRAIN 1
590 #define MCP251863_CLKO_CLOCK 0
591 #define MCP251863_CLKO_SOF 1
597 #define MCP251863_TXREQ_CH0 0x00000001
598 #define MCP251863_TXREQ_CH1 0x00000002
599 #define MCP251863_TXREQ_CH2 0x00000004
600 #define MCP251863_TXREQ_CH3 0x00000008
601 #define MCP251863_TXREQ_CH4 0x00000010
602 #define MCP251863_TXREQ_CH5 0x00000020
603 #define MCP251863_TXREQ_CH6 0x00000040
604 #define MCP251863_TXREQ_CH7 0x00000080
606 #define MCP251863_TXREQ_CH8 0x00000100
607 #define MCP251863_TXREQ_CH9 0x00000200
608 #define MCP251863_TXREQ_CH10 0x00000400
609 #define MCP251863_TXREQ_CH11 0x00000800
610 #define MCP251863_TXREQ_CH12 0x00001000
611 #define MCP251863_TXREQ_CH13 0x00002000
612 #define MCP251863_TXREQ_CH14 0x00004000
613 #define MCP251863_TXREQ_CH15 0x00008000
615 #define MCP251863_TXREQ_CH16 0x00010000
616 #define MCP251863_TXREQ_CH17 0x00020000
617 #define MCP251863_TXREQ_CH18 0x00040000
618 #define MCP251863_TXREQ_CH19 0x00080000
619 #define MCP251863_TXREQ_CH20 0x00100000
620 #define MCP251863_TXREQ_CH21 0x00200000
621 #define MCP251863_TXREQ_CH22 0x00400000
622 #define MCP251863_TXREQ_CH23 0x00800000
624 #define MCP251863_TXREQ_CH24 0x01000000
625 #define MCP251863_TXREQ_CH25 0x02000000
626 #define MCP251863_TXREQ_CH26 0x04000000
627 #define MCP251863_TXREQ_CH27 0x08000000
628 #define MCP251863_TXREQ_CH28 0x10000000
629 #define MCP251863_TXREQ_CH29 0x20000000
630 #define MCP251863_TXREQ_CH30 0x40000000
631 #define MCP251863_TXREQ_CH31 0x80000000
637 #define MCP251863_ICODE_FIFO_CH0 0
638 #define MCP251863_ICODE_FIFO_CH1 1
639 #define MCP251863_ICODE_FIFO_CH2 2
640 #define MCP251863_ICODE_FIFO_CH3 3
641 #define MCP251863_ICODE_FIFO_CH4 4
642 #define MCP251863_ICODE_FIFO_CH5 5
643 #define MCP251863_ICODE_FIFO_CH6 6
644 #define MCP251863_ICODE_FIFO_CH7 7
646 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
647 #define MCP251863_ICODE_FIFO_CH8 8
648 #define MCP251863_ICODE_FIFO_CH9 9
649 #define MCP251863_ICODE_FIFO_CH10 10
650 #define MCP251863_ICODE_FIFO_CH11 11
651 #define MCP251863_ICODE_FIFO_CH12 12
652 #define MCP251863_ICODE_FIFO_CH13 13
653 #define MCP251863_ICODE_FIFO_CH14 14
654 #define MCP251863_ICODE_FIFO_CH15 15
657 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
658 #define MCP251863_ICODE_FIFO_CH16 16
659 #define MCP251863_ICODE_FIFO_CH17 17
660 #define MCP251863_ICODE_FIFO_CH18 18
661 #define MCP251863_ICODE_FIFO_CH19 19
662 #define MCP251863_ICODE_FIFO_CH20 20
663 #define MCP251863_ICODE_FIFO_CH21 21
664 #define MCP251863_ICODE_FIFO_CH22 22
665 #define MCP251863_ICODE_FIFO_CH23 23
666 #define MCP251863_ICODE_FIFO_CH24 24
667 #define MCP251863_ICODE_FIFO_CH25 25
668 #define MCP251863_ICODE_FIFO_CH26 26
669 #define MCP251863_ICODE_FIFO_CH27 27
670 #define MCP251863_ICODE_FIFO_CH28 28
671 #define MCP251863_ICODE_FIFO_CH29 29
672 #define MCP251863_ICODE_FIFO_CH30 30
673 #define MCP251863_ICODE_FIFO_CH31 31
676 #define MCP251863_ICODE_TOTAL_CHANNELS 32
677 #define MCP251863_ICODE_NO_INT 64
678 #define MCP251863_ICODE_CERRIF 65
679 #define MCP251863_ICODE_WAKIF 66
680 #define MCP251863_ICODE_RXOVIF 67
681 #define MCP251863_ICODE_ADDRERR_SERRIF 68
682 #define MCP251863_ICODE_MABOV_SERRIF 69
683 #define MCP251863_ICODE_TBCIF 70
684 #define MCP251863_ICODE_MODIF 71
685 #define MCP251863_ICODE_IVMIF 72
686 #define MCP251863_ICODE_TEFIF 73
687 #define MCP251863_ICODE_TXATIF 74
688 #define MCP251863_ICODE_RESERVED 75
694 #define MCP251863_RXCODE_FIFO_CH0 0
695 #define MCP251863_RXCODE_FIFO_CH1 1
696 #define MCP251863_RXCODE_FIFO_CH2 2
697 #define MCP251863_RXCODE_FIFO_CH3 3
698 #define MCP251863_RXCODE_FIFO_CH4 4
699 #define MCP251863_RXCODE_FIFO_CH5 5
700 #define MCP251863_RXCODE_FIFO_CH6 6
701 #define MCP251863_RXCODE_FIFO_CH7 7
703 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
704 #define MCP251863_RXCODE_FIFO_CH8 8
705 #define MCP251863_RXCODE_FIFO_CH9 9
706 #define MCP251863_RXCODE_FIFO_CH10 10
707 #define MCP251863_RXCODE_FIFO_CH11 11
708 #define MCP251863_RXCODE_FIFO_CH12 12
709 #define MCP251863_RXCODE_FIFO_CH13 13
710 #define MCP251863_RXCODE_FIFO_CH14 14
711 #define MCP251863_RXCODE_FIFO_CH15 15
714 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
715 #define MCP251863_RXCODE_FIFO_CH16 16
716 #define MCP251863_RXCODE_FIFO_CH17 17
717 #define MCP251863_RXCODE_FIFO_CH18 18
718 #define MCP251863_RXCODE_FIFO_CH19 19
719 #define MCP251863_RXCODE_FIFO_CH20 20
720 #define MCP251863_RXCODE_FIFO_CH21 21
721 #define MCP251863_RXCODE_FIFO_CH22 22
722 #define MCP251863_RXCODE_FIFO_CH23 23
723 #define MCP251863_RXCODE_FIFO_CH24 24
724 #define MCP251863_RXCODE_FIFO_CH25 25
725 #define MCP251863_RXCODE_FIFO_CH26 26
726 #define MCP251863_RXCODE_FIFO_CH27 27
727 #define MCP251863_RXCODE_FIFO_CH28 28
728 #define MCP251863_RXCODE_FIFO_CH29 29
729 #define MCP251863_RXCODE_FIFO_CH30 30
730 #define MCP251863_RXCODE_FIFO_CH31 31
733 #define MCP251863_RXCODE_TOTAL_CHANNELS 32
734 #define MCP251863_RXCODE_NO_INT 64
735 #define MCP251863_RXCODE_RESERVED 65
741 #define MCP251863_TXCODE_FIFO_CH0 0
742 #define MCP251863_TXCODE_FIFO_CH1 1
743 #define MCP251863_TXCODE_FIFO_CH2 2
744 #define MCP251863_TXCODE_FIFO_CH3 3
745 #define MCP251863_TXCODE_FIFO_CH4 4
746 #define MCP251863_TXCODE_FIFO_CH5 5
747 #define MCP251863_TXCODE_FIFO_CH6 6
748 #define MCP251863_TXCODE_FIFO_CH7 7
750 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
751 #define MCP251863_TXCODE_FIFO_CH8 8
752 #define MCP251863_TXCODE_FIFO_CH9 9
753 #define MCP251863_TXCODE_FIFO_CH10 10
754 #define MCP251863_TXCODE_FIFO_CH11 11
755 #define MCP251863_TXCODE_FIFO_CH12 12
756 #define MCP251863_TXCODE_FIFO_CH13 13
757 #define MCP251863_TXCODE_FIFO_CH14 14
758 #define MCP251863_TXCODE_FIFO_CH15 15
761 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
762 #define MCP251863_TXCODE_FIFO_CH16 16
763 #define MCP251863_TXCODE_FIFO_CH17 17
764 #define MCP251863_TXCODE_FIFO_CH18 18
765 #define MCP251863_TXCODE_FIFO_CH19 19
766 #define MCP251863_TXCODE_FIFO_CH20 20
767 #define MCP251863_TXCODE_FIFO_CH21 21
768 #define MCP251863_TXCODE_FIFO_CH22 22
769 #define MCP251863_TXCODE_FIFO_CH23 23
770 #define MCP251863_TXCODE_FIFO_CH24 24
771 #define MCP251863_TXCODE_FIFO_CH25 25
772 #define MCP251863_TXCODE_FIFO_CH26 26
773 #define MCP251863_TXCODE_FIFO_CH27 27
774 #define MCP251863_TXCODE_FIFO_CH28 28
775 #define MCP251863_TXCODE_FIFO_CH29 29
776 #define MCP251863_TXCODE_FIFO_CH30 30
777 #define MCP251863_TXCODE_FIFO_CH31 31
780 #define MCP251863_TXCODE_TOTAL_CHANNELS 32
781 #define MCP251863_TXCODE_NO_INT 64
782 #define MCP251863_TXCODE_RESERVED 65
788 #define MCP251863_SYSCLK_40M 0
789 #define MCP251863_SYSCLK_20M 1
790 #define MCP251863_SYSCLK_10M 2
796 #define MCP251863_CLKO_DIV1 0
797 #define MCP251863_CLKO_DIV2 1
798 #define MCP251863_CLKO_DIV4 2
799 #define MCP251863_CLKO_DIV10 3
801 #define N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )
802 #define N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )
803 #define N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )
813 #define MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
814 #define MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
832 #define MCP251863_MAP_MIKROBUS( cfg, mikrobus ) \
833 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
834 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
835 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
836 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
837 cfg.stby = MIKROBUS( mikrobus, MIKROBUS_AN ); \
838 cfg.clk = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
839 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
1168 uint32_t unimplemented1 : 1;
1170 uint32_t unimplemented2 : 1;
1172 uint32_t tx_enable : 1;
1175 uint32_t freset : 1;
1176 uint32_t unimplemented3 : 5;
1179 uint32_t unimplemented4 : 1;
1180 uint32_t fifo_size : 5;
1181 uint32_t pay_load_size : 3;
1652 uint32_t unimplemented1 : 1;
1657 uint32_t fifo_index : 5;
1658 uint32_t unimplemented2 : 19;
3730 #endif // MCP251863_H
uint32_t spi_speed
Definition: mcp251863.h:1898
uint32_t unimplemented1
Definition: mcp251863.h:1390
uint32_t freset
Definition: mcp251863.h:1102
MCP251863 Click Transmit Event FIFO Control Register.
Definition: mcp251863.h:1120
uint32_t meid
Definition: mcp251863.h:1029
err_t mcp251863_read_word(mcp251863_t *ctx, uint16_t address, uint32_t *data_out)
SPI Read Word.
uint32_t rx_over_flow_if
Definition: mcp251863.h:1642
err_t mcp251863_write_half_word(mcp251863_t *ctx, uint16_t address, uint16_t data_in)
SPI Write Half Word.
uint8_t n_rec
Definition: mcp251863.h:1747
err_t mcp251863_transmit_channel_event_attempt_clear(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Event Clear.
err_t mcp251863_transmit_request_get(mcp251863_t *ctx, uint32_t *tx_req)
Get TXREQ register.
MCP251863 Click Interrupt Vector Register.
Definition: mcp251863.h:1502
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1072
mcp251863_rx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:972
uint32_t tx_not_full_if
Definition: mcp251863.h:1649
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:973
uint32_t unimplemented3
Definition: mcp251863.h:1216
uint32_t unimplemented4
Definition: mcp251863.h:1132
uint32_t unimplemented3
Definition: mcp251863.h:1258
uint32_t fdf
Definition: mcp251863.h:923
uint32_t tx_attempts
Definition: mcp251863.h:1105
pin_name_t sck
Definition: mcp251863.h:1889
err_t mcp251863_bit_time_configure_data_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 10MHz system clock.
uint32_t error_address
Definition: mcp251863.h:1696
uint32_t d_form_error
Definition: mcp251863.h:1806
uint32_t ivmie
Definition: mcp251863.h:1481
uint32_t swj
Definition: mcp251863.h:1389
MCP251863 Click FIFO Control Register.
Definition: mcp251863.h:1146
uint32_t unimplemented2
Definition: mcp251863.h:1472
MCP251863 Click configuration object.
Definition: mcp251863.h:1885
uint32_t wake_up_filter_time
Definition: mcp251863.h:1067
err_t mcp251863_ecc_event_enable(mcp251863_t *ctx, uint8_t flags)
ECC Event Enable.
uint32_t dedie
Definition: mcp251863.h:1285
uint32_t unimplemented1
Definition: mcp251863.h:1409
uint32_t n_ack_error
Definition: mcp251863.h:1797
uint32_t n_stuff_err
Definition: mcp251863.h:1726
err_t mcp251863_ecc_enable(mcp251863_t *ctx)
Enable ECC.
uint32_t unimplemented2
Definition: mcp251863.h:1128
uint32_t unimplemented2
Definition: mcp251863.h:1288
uint32_t brp
Definition: mcp251863.h:1414
MCP251863 Click CAN Receive Channel Configure.
Definition: mcp251863.h:1348
err_t mcp251863_gpio_transmit_pin_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain TXCAN.
err_t mcp251863_receive_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Receive FIFO Index Get.
err_t mcp251863_oscillator_status_get(mcp251863_t *ctx, mcp251863_osc_sta_t *status)
Get Oscillator Status.
err_t mcp251863_bit_time_configure_data_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 40MHz system clock.
err_t mcp251863_receive_channel_update(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Update.
err_t mcp251863_transmit_channel_abort(mcp251863_t *ctx, uint8_t channel)
Abort transmission of single FIFO.
uint32_t tx_enable
Definition: mcp251863.h:1155
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:937
uint32_t tefhfie
Definition: mcp251863.h:1123
err_t mcp251863_transmit_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Transmit FIFO Event Get.
uint32_t d_crc_err
Definition: mcp251863.h:1735
err_t mcp251863_device_net_filter_count_set(mcp251863_t *ctx, uint8_t dnfc)
Set Device Net Filter Count.
uint32_t tx_error_state_warning
Definition: mcp251863.h:1580
uint32_t RXOVIF
Definition: mcp251863.h:1534
MCP251863 Click Transmit/Receive Error Count Register.
Definition: mcp251863.h:1574
uint32_t wake_up_filter_enable
Definition: mcp251863.h:853
err_t mcp251863_oscillator_enable(mcp251863_t *ctx)
Enable oscillator to wake-up from sleep.
uint32_t esi
Definition: mcp251863.h:1809
err_t mcp251863_transmit_channel_flush(mcp251863_t *ctx, uint8_t channel)
TX Channel Flush.
MCP251863 Click Mask Object Register.
Definition: mcp251863.h:1041
uint32_t swj
Definition: mcp251863.h:1408
void mcp251863_oscillator_control_object_reset(mcp251863_div_ctl_t *ctrl)
Reset Oscillator Control.
MCP251863 Click Oscillator Control.
Definition: mcp251863.h:1234
uint32_t tx_error_state_passive
Definition: mcp251863.h:1582
uint32_t seq
Definition: mcp251863.h:925
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1309
mcp251863_bus_error_count_t error_count
Definition: mcp251863.h:1761
uint32_t tx_empty_ie
Definition: mcp251863.h:1167
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1073
uint32_t unimplemented2
Definition: mcp251863.h:1695
uint32_t sclk_ready
Definition: mcp251863.h:1712
uint16_t mcp251863_calculate_crc16(uint8_t *data_pointer, uint16_t size)
Calculate CRC16.
err_t mcp251863_module_event_icode_get(mcp251863_t *ctx, uint8_t *icode)
Get ICODE.
uint32_t rx_half_full_ie
Definition: mcp251863.h:1149
MCP251863 Click CAN Transmit Channel Configure.
Definition: mcp251863.h:1321
uint32_t unimplemented2
Definition: mcp251863.h:1678
uint32_t clk_out_divide
Definition: mcp251863.h:1238
uint32_t sof_output_enable
Definition: mcp251863.h:1267
uint32_t fdf
Definition: mcp251863.h:956
MCP251863 Click Time Stamp Configuration Register.
Definition: mcp251863.h:1448
uint32_t unimplemented1
Definition: mcp251863.h:1196
err_t mcp251863_ecc_error_address_get(mcp251863_t *ctx, uint16_t *address)
Get ECC Error Address.
uint32_t tseg2
Definition: mcp251863.h:1391
uint32_t fifo_index
Definition: mcp251863.h:1624
uint32_t unimplemented2
Definition: mcp251863.h:960
uint32_t pll_enable
Definition: mcp251863.h:1210
uint32_t unimplemented1
Definition: mcp251863.h:1505
uint8_t mcp251863_operation_mode_get(mcp251863_t *ctx)
Get Operation Mode.
uint32_t ecc_en
Definition: mcp251863.h:1283
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1071
err_t mcp251863_module_event_tx_code_get(mcp251863_t *ctx, uint8_t *tx_code)
Get TX Code.
uint32_t n_bit0_err
Definition: mcp251863.h:1722
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1066
uint32_t word
Definition: mcp251863.h:1564
uint8_t tx_flags
Definition: mcp251863.h:1838
uint32_t unimplemented1
Definition: mcp251863.h:1364
MCP251863 Click Data Bit Time Configuration Register.
Definition: mcp251863.h:1406
uint8_t rx_pay_load_size
Definition: mcp251863.h:877
uint32_t osc_disable
Definition: mcp251863.h:1236
uint16_t address
Definition: mcp251863.h:1823
err_t mcp251863_tef_status_get(mcp251863_t *ctx, uint8_t *status)
Transmit Event FIFO Status Get.
uint32_t freset
Definition: mcp251863.h:1131
err_t mcp251863_transmit_request_set(mcp251863_t *ctx, uint32_t tx_req)
Request transmissions using TXREQ register.
digital_out_t stby
Definition: mcp251863.h:1864
MCP251863 Click FIFO User Address Register.
Definition: mcp251863.h:1361
err_t mcp251863_time_stamp_enable(mcp251863_t *ctx)
Time Stamp Enable.
err_t mcp251863_transmit_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Enable.
MCP251863 Click CAN Mask Object ID.
Definition: mcp251863.h:1027
MCP251863 Click I/O Control Register.
Definition: mcp251863.h:1247
This file contains SPI specific macros, functions, etc.
uint32_t word
Definition: mcp251863.h:1136
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:857
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:988
err_t mcp251863_read_half_word(mcp251863_t *ctx, uint16_t address, uint16_t *data_out)
SPI Read Half Word.
err_t mcp251863_bit_time_configure_nominal_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 10MHz system clock.
err_t mcp251863_ecc_event_disable(mcp251863_t *ctx, uint8_t flags)
ECC Event Disable.
uint32_t filter_hit
Definition: mcp251863.h:959
MCP251863 Click Transmit Queue Control Register.
Definition: mcp251863.h:1091
uint32_t word
Definition: mcp251863.h:1290
uint8_t rec
Definition: mcp251863.h:1842
uint32_t CERRIF
Definition: mcp251863.h:1536
uint32_t txbo_err
Definition: mcp251863.h:1729
uint32_t lat0
Definition: mcp251863.h:1256
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1079
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:989
uint32_t fifo_size
Definition: mcp251863.h:1160
uint32_t word
Definition: mcp251863.h:1224
@ MCP251863_OK
Definition: mcp251863.h:1910
uint32_t uinc
Definition: mcp251863.h:1100
err_t mcp251863_transmit_band_width_sharing_set(mcp251863_t *ctx, uint8_t tx_bws)
Set Transmit Bandwidth Sharing Delay.
uint32_t rxie
Definition: mcp251863.h:1468
uint32_t tx_empty_ie
Definition: mcp251863.h:1095
err_t mcp251863_write_byte_safe(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI SFR Write Byte Safe.
MCP251863 Click Interrupt Configuration.
Definition: mcp251863.h:1490
uint32_t brs
Definition: mcp251863.h:955
uint32_t word
Definition: mcp251863.h:1782
uint32_t unimplemented1
Definition: mcp251863.h:1451
err_t mcp251863_transmit_channel_update(mcp251863_t *ctx, uint8_t channel, bool flush)
Transmit FIFO Update.
uint32_t esi
Definition: mcp251863.h:957
uint8_t ide
Definition: mcp251863.h:882
err_t mcp251863_filter_object_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_filt_obj_id_t *id)
Filter Object Configuration.
MCP251863 Click Transmit Event FIFO Status Register.
Definition: mcp251863.h:1596
uint32_t rx_error_count
Definition: mcp251863.h:1576
uint32_t TBCIF
Definition: mcp251863.h:1526
spi_master_t spi
Definition: mcp251863.h:1871
MCP251863 Click ECC Status Register.
Definition: mcp251863.h:1690
err_t mcp251863_time_stamp_disable(mcp251863_t *ctx)
Time Stamp Disable.
uint32_t tx_attempt_ie
Definition: mcp251863.h:1169
err_t mcp251863_error_count_transmit_get(mcp251863_t *ctx, uint8_t *tec)
Transmit Error Count Get.
uint32_t tseg2
Definition: mcp251863.h:1410
MCP251863 Click Oscillator Control Register.
Definition: mcp251863.h:1208
uint32_t unimplemented1
Definition: mcp251863.h:1675
MCP251863 Click Filter Control Register.
Definition: mcp251863.h:1193
uint32_t osc_disable
Definition: mcp251863.h:1212
err_t mcp251863_write_word(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI Write Word.
uint32_t tx_not_full_ie
Definition: mcp251863.h:1093
uint32_t sclk_divide
Definition: mcp251863.h:1214
uint32_t unimplemented2
Definition: mcp251863.h:1213
uint32_t tx_attempts
Definition: mcp251863.h:1337
uint32_t tefneie
Definition: mcp251863.h:1122
uint32_t unimplemented1
Definition: mcp251863.h:926
uint32_t n_form_error
Definition: mcp251863.h:1798
uint32_t esi
Definition: mcp251863.h:1736
uint32_t rx_error_state_warning
Definition: mcp251863.h:1579
mcp251863_rx_fifo_cfg_t rx_config
Definition: mcp251863.h:1848
uint32_t word
Definition: mcp251863.h:1110
uint32_t unimplemented3
Definition: mcp251863.h:1413
err_t mcp251863_time_stamp_set(mcp251863_t *ctx, uint32_t ts)
Time Stamp Set.
uint32_t word
Definition: mcp251863.h:1680
uint32_t word
Definition: mcp251863.h:1456
uint32_t d_bit1_error
Definition: mcp251863.h:1804
uint32_t mcp251863_msg_time_stamp_t
MCP251863 Click CAN Message Time Stamp.
Definition: mcp251863.h:898
err_t mcp251863_transmit_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Transmit FIFO Index Get.
mcp251863_mask_obj_t m_obj
Definition: mcp251863.h:1852
err_t mcp251863_transmit_event_get(mcp251863_t *ctx, uint32_t *txif)
Get pending interrupts of all transmit FIFOs.
uint32_t d_net_filter_count
Definition: mcp251863.h:1062
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1307
uint32_t unimplemented1
Definition: mcp251863.h:1429
uint8_t mcp251863_data_bytes_to_dlc(uint8_t num)
Data bytes to DLC conversion.
void mcp251863_configure_object_reset(mcp251863_can_cfg_t *config)
Reset Configure object to reset values.
mcp251863_bus_diag_t bus_diagnostics
Definition: mcp251863.h:1853
err_t mcp251863_generic_write(mcp251863_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
MCP251863 data writing function.
Definition: mcp251863.h:1049
uint32_t pll_ready
Definition: mcp251863.h:1217
uint32_t unimplemented2
Definition: mcp251863.h:1645
err_t mcp251863_write_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_in, uint16_t n_bytes)
SPI Write Byte Array.
err_t mcp251863_bit_time_configure_data_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.
uint32_t sid
Definition: mcp251863.h:1002
uint32_t tx_not_full_ie
Definition: mcp251863.h:1165
uint32_t unimplemented4
Definition: mcp251863.h:1218
uint32_t clear_auto_sleep_on_match
Definition: mcp251863.h:1252
mcp251863_func_data_t func_data
Definition: mcp251863.h:1876
uint32_t n_ack_err
Definition: mcp251863.h:1724
uint32_t n_crc_error
Definition: mcp251863.h:1800
uint32_t tx_attempts
Definition: mcp251863.h:1178
uint32_t iso_crc_enable
Definition: mcp251863.h:1063
uint32_t n_tx_error_count
Definition: mcp251863.h:1778
MCP251863 Click Interrupt Flag Register.
Definition: mcp251863.h:1547
uint8_t * rxd
Definition: mcp251863.h:1824
uint32_t esi
Definition: mcp251863.h:924
uint32_t n_form_err
Definition: mcp251863.h:1725
uint32_t tx_priority
Definition: mcp251863.h:1177
uint32_t IVMIF
Definition: mcp251863.h:1538
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:939
uint32_t dlc_mismatch
Definition: mcp251863.h:1737
uint32_t time_stamp_enable
Definition: mcp251863.h:1377
mcp251863_mask_obj_id_t bf
Definition: mcp251863.h:1042
uint32_t sid11
Definition: mcp251863.h:908
uint32_t msid
Definition: mcp251863.h:1028
uint32_t unimplemented1
Definition: mcp251863.h:1728
uint32_t msid11
Definition: mcp251863.h:1030
uint32_t pay_load_size
Definition: mcp251863.h:1108
@ MCP251863_ERROR
Definition: mcp251863.h:1911
uint32_t request_op_mode
Definition: mcp251863.h:1077
uint32_t tseg1
Definition: mcp251863.h:1412
err_t mcp251863_transmit_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Disable.
uint32_t pay_load_size
Definition: mcp251863.h:1161
uint32_t uinc
Definition: mcp251863.h:1156
uint32_t pay_load_size
Definition: mcp251863.h:1339
uint32_t unimplemented3
Definition: mcp251863.h:1509
uint32_t d_bit1_err
Definition: mcp251863.h:1731
uint32_t unimplemented2
Definition: mcp251863.h:1431
uint32_t txie
Definition: mcp251863.h:1467
uint32_t lat1
Definition: mcp251863.h:1257
uint32_t osc_ready
Definition: mcp251863.h:1219
uint16_t word
Definition: mcp251863.h:1549
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1069
uint32_t buffer_pointer
Definition: mcp251863.h:1195
uint32_t d_bit0_err
Definition: mcp251863.h:1730
err_t mcp251863_receive_channel_reset(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Reset.
uint32_t fifo_size
Definition: mcp251863.h:1325
err_t mcp251863_configure(mcp251863_t *ctx, mcp251863_can_cfg_t *config)
CAN Control register configuration.
uint32_t tbcie
Definition: mcp251863.h:1469
err_t mcp251863_reset(mcp251863_t *ctx)
Reset function.
uint32_t SPICRCIF
Definition: mcp251863.h:1532
uint32_t pll_enable
Definition: mcp251863.h:1235
uint32_t exide
Definition: mcp251863.h:1005
err_t mcp251863_tef_event_overflow_clear(mcp251863_t *ctx)
Transmit Event FIFO Event Clear.
uint32_t word
Definition: mcp251863.h:1699
err_t mcp251863_read_byte_array_with_crc(mcp251863_t *ctx, bool from_ram, bool *crc_is_correct)
SPI Read Byte Array with CRC.
err_t mcp251863_bus_diagnostics_get(mcp251863_t *ctx, mcp251863_bus_diag_t *bus_diag)
Get Bus Diagnostic Registers: all data_ at once, since we want to keep them in synch.
pin_name_t cs
Definition: mcp251863.h:1890
uint32_t unimplemented2
Definition: mcp251863.h:1454
uint32_t word
Definition: mcp251863.h:1366
uint32_t tseg1
Definition: mcp251863.h:1393
uint8_t iso_crc_enable
Definition: mcp251863.h:871
uint32_t unimplemented2
Definition: mcp251863.h:1255
uint32_t tef_not_empty_if
Definition: mcp251863.h:1598
uint32_t unimplemented4
Definition: mcp251863.h:1511
uint32_t unimplemented2
Definition: mcp251863.h:1810
uint32_t unimplemented3
Definition: mcp251863.h:1130
err_t mcp251863_transmit_message(mcp251863_t *ctx, uint8_t *data_in, uint16_t data_len)
Message Transmit function.
uint32_t rtr_enable
Definition: mcp251863.h:1322
err_t mcp251863_tef_configure(mcp251863_t *ctx, mcp251863_tef_cfg_t *config)
Configure Transmit Event FIFO.
uint32_t spicrcie
Definition: mcp251863.h:1475
uint32_t unimplemented1
Definition: mcp251863.h:1152
uint32_t enable
Definition: mcp251863.h:1197
uint32_t unimplemented1
Definition: mcp251863.h:1006
MCP251863 Click CAN TEF Message Object.
Definition: mcp251863.h:985
err_t mcp251863_filter_mask_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_mask_obj_id_t *mask)
Filter Mask Configuration.
uint32_t tdc_offset
Definition: mcp251863.h:1430
uint32_t eccie
Definition: mcp251863.h:1474
uint32_t unimplemented2
Definition: mcp251863.h:1096
uint8_t remote_frame_req
Definition: mcp251863.h:883
uint32_t osc_ready
Definition: mcp251863.h:1711
uint32_t txbo_error
Definition: mcp251863.h:1802
uint32_t sclk_divide
Definition: mcp251863.h:1237
uint32_t tx_attempt_if
Definition: mcp251863.h:1653
uint32_t clk_out_divide
Definition: mcp251863.h:1215
uint32_t word
Definition: mcp251863.h:1051
err_t mcp251863_gpio_mode_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Mode.
uint32_t unimplemented4
Definition: mcp251863.h:1159
uint32_t pin_mode1
Definition: mcp251863.h:1264
digital_in_t int_pin
Definition: mcp251863.h:1868
uint32_t eid
Definition: mcp251863.h:907
err_t mcp251863_gpio_pin_read(mcp251863_t *ctx, uint8_t pos, uint8_t *state)
Input Pin Read.
uint32_t wake_up_filter_time
Definition: mcp251863.h:854
uint32_t eid
Definition: mcp251863.h:1003
MCP251863 Click Transmit Queue Status Register.
Definition: mcp251863.h:1614
void mcp251863_transmit_queue_configure_object_reset(mcp251863_tx_que_cfg_t *config)
Reset Transmit Queue Configure object to reset values.
MCP251863 Click CAN Message Object ID.
Definition: mcp251863.h:905
uint32_t sid11_enable
Definition: mcp251863.h:1434
uint32_t gpio0
Definition: mcp251863.h:1260
uint32_t mcp251863_dlc_to_data_bytes(uint8_t dlc)
DLC to number of actual data_bytes conversion.
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1308
uint32_t unimplemented1
Definition: mcp251863.h:1643
uint32_t unimplemented1
Definition: mcp251863.h:909
uint32_t fifo_size
Definition: mcp251863.h:1350
MCP251863 Click CAN Configure.
Definition: mcp251863.h:849
err_t mcp251863_receive_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Enable.
uint32_t system_error_to_listen_only
Definition: mcp251863.h:858
err_t mcp251863_receive_message_get(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_msg_obj_t *rx_obj)
Get Received Message.
uint32_t unimplemented4
Definition: mcp251863.h:1262
uint32_t fifo_size
Definition: mcp251863.h:1107
err_t mcp251863_tef_reset(mcp251863_t *ctx)
Transmit Event FIFO Reset.
err_t mcp251863_transmit_abort_all(mcp251863_t *ctx)
Abort All transmissions.
uint32_t icode
Definition: mcp251863.h:1504
err_t mcp251863_time_stamp_get(mcp251863_t *ctx, uint32_t *time_stamp)
Time Stamp Get.
mcp251863_can_cfg_t config
Definition: mcp251863.h:1846
uint32_t word
Definition: mcp251863.h:1017
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1304
MCP251863 Click Interrupt Flags.
Definition: mcp251863.h:1523
uint32_t d_form_err
Definition: mcp251863.h:1733
MCP251863 Click Interrupt Enables.
Definition: mcp251863.h:1466
MCP251863 Click CAN TX Message Object Control.
Definition: mcp251863.h:918
uint32_t word
Definition: mcp251863.h:1586
err_t mcp251863_read_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_out, uint16_t n_words)
SPI Read Word Array.
MCP251863 Click Oscillator Status.
Definition: mcp251863.h:1709
mcp251863_rx_msg_obj_t rx_obj
Definition: mcp251863.h:1850
uint32_t txq_enable
Definition: mcp251863.h:1311
MCP251863 Click CAN Transmit Queue Configure.
Definition: mcp251863.h:1335
uint32_t tefie
Definition: mcp251863.h:1471
mcp251863_tx_msg_obj_t tx_obj
Definition: mcp251863.h:1849
void mcp251863_receive_channel_configure_object_reset(mcp251863_rx_fifo_cfg_t *config)
Reset Receive Channel Configure object to reset value.
uint32_t unimplemented3
Definition: mcp251863.h:1098
uint32_t brs
Definition: mcp251863.h:922
err_t mcp251863_transmit_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint16_t *status)
Transmit Channel Status Get.
uint32_t RXIF
Definition: mcp251863.h:1525
err_t mcp251863_fifo_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *data_out)
FIFO Index Get.
pin_name_t stby
Definition: mcp251863.h:1893
uint32_t filter_hit
Definition: mcp251863.h:1506
MCP251863 Click CAN Message Configuration.
Definition: mcp251863.h:870
uint32_t ide
Definition: mcp251863.h:920
void mcp251863_transmit_channel_configure_object_reset(mcp251863_tx_fifo_cfg_t *config)
Reset Transmit Channel Configure object to reset values.
uint32_t txd_num_bytes
Definition: mcp251863.h:1827
err_t mcp251863_gpio_direction_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Direction.
uint32_t fifo_size
Definition: mcp251863.h:1133
void mcp251863_cfg_setup(mcp251863_cfg_t *cfg)
MCP251863 configuration object setup function.
err_t mcp251863_filter_enable(mcp251863_t *ctx, uint8_t filter)
Filter Enable.
err_t mcp251863_ecc_parity_set(mcp251863_t *ctx, uint8_t parity)
Set ECC Parity.
uint32_t iso_crc_enable
Definition: mcp251863.h:851
uint32_t mide
Definition: mcp251863.h:1031
uint32_t tx_error_count
Definition: mcp251863.h:1577
uint32_t rxovie
Definition: mcp251863.h:1477
uint32_t unimplemented1
Definition: mcp251863.h:1617
err_t mcp251863_default_cfg(mcp251863_t *ctx)
MCP251863 default configuration function.
MCP251863 Click Transmitter Delay Compensation Register.
Definition: mcp251863.h:1426
MCP251863 Click CAN Filter Object ID.
Definition: mcp251863.h:1001
uint32_t unimplemented3
Definition: mcp251863.h:1625
uint32_t wakie
Definition: mcp251863.h:1480
uint8_t store_in_tef
Definition: mcp251863.h:872
uint32_t ECCIF
Definition: mcp251863.h:1531
uint32_t tef_ov_if
Definition: mcp251863.h:1601
uint32_t txq_enable
Definition: mcp251863.h:860
uint32_t unimplemented2
Definition: mcp251863.h:1411
uint32_t unimplemented1
Definition: mcp251863.h:1602
uint32_t d_crc_error
Definition: mcp251863.h:1808
uint32_t unimplemented3
Definition: mcp251863.h:1697
uint32_t unimplemented3
Definition: mcp251863.h:1157
err_t mcp251863_receive_message(mcp251863_t *ctx, uint8_t *data_out, uint16_t *data_len)
Message Receive function.
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1561
uint32_t tx_half_full_if
Definition: mcp251863.h:1650
uint8_t rx_fifo_size
Definition: mcp251863.h:876
uint32_t unimplemented2
Definition: mcp251863.h:1068
MCP251863 Click Nominal Bit Time Configuration Register.
Definition: mcp251863.h:1387
uint32_t rx_full_ie
Definition: mcp251863.h:1150
MCP251863 Click CAN Configure.
Definition: mcp251863.h:1300
uint8_t n_tec
Definition: mcp251863.h:1748
mcp251863_return_value_t
MCP251863 Click return value data.
Definition: mcp251863.h:1909
uint32_t word
Definition: mcp251863.h:1627
uint32_t hvdetsel
Definition: mcp251863.h:1259
uint32_t extended_id
Definition: mcp251863.h:879
uint32_t tx_attempt_if
Definition: mcp251863.h:1620
uint32_t n_bit1_err
Definition: mcp251863.h:1723
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:987
err_t mcp251863_transmit_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_fifo_cfg_t *config)
Configure Transmit FIFO.
uint32_t unimplemented4
Definition: mcp251863.h:1103
uint32_t unimplemented2
Definition: mcp251863.h:1392
MCP251863 Click Interrupt Register.
Definition: mcp251863.h:1559
uint32_t int_pin_open_drain
Definition: mcp251863.h:1268
err_t mcp251863_ram_init(mcp251863_t *ctx, uint8_t rx_data)
Initialize RAM.
uint32_t secif
Definition: mcp251863.h:1693
uint32_t tx_error_state_bus_off
Definition: mcp251863.h:1583
uint32_t tbc_prescaler
Definition: mcp251863.h:1450
uint32_t tx_code
Definition: mcp251863.h:1508
uint8_t mcp251863_id_t
MCP251863 Click Module ID.
Definition: mcp251863.h:892
uint32_t unimplemented1
Definition: mcp251863.h:1692
uint32_t rx_not_empty_if
Definition: mcp251863.h:1639
uint32_t rx_code
Definition: mcp251863.h:1510
err_t mcp251863_crc_event_get(mcp251863_t *ctx, uint8_t *flags)
CRC Event Get.
uint8_t * txd
Definition: mcp251863.h:1826
err_t mcp251863_crc_event_clear(mcp251863_t *ctx, uint8_t flags)
CRC Event Clear.
mcp251863_filt_obj_t f_obj
Definition: mcp251863.h:1851
pin_name_t chip_select
Definition: mcp251863.h:1873
uint32_t unimplemented3
Definition: mcp251863.h:1433
uint32_t word
Definition: mcp251863.h:1513
uint32_t word
Definition: mcp251863.h:1081
pin_name_t int_pin
Definition: mcp251863.h:1895
uint32_t unimplemented2
Definition: mcp251863.h:1619
uint32_t tx_error
Definition: mcp251863.h:1654
uint32_t tef_half_full_if
Definition: mcp251863.h:1599
uint32_t d_stuff_error
Definition: mcp251863.h:1807
uint32_t WAKIF
Definition: mcp251863.h:1537
err_t mcp251863_write_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_in, uint16_t n_words)
SPI Write Word Array.
err_t mcp251863_gpio_clock_output_configure(mcp251863_t *ctx, uint8_t mode)
Configure CLKO Pin.
uint8_t seq
Definition: mcp251863.h:884
err_t mcp251863_time_stamp_mode_configure(mcp251863_t *ctx, uint8_t mode)
Time Stamp Mode Configure.
void mcp251863_tef_configure_object_reset(mcp251863_tef_cfg_t *config)
Reset TefConfigure object to reset value.
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1822
uint32_t error_free_msg_count
Definition: mcp251863.h:1794
MCP251863 Click FIFO Status Register.
Definition: mcp251863.h:1637
uint32_t sid11
Definition: mcp251863.h:1004
uint32_t edge_filter_enable
Definition: mcp251863.h:1435
uint32_t tx_priority
Definition: mcp251863.h:1104
err_t mcp251863_crc_event_disable(mcp251863_t *ctx, uint8_t flags)
CRC Event Disnable.
uint8_t rx_flags
Definition: mcp251863.h:1839
uint32_t sclk_ready
Definition: mcp251863.h:1221
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1153
uint32_t SERRIF
Definition: mcp251863.h:1535
uint32_t word
Definition: mcp251863.h:1812
err_t mcp251863_transmit_event_attempt_get(mcp251863_t *ctx, uint32_t *txatif)
Get pending TXATIF of all transmit FIFOs.
uint32_t tx_aborted
Definition: mcp251863.h:1656
uint32_t txq_enable
Definition: mcp251863.h:1075
uint32_t parity
Definition: mcp251863.h:1287
uint32_t unimplemented2
Definition: mcp251863.h:1507
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1836
uint32_t tx_priority
Definition: mcp251863.h:1336
uint32_t crcerrif
Definition: mcp251863.h:1673
err_t mcp251863_bus_diagnostics_clear(mcp251863_t *ctx)
Clear Bus Diagnostic Registers.
uint32_t rtr
Definition: mcp251863.h:954
uint32_t store_in_tef
Definition: mcp251863.h:1310
uint32_t store_in_tef
Definition: mcp251863.h:1074
uint32_t time_stamp_enable
Definition: mcp251863.h:1127
uint32_t rx_not_empty_ie
Definition: mcp251863.h:1148
err_t mcp251863_bit_time_configure_nominal_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 40MHz system clock.
uint8_t switch_bit_rate
Definition: mcp251863.h:881
uint32_t unimplemented1
Definition: mcp251863.h:1211
uint32_t op_mode
Definition: mcp251863.h:1076
uint32_t abort_all_tx
Definition: mcp251863.h:1078
uint32_t tris1
Definition: mcp251863.h:1250
uint32_t tdc_value
Definition: mcp251863.h:1428
err_t mcp251863_operation_mode_select(mcp251863_t *ctx, uint8_t op_mode)
Select Operation Mode.
MCP251863 Click CAN Transmit Event FIFO Configure.
Definition: mcp251863.h:1376
err_t mcp251863_receive_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Receive FIFO Event Get.
uint32_t dlc
Definition: mcp251863.h:952
uint32_t tx_empty_if
Definition: mcp251863.h:1651
uint8_t tec
Definition: mcp251863.h:1841
uint32_t tef_full_if
Definition: mcp251863.h:1600
err_t mcp251863_gpio_standby_control_disable(mcp251863_t *ctx)
Disable Transceiver Standby Control.
uint32_t cerrie
Definition: mcp251863.h:1479
uint32_t word
Definition: mcp251863.h:1416
mcp251863_int_en_t ie
Definition: mcp251863.h:1562
uint32_t unimplemented6
Definition: mcp251863.h:1222
uint32_t tx_enable
Definition: mcp251863.h:1099
uint32_t unimplemented5
Definition: mcp251863.h:1265
err_t mcp251863_tef_event_get(mcp251863_t *ctx, uint8_t *flags)
Transmit Event FIFO Event Get.
uint32_t tx_empty_if
Definition: mcp251863.h:1618
uint32_t TEFIF
Definition: mcp251863.h:1528
uint32_t n_rx_error_count
Definition: mcp251863.h:1777
uint32_t unimplemented1
Definition: mcp251863.h:1126
err_t mcp251863_time_stamp_prescaler_set(mcp251863_t *ctx, uint16_t time_stamp)
Time Stamp Prescaler Set.
uint32_t word
Definition: mcp251863.h:1438
err_t mcp251863_module_event_get(mcp251863_t *ctx, uint16_t *flags)
Module Event Get.
uint32_t pay_load_size
Definition: mcp251863.h:1351
pin_name_t mosi
Definition: mcp251863.h:1888
err_t mcp251863_tef_event_enable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Enable.
uint8_t selected_bit_time
Definition: mcp251863.h:1837
uint32_t unimplemented1
Definition: mcp251863.h:1032
uint32_t unimplemented2
Definition: mcp251863.h:1732
uint32_t tdc_mode
Definition: mcp251863.h:1432
uint32_t fifo_size
Definition: mcp251863.h:1378
uint32_t unimplemented2
Definition: mcp251863.h:1154
uint32_t gpio1
Definition: mcp251863.h:1261
uint32_t TXATIF
Definition: mcp251863.h:1533
uint32_t fifo_index
Definition: mcp251863.h:1644
uint32_t TXIF
Definition: mcp251863.h:1524
uint32_t word
Definition: mcp251863.h:1183
err_t mcp251863_generic_read(mcp251863_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
MCP251863 data reading function.
MCP251863 Click CAN Control Register.
Definition: mcp251863.h:1060
uint32_t time_stamp_eof
Definition: mcp251863.h:1453
uint32_t tx_request
Definition: mcp251863.h:1174
uint32_t sid
Definition: mcp251863.h:906
uint32_t unimplemented1
Definition: mcp251863.h:1251
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1622
err_t mcp251863_ecc_event_get(mcp251863_t *ctx, uint8_t *flags)
ECC Event Get.
uint32_t tris0
Definition: mcp251863.h:1249
uint32_t word
Definition: mcp251863.h:1660
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1655
uint8_t byte
Definition: mcp251863.h:1199
err_t mcp251863_filter_disable(mcp251863_t *ctx, uint8_t filter)
Filter Disable.
uint8_t d_tec
Definition: mcp251863.h:1750
uint32_t tx_not_full_if
Definition: mcp251863.h:1616
uint32_t modie
Definition: mcp251863.h:1470
uint8_t d_rec
Definition: mcp251863.h:1749
uint32_t d_net_filter_count
Definition: mcp251863.h:850
uint32_t rtr
Definition: mcp251863.h:921
err_t mcp251863_receive_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Disable.
uint32_t n_crc_err
Definition: mcp251863.h:1727
uint32_t MODIF
Definition: mcp251863.h:1527
uint32_t d_net_filter_count
Definition: mcp251863.h:1301
MCP251863 Click CAN RX Message Object Control.
Definition: mcp251863.h:951
uint16_t word
Definition: mcp251863.h:1492
uint32_t xcr_stby_enable
Definition: mcp251863.h:1254
uint32_t unimplemented3
Definition: mcp251863.h:1070
err_t mcp251863_module_event_disable(mcp251863_t *ctx, uint16_t flags)
Module Event Disable.
uint32_t tx_aborted
Definition: mcp251863.h:1623
err_t mcp251863_receive_event_get(mcp251863_t *ctx, uint32_t *rxif)
Get pending interrupts of all receive FIFOs.
uint32_t wake_up_filter_time
Definition: mcp251863.h:1305
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:971
uint32_t user_address
Definition: mcp251863.h:1363
err_t mcp251863_module_event_rx_code_get(mcp251863_t *ctx, uint8_t *rx_code)
Get RX Code.
uint32_t dlc
Definition: mcp251863.h:919
uint32_t unimplemented1
Definition: mcp251863.h:1286
mcp251863_filt_obj_id_t bf
Definition: mcp251863.h:1016
uint32_t n_bit1_error
Definition: mcp251863.h:1796
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:852
uint32_t crc
Definition: mcp251863.h:1672
uint32_t rx_over_flow_ie
Definition: mcp251863.h:1151
uint32_t protocol_exception_event_disable
Definition: mcp251863.h:1064
uint32_t rx_full_if
Definition: mcp251863.h:1641
err_t mcp251863_transmit_channel_reset(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Reset.
uint32_t ide
Definition: mcp251863.h:953
err_t mcp251863_crc_value_get(mcp251863_t *ctx, uint16_t *crc)
Get CRC Value from device.
pin_name_t clk
Definition: mcp251863.h:1894
uint32_t ferrie
Definition: mcp251863.h:1677
uint32_t pay_load_size
Definition: mcp251863.h:1326
mcp251863_int_en_t ie
Definition: mcp251863.h:1491
uint32_t tbc_enable
Definition: mcp251863.h:1452
mcp251863_tx_fifo_cfg_t tx_config
Definition: mcp251863.h:1847
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:856
spi_master_mode_t spi_mode
Definition: mcp251863.h:1899
uint32_t word
Definition: mcp251863.h:1271
MCP251863 Click context object.
Definition: mcp251863.h:1862
err_t mcp251863_gpio_pin_set(mcp251863_t *ctx, uint8_t pos, uint8_t latch)
GPIO Output Pin Set.
err_t mcp251863_receive_channel_event_overflow_clear(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Event Clear.
MCP251863 Click ECC Control Register.
Definition: mcp251863.h:1281
MCP251863 Click CAN Bus Diagnostic flags.
Definition: mcp251863.h:1721
err_t mcp251863_tef_event_disable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Disable.
uint32_t teffulie
Definition: mcp251863.h:1124
uint8_t tx_fifo_size
Definition: mcp251863.h:873
uint32_t unimplemented1
Definition: mcp251863.h:1801
err_t mcp251863_module_event_enable(mcp251863_t *ctx, uint16_t flags)
Module Event Enable.
uint32_t unimplemented5
Definition: mcp251863.h:1106
err_t mcp251863_receive_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_fifo_cfg_t *config)
Configure Receive FIFO.
uint32_t rx_half_full_if
Definition: mcp251863.h:1640
uint32_t txatie
Definition: mcp251863.h:1476
err_t mcp251863_write_word_safe(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI RAM Write Word Safe.
uint32_t pll_ready
Definition: mcp251863.h:1710
uint32_t tx_half_full_ie
Definition: mcp251863.h:1166
err_t mcp251863_init(mcp251863_t *ctx, mcp251863_cfg_t *cfg)
MCP251863 initialization function.
uint32_t tx_attempts
Definition: mcp251863.h:1324
err_t mcp251863_error_count_state_get(mcp251863_t *ctx, uint8_t *tec, uint8_t *rec, uint8_t *flags)
Error Counts and Error State Get.
err_t mcp251863_tef_message_get(mcp251863_t *ctx, mcp251863_tef_msg_obj_t *tef_obj)
Get Transmit Event FIFO Message.
uint8_t op_mode
Definition: mcp251863.h:1843
err_t mcp251863_write_byte_array_with_crc(mcp251863_t *ctx, bool from_ram)
SPI Write Byte Array with CRC.
err_t mcp251863_ecc_event_clear(mcp251863_t *ctx, uint8_t flags)
ECC Event Clear.
MCP251863 Click CAN BUS DIAGNOSTICS.
Definition: mcp251863.h:1759
uint32_t tx_attempt_ie
Definition: mcp251863.h:1097
uint8_t fd_frame
Definition: mcp251863.h:880
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1306
MCP251863 Click CAN TX Message Object.
Definition: mcp251863.h:935
uint32_t unimplemented1
Definition: mcp251863.h:1094
uint32_t word
Definition: mcp251863.h:1396
MCP251863 Click CAN RX Message Object.
Definition: mcp251863.h:969
uint32_t unimplemented1
Definition: mcp251863.h:1584
uint32_t brp
Definition: mcp251863.h:1394
uint32_t unimplemented1
Definition: mcp251863.h:1529
MCP251863 Click Filter Object Register.
Definition: mcp251863.h:1015
err_t mcp251863_read_byte(mcp251863_t *ctx, uint16_t address, uint8_t *data_out)
SPI Read Byte function.
uint32_t unimplemented1
Definition: mcp251863.h:1065
err_t mcp251863_tef_update(mcp251863_t *ctx)
Transmit Event FIFO Update.
uint32_t freset
Definition: mcp251863.h:1158
uint32_t word
Definition: mcp251863.h:1043
err_t mcp251863_receive_event_overflow_get(mcp251863_t *ctx, uint32_t *rxovif)
Get pending RXOVIF of all receive FIFOs.
err_t mcp251863_crc_event_enable(mcp251863_t *ctx, uint8_t flags)
CRC Event Enable.
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:938
uint32_t d_stuff_err
Definition: mcp251863.h:1734
uint32_t rx_error_state_passive
Definition: mcp251863.h:1581
uint32_t serrie
Definition: mcp251863.h:1478
err_t mcp251863_receive_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint8_t *status)
Receive Channel Status Get.
MCP251863 Click CRC Regsiter.
Definition: mcp251863.h:1670
uint32_t tx_can_open_drain
Definition: mcp251863.h:1266
uint32_t store_in_tef
Definition: mcp251863.h:859
err_t mcp251863_ecc_disable(mcp251863_t *ctx)
Disable ECC.
MCP251863 Click CAN Bus Diagnostic Error Counts.
Definition: mcp251863.h:1746
uint8_t tx_pay_load_size
Definition: mcp251863.h:874
err_t mcp251863_module_event_filter_hit_get(mcp251863_t *ctx, uint8_t *filter_hit)
Get Filter Hit.
uint32_t dedif
Definition: mcp251863.h:1694
mcp251863_bus_diag_flags_t flag
Definition: mcp251863.h:1763
uint32_t tx_priority
Definition: mcp251863.h:1323
err_t mcp251863_error_state_get(mcp251863_t *ctx, uint8_t *flags)
Error State Get.
mcp251863_data_t glb_data
Definition: mcp251863.h:1875
uint32_t n_bit0_error
Definition: mcp251863.h:1795
uint32_t d_rx_error_count
Definition: mcp251863.h:1779
uint16_t n_bytes
Definition: mcp251863.h:1825
uint8_t error_flags
Definition: mcp251863.h:1840
err_t mcp251863_ecc_parity_get(mcp251863_t *ctx, uint8_t *parity)
Get ECC Parity.
uint32_t pin_mode0
Definition: mcp251863.h:1263
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1312
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1548
uint32_t d_ack_error
Definition: mcp251863.h:1805
err_t mcp251863_transmit_queue_configure(mcp251863_t *ctx, mcp251863_tx_que_cfg_t *config)
Configure Transmit Queue.
uint32_t unimplemented6
Definition: mcp251863.h:1269
uint32_t rtr_enable
Definition: mcp251863.h:1171
uint16_t standard_id
Definition: mcp251863.h:878
MCP251863 Click Diagnostic register 0.
Definition: mcp251863.h:1775
uint32_t iso_crc_enable
Definition: mcp251863.h:1302
uint32_t unimplemented5
Definition: mcp251863.h:1220
err_t mcp251863_filter_to_fifo_link(mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable)
Link Filter to FIFO.
digital_in_t clk
Definition: mcp251863.h:1867
uint32_t error_state_warning
Definition: mcp251863.h:1578
uint32_t unimplemented5
Definition: mcp251863.h:1134
err_t mcp251863_oscillator_control_set(mcp251863_t *ctx, mcp251863_div_ctl_t ctrl)
Set Oscillator Control.
uint32_t word
Definition: mcp251863.h:1604
uint16_t error_free_msg_count
Definition: mcp251863.h:1762
uint32_t unimplemented4
Definition: mcp251863.h:1436
uint32_t d_bit0_error
Definition: mcp251863.h:1803
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:1303
uint32_t tx_band_width_sharing
Definition: mcp251863.h:861
pin_name_t miso
Definition: mcp251863.h:1887
uint32_t tx_request
Definition: mcp251863.h:1101
MCP251863 Click Diagnostic register 1.
Definition: mcp251863.h:1792
err_t mcp251863_gpio_standby_control_enable(mcp251863_t *ctx)
Enable Transceiver Standby Control.
uint32_t unimplemented1
Definition: mcp251863.h:958
err_t mcp251863_read_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_out, uint16_t n_bytes)
SPI Read Byte Array.
err_t mcp251863_bit_time_configure(mcp251863_t *ctx, uint8_t bit_time, uint8_t clk)
Configure Bit Time registers (based on CAN clock speed).
uint32_t tefovie
Definition: mcp251863.h:1125
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:855
uint32_t tx_error
Definition: mcp251863.h:1621
uint32_t n_stuff_error
Definition: mcp251863.h:1799
uint32_t d_tx_error_count
Definition: mcp251863.h:1780
err_t mcp251863_module_event_clear(mcp251863_t *ctx, uint16_t flags)
Module Event Clear.
spi_master_chip_select_polarity_t cs_polarity
Definition: mcp251863.h:1900
uint32_t secie
Definition: mcp251863.h:1284
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1349
uint32_t tx_id
Definition: mcp251863.h:1844
err_t mcp251863_error_count_receive_get(mcp251863_t *ctx, uint8_t *rec)
Receive Error Count Get.
err_t mcp251863_write_byte(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI Write Byte.
uint32_t auto_sleep_enable
Definition: mcp251863.h:1253
err_t mcp251863_gpio_interrupt_pins_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain Interrupts.
uint32_t crcerrie
Definition: mcp251863.h:1676
uint32_t fifo_size
Definition: mcp251863.h:1338
uint8_t tx_priority
Definition: mcp251863.h:875
uint32_t uinc
Definition: mcp251863.h:1129
err_t mcp251863_transmit_channel_load(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_msg_obj_t *tx_obj, bool flush)
TX Channel Load.
uint32_t ferrif
Definition: mcp251863.h:1674
err_t mcp251863_bit_time_configure_nominal_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.