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35 #include "mikrosdk_version.h"
38 #if mikroSDK_GET_VERSION < 20800ul
39 #include "rcu_delays.h"
45 #include "drv_digital_out.h"
46 #include "drv_digital_in.h"
47 #include "drv_spi_master.h"
70 #define FIXED_FILTER_ADDRESS
78 #define MCP251863_FIFO_08TO15_IMPLEMENTED
79 #define MCP251863_FIFO_16TO31_IMPLEMENTED
87 #define MCP251863_FILT_08TO15_IMPLEMENTED
88 #define MCP251863_FILT_16TO31_IMPLEMENTED
96 #define CAN_INTERNAL_OSC_PRESENT
104 #define CAN_RESTRICTED_MODE_PRESENT
112 #define CAN_TXQUEUE_IMPLEMENTED
121 #define USERADDRESS_TIMES_FOUR
125 #define N_MCP2518_CTRL_REGS 5
128 #define MCP251863_MAX_TXQUEUE_ATTEMPTS 50
129 #define MCP251863_TX_REQUEST_ID 0x300
130 #define MCP251863_TX_RESPONSE_ID 0x301
132 #define MCP251863_CRCBASE 0xFFFF
133 #define MCP251863_CRCUPPER 1
134 #define MCP251863_DRV_CANFDSPI_INDEX_0 0
135 #define MCP251863_SPI_DEFAULT_BUFFER_LENGTH 96
137 #define MCP251863_ISO_CRC 1
139 #define MCP251863_MAX_MSG_SIZE 76
141 #define MCP251863_MAX_DATA_BYTES 64
143 #define MCP251863_INS_RESET 0x00
144 #define MCP251863_INS_READ 0x03
145 #define MCP251863_INS_READ_CRC 0x0B
146 #define MCP251863_INS_WRITE 0x02
147 #define MCP251863_INS_WRITE_CRC 0x0A
148 #define MCP251863_INS_WRITE_SAFE 0x0C
151 #define MCP251863_FIFO_OFFSET ( 3 * 4 )
152 #define MCP251863_FILTER_OFFSET ( 2 * 4 )
154 #ifdef CAN_TXQUEUE_IMPLEMENTED
155 #define MCP251863_REG_CITXQCON 0x050
156 #define MCP251863_REG_CITXQSTA 0x054
157 #define MCP251863_REG_CITXQUA 0x058
160 #ifdef FIXED_FILTER_ADDRESS
161 #define MCP251863_REG_CIFLTCON 0x1D0
162 #define MCP251863_REG_CIFLTOBJ 0x1F0
163 #define MCP251863_REG_CIMASK 0x1F4
165 #define MCP251863_REG_CIFLTCON ( MCP251863_REG_CIFIFOCON + ( MCP251863_FIFO_OFFSET * MCP251863_FIFO_TOTAL_CHANNELS ) )
166 #define MCP251863_REG_CIFLTOBJ ( MCP251863_REG_CIFLTCON + MCP251863_FIFO_TOTAL_CHANNELS )
167 #define MCP251863_REG_CIMASK ( MCP251863_REG_CIFLTOBJ + 4 )
170 #define MCP251863_REG_OSC 0xE00
171 #define MCP251863_REG_IOCON 0xE04
172 #define MCP251863_REG_CRC 0xE08
173 #define MCP251863_REG_ECCCON 0xE0C
174 #define MCP251863_REG_ECCSTA 0xE10
176 #define MCP251863_RAM_SIZE 2048
177 #define MCP251863_RAMADDR_START 0x400
178 #define MCP251863_RAMADDR_END ( MCP251863_RAMADDR_START + MCP251863_RAM_SIZE )
180 #define MCP251863_LOW_POWER_MODE_EN 0x08
181 #define MCP251863_LOW_POWER_MODE_DIS 0x00
182 #define MCP251863_WAKEUP_INTERR_EN 0x40
184 #define MCP251863_REG_CICON 0x000
185 #define MCP251863_REG_CINBTCFG 0x004
186 #define MCP251863_REG_CIDBTCFG 0x008
187 #define MCP251863_REG_CITDC 0x00C
189 #define MCP251863_REG_CITBC 0x010
190 #define MCP251863_REG_CITSCON 0x014
191 #define MCP251863_REG_CIVEC 0x018
192 #define MCP251863_REG_CIINT 0x01C
193 #define MCP251863_REG_CIINTFLAG MCP251863_REG_CIINT
194 #define MCP251863_REG_CIINTENABLE ( MCP251863_REG_CIINT + 2 )
196 #define MCP251863_REG_CIRXIF 0x020
197 #define MCP251863_REG_CITXIF 0x024
198 #define MCP251863_REG_CIRXOVIF 0x028
199 #define MCP251863_REG_CITXATIF 0x02C
201 #define MCP251863_REG_CITXREQ 0x030
202 #define MCP251863_REG_CITREC 0x034
203 #define MCP251863_REG_CIBDIAG0 0x038
204 #define MCP251863_REG_CIBDIAG1 0x03C
206 #define MCP251863_REG_CITEFCON 0x040
207 #define MCP251863_REG_CITEFSTA 0x044
208 #define MCP251863_REG_CITEFUA 0x048
209 #define MCP251863_REG_CIFIFOBA 0x04C
211 #define MCP251863_REG_CIFIFOCON 0x050
212 #define MCP251863_REG_CIFIFOSTA 0x054
213 #define MCP251863_REG_CIFIFOUA 0x058
246 #define MCP251863_FIFO_CH0 0
247 #define MCP251863_FIFO_CH1 1
248 #define MCP251863_FIFO_CH2 2
249 #define MCP251863_FIFO_CH3 3
250 #define MCP251863_FIFO_CH4 4
251 #define MCP251863_FIFO_CH5 5
252 #define MCP251863_FIFO_CH6 6
253 #define MCP251863_FIFO_CH7 7
255 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
256 #define MCP251863_FIFO_CH8 8
257 #define MCP251863_FIFO_CH9 9
258 #define MCP251863_FIFO_CH10 10
259 #define MCP251863_FIFO_CH11 11
260 #define MCP251863_FIFO_CH12 12
261 #define MCP251863_FIFO_CH13 13
262 #define MCP251863_FIFO_CH14 14
263 #define MCP251863_FIFO_CH15 15
266 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
267 #define MCP251863_FIFO_CH16 16
268 #define MCP251863_FIFO_CH17 17
269 #define MCP251863_FIFO_CH18 18
270 #define MCP251863_FIFO_CH19 19
271 #define MCP251863_FIFO_CH20 20
272 #define MCP251863_FIFO_CH21 21
273 #define MCP251863_FIFO_CH22 22
274 #define MCP251863_FIFO_CH23 23
275 #define MCP251863_FIFO_CH24 24
276 #define MCP251863_FIFO_CH25 25
277 #define MCP251863_FIFO_CH26 26
278 #define MCP251863_FIFO_CH27 27
279 #define MCP251863_FIFO_CH28 28
280 #define MCP251863_FIFO_CH29 29
281 #define MCP251863_FIFO_CH30 30
282 #define MCP251863_FIFO_CH31 31
286 #define MCP251863_FIFO_TOTAL_CHANNELS 32
288 #ifdef CAN_TXQUEUE_IMPLEMENTED
289 #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1
290 #define CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0
292 #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH0
299 #define MCP251863_FILT0 0
300 #define MCP251863_FILT1 1
301 #define MCP251863_FILT2 2
302 #define MCP251863_FILT3 3
303 #define MCP251863_FILT4 4
304 #define MCP251863_FILT5 5
305 #define MCP251863_FILT6 6
306 #define MCP251863_FILT7 7
308 #ifdef MCP251863_FILT_08TO15_IMPLEMENTED
309 #define MCP251863_FILT8 8
310 #define MCP251863_FILT9 9
311 #define MCP251863_FILT10 10
312 #define MCP251863_FILT11 11
313 #define MCP251863_FILT12 12
314 #define MCP251863_FILT13 13
315 #define MCP251863_FILT14 14
316 #define MCP251863_FILT15 15
319 #ifdef MCP251863_FILT_16TO31_IMPLEMENTED
320 #define MCP251863_FILT16 16
321 #define MCP251863_FILT17 17
322 #define MCP251863_FILT18 18
323 #define MCP251863_FILT19 19
324 #define MCP251863_FILT20 20
325 #define MCP251863_FILT21 21
326 #define MCP251863_FILT22 22
327 #define MCP251863_FILT23 23
328 #define MCP251863_FILT24 24
329 #define MCP251863_FILT25 25
330 #define MCP251863_FILT26 26
331 #define MCP251863_FILT27 27
332 #define MCP251863_FILT28 28
333 #define MCP251863_FILT29 29
334 #define MCP251863_FILT30 30
335 #define MCP251863_FILT31 31
338 #define MCP251863_FILT_TOTAL 32
344 #define MCP251863_NORMAL_MODE 0x00
345 #define MCP251863_SLEEP_MODE 0x01
346 #define MCP251863_INT_LOOP_MODE 0x02
347 #define MCP251863_LISTEN_ONLY_MODE 0x03
348 #define MCP251863_CONFIG_MODE 0x04
349 #define MCP251863_EXT_LOOP_MODE 0x05
350 #define MCP251863_CLASSIC_MODE 0x06
351 #define MCP251863_RESTRICT_MODE 0x07
352 #define MCP251863_INVALID_MODE 0xFF
358 #define MCP251863_TXBWS_NO_DELAY 0
359 #define MCP251863_TXBWS_2 1
360 #define MCP251863_TXBWS_4 2
361 #define MCP251863_TXBWS_8 3
362 #define MCP251863_TXBWS_16 4
363 #define MCP251863_TXBWS_32 5
364 #define MCP251863_TXBWS_64 6
365 #define MCP251863_TXBWS_128 7
366 #define MCP251863_TXBWS_256 8
367 #define MCP251863_TXBWS_512 9
368 #define MCP251863_TXBWS_1024 10
369 #define MCP251863_TXBWS_2048 11
370 #define MCP251863_TXBWS_4096 12
376 #define MCP251863_WFT00 0
377 #define MCP251863_WFT01 1
378 #define MCP251863_WFT10 2
379 #define MCP251863_WFT11 3
385 #define MCP251863_DNET_FILT_DISABLE 0
386 #define MCP251863_DNET_FILT_SIZE_1_BIT 1
387 #define MCP251863_DNET_FILT_SIZE_2_BIT 2
388 #define MCP251863_DNET_FILT_SIZE_3_BIT 3
389 #define MCP251863_DNET_FILT_SIZE_4_BIT 4
390 #define MCP251863_DNET_FILT_SIZE_5_BIT 5
391 #define MCP251863_DNET_FILT_SIZE_6_BIT 6
392 #define MCP251863_DNET_FILT_SIZE_7_BIT 7
393 #define MCP251863_DNET_FILT_SIZE_8_BIT 8
394 #define MCP251863_DNET_FILT_SIZE_9_BIT 9
395 #define MCP251863_DNET_FILT_SIZE_10_BIT 10
396 #define MCP251863_DNET_FILT_SIZE_11_BIT 11
397 #define MCP251863_DNET_FILT_SIZE_12_BIT 12
398 #define MCP251863_DNET_FILT_SIZE_13_BIT 13
399 #define MCP251863_DNET_FILT_SIZE_14_BIT 14
400 #define MCP251863_DNET_FILT_SIZE_15_BIT 15
401 #define MCP251863_DNET_FILT_SIZE_16_BIT 16
402 #define MCP251863_DNET_FILT_SIZE_17_BIT 17
403 #define MCP251863_DNET_FILT_SIZE_18_BIT 18
409 #define MCP251863_PLSIZE_8 0
410 #define MCP251863_PLSIZE_12 1
411 #define MCP251863_PLSIZE_16 2
412 #define MCP251863_PLSIZE_20 3
413 #define MCP251863_PLSIZE_24 4
414 #define MCP251863_PLSIZE_32 5
415 #define MCP251863_PLSIZE_48 6
416 #define MCP251863_PLSIZE_64 7
422 #define MCP251863_DLC_0 0
423 #define MCP251863_DLC_1 1
424 #define MCP251863_DLC_2 2
425 #define MCP251863_DLC_3 3
426 #define MCP251863_DLC_4 4
427 #define MCP251863_DLC_5 5
428 #define MCP251863_DLC_6 6
429 #define MCP251863_DLC_7 7
430 #define MCP251863_DLC_8 8
431 #define MCP251863_DLC_12 9
432 #define MCP251863_DLC_16 10
433 #define MCP251863_DLC_20 11
434 #define MCP251863_DLC_24 12
435 #define MCP251863_DLC_32 13
436 #define MCP251863_DLC_48 14
437 #define MCP251863_DLC_64 15
443 #define MCP251863_RX_FIFO_EMPTY 0
444 #define MCP251863_RX_FIFO_STATUS_MASK 0x0F
445 #define MCP251863_RX_FIFO_NOT_EMPTY 0x01
446 #define MCP251863_RX_FIFO_HALF_FULL 0x02
447 #define MCP251863_RX_FIFO_FULL 0x04
448 #define MCP251863_RX_FIFO_OVERFLOW 0x08
454 #define MCP251863_TX_FIFO_FULL 0
455 #define MCP251863_TX_FIFO_STATUS_MASK 0x1F7
456 #define MCP251863_TX_FIFO_NOT_FULL 0x01
457 #define MCP251863_TX_FIFO_HALF_FULL 0x02
458 #define MCP251863_TX_FIFO_EMPTY 0x04
459 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10
460 #define MCP251863_TX_FIFO_ERROR 0x20
461 #define MCP251863_TX_FIFO_ARBITRATION_LOST 0x40
462 #define MCP251863_TX_FIFO_ABORTED 0x80
463 #define MCP251863_TX_FIFO_TRANSMITTING 0x100
469 #define MCP251863_TEF_FIFO_EMPTY 0
470 #define MCP251863_TEF_FIFO_STATUS_MASK 0x0F
471 #define MCP251863_TEF_FIFO_NOT_EMPTY 0x01
472 #define MCP251863_TEF_FIFO_HALF_FULL 0x02
473 #define MCP251863_TEF_FIFO_FULL 0x04
474 #define MCP251863_TEF_FIFO_OVERFLOW 0x08
480 #define MCP251863_TX_FIFO_NO_EVENT 0
481 #define MCP251863_TX_FIFO_ALL_EVENTS 0x17
482 #define MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01
483 #define MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02
484 #define MCP251863_TX_FIFO_EMPTY_EVENT 0x04
485 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10
487 #define MCP251863_RX_FIFO_NO_EVENT 0
488 #define MCP251863_RX_FIFO_ALL_EVENTS 0x0F
489 #define MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01
490 #define MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02
491 #define MCP251863_RX_FIFO_FULL_EVENT 0x04
492 #define MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08
494 #define MCP251863_TEF_FIFO_NO_EVENT 0
495 #define MCP251863_TEF_FIFO_ALL_EVENTS 0x0F
496 #define MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01
497 #define MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02
498 #define MCP251863_TEF_FIFO_FULL_EVENT 0x04
499 #define MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08
501 #define MCP251863_NO_EVENT 0
502 #define MCP251863_ALL_EVENTS 0xFF1F
503 #define MCP251863_TX_EVENT 0x0001
504 #define MCP251863_RX_EVENT 0x0002
505 #define MCP251863_TIME_BASE_COUNTER_EVENT 0x0004
506 #define MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008
507 #define MCP251863_TEF_EVENT 0x0010
509 #define MCP251863_RAM_ECC_EVENT 0x0100
510 #define MCP251863_SPI_CRC_EVENT 0x0200
511 #define MCP251863_TX_ATTEMPTS_EVENT 0x0400
512 #define MCP251863_RX_OVERFLOW_EVENT 0x0800
513 #define MCP251863_SYSTEM_ERROR_EVENT 0x1000
514 #define MCP251863_BUS_ERROR_EVENT 0x2000
515 #define MCP251863_BUS_WAKEUP_EVENT 0x4000
516 #define MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000
518 #define MCP251863_500K_1M 0
519 #define MCP251863_500K_2M 1
520 #define MCP251863_500K_3M 2
521 #define MCP251863_500K_4M 3
522 #define MCP251863_500K_5M 4
523 #define MCP251863_500K_6M7 5
524 #define MCP251863_500K_8M 6
525 #define MCP251863_500K_10M 7
526 #define MCP251863_250K_500K 8
527 #define MCP251863_250K_833K 9
528 #define MCP251863_250K_1M 10
529 #define MCP251863_250K_1M5 11
530 #define MCP251863_250K_2M 12
531 #define MCP251863_250K_3M 13
532 #define MCP251863_250K_4M 14
533 #define MCP251863_1000K_4M 15
534 #define MCP251863_1000K_8M 16
535 #define MCP251863_125K_500K 17
537 #define MCP251863_NBT_125K 0
538 #define MCP251863_NBT_250K 1
539 #define MCP251863_NBT_500K 2
540 #define MCP251863_NBT_1M 3
542 #define MCP251863_DBT_500K 0
543 #define MCP251863_DBT_833K 1
544 #define MCP251863_DBT_1M 2
545 #define MCP251863_DBT_1M5 3
546 #define MCP251863_DBT_2M 4
547 #define MCP251863_DBT_3M 5
548 #define MCP251863_DBT_4M 6
549 #define MCP251863_DBT_5M 7
550 #define MCP251863_DBT_6M7 8
551 #define MCP251863_DBT_8M 9
552 #define MCP251863_DBT_10M 10
554 #define MCP251863_SSP_MODE_OFF 0
555 #define MCP251863_SSP_MODE_MANUAL 1
556 #define MCP251863_SSP_MODE_AUTO 2
558 #define MCP251863_ERROR_FREE_STATE 0
559 #define MCP251863_ERROR_ALL 0x3F
560 #define MCP251863_TX_RX_WARNING_STATE 0x01
561 #define MCP251863_RX_WARNING_STATE 0x02
562 #define MCP251863_TX_WARNING_STATE 0x04
563 #define MCP251863_RX_BUS_PASSIVE_STATE 0x08
564 #define MCP251863_TX_BUS_PASSIVE_STATE 0x10
565 #define MCP251863_TX_BUS_OFF_STATE 0x20
567 #define MCP251863_TS_SOF 0x00
568 #define MCP251863_TS_EOF 0x01
569 #define MCP251863_TS_RES 0x02
571 #define MCP2518_ECC_NO_EVENT 0x00
572 #define MCP2518_ECC_ALL_EVENTS 0x06
573 #define MCP2518_ECC_SEC_EVENT 0x02
574 #define MCP2518_ECC_DED_EVENT 0x04
576 #define MCP251863_CRC_NO_EVENT 0x00
577 #define MCP251863_CRC_ALL_EVENTS 0x03
578 #define MCP251863_CRC_CRCERR_EVENT 0x01
579 #define MCP251863_CRC_FORMERR_EVENT 0x02
585 #define MCP251863_PIN_0 0
586 #define MCP251863_PIN_1 1
588 #define MCP251863_PINMODE_INT 0
589 #define MCP251863_PINMODE_GPIO 1
591 #define MCP251863_PINOUT 0
592 #define MCP251863_PININ 1
594 #define MCP251863_PINLOW 0
595 #define MCP251863_PINHIGH 1
597 #define MCP251863_PUSHPULL 0
598 #define MCP251863_OPENDRAIN 1
600 #define MCP251863_CLKO_CLOCK 0
601 #define MCP251863_CLKO_SOF 1
607 #define MCP251863_TXREQ_CH0 0x00000001
608 #define MCP251863_TXREQ_CH1 0x00000002
609 #define MCP251863_TXREQ_CH2 0x00000004
610 #define MCP251863_TXREQ_CH3 0x00000008
611 #define MCP251863_TXREQ_CH4 0x00000010
612 #define MCP251863_TXREQ_CH5 0x00000020
613 #define MCP251863_TXREQ_CH6 0x00000040
614 #define MCP251863_TXREQ_CH7 0x00000080
616 #define MCP251863_TXREQ_CH8 0x00000100
617 #define MCP251863_TXREQ_CH9 0x00000200
618 #define MCP251863_TXREQ_CH10 0x00000400
619 #define MCP251863_TXREQ_CH11 0x00000800
620 #define MCP251863_TXREQ_CH12 0x00001000
621 #define MCP251863_TXREQ_CH13 0x00002000
622 #define MCP251863_TXREQ_CH14 0x00004000
623 #define MCP251863_TXREQ_CH15 0x00008000
625 #define MCP251863_TXREQ_CH16 0x00010000
626 #define MCP251863_TXREQ_CH17 0x00020000
627 #define MCP251863_TXREQ_CH18 0x00040000
628 #define MCP251863_TXREQ_CH19 0x00080000
629 #define MCP251863_TXREQ_CH20 0x00100000
630 #define MCP251863_TXREQ_CH21 0x00200000
631 #define MCP251863_TXREQ_CH22 0x00400000
632 #define MCP251863_TXREQ_CH23 0x00800000
634 #define MCP251863_TXREQ_CH24 0x01000000
635 #define MCP251863_TXREQ_CH25 0x02000000
636 #define MCP251863_TXREQ_CH26 0x04000000
637 #define MCP251863_TXREQ_CH27 0x08000000
638 #define MCP251863_TXREQ_CH28 0x10000000
639 #define MCP251863_TXREQ_CH29 0x20000000
640 #define MCP251863_TXREQ_CH30 0x40000000
641 #define MCP251863_TXREQ_CH31 0x80000000
647 #define MCP251863_ICODE_FIFO_CH0 0
648 #define MCP251863_ICODE_FIFO_CH1 1
649 #define MCP251863_ICODE_FIFO_CH2 2
650 #define MCP251863_ICODE_FIFO_CH3 3
651 #define MCP251863_ICODE_FIFO_CH4 4
652 #define MCP251863_ICODE_FIFO_CH5 5
653 #define MCP251863_ICODE_FIFO_CH6 6
654 #define MCP251863_ICODE_FIFO_CH7 7
656 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
657 #define MCP251863_ICODE_FIFO_CH8 8
658 #define MCP251863_ICODE_FIFO_CH9 9
659 #define MCP251863_ICODE_FIFO_CH10 10
660 #define MCP251863_ICODE_FIFO_CH11 11
661 #define MCP251863_ICODE_FIFO_CH12 12
662 #define MCP251863_ICODE_FIFO_CH13 13
663 #define MCP251863_ICODE_FIFO_CH14 14
664 #define MCP251863_ICODE_FIFO_CH15 15
667 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
668 #define MCP251863_ICODE_FIFO_CH16 16
669 #define MCP251863_ICODE_FIFO_CH17 17
670 #define MCP251863_ICODE_FIFO_CH18 18
671 #define MCP251863_ICODE_FIFO_CH19 19
672 #define MCP251863_ICODE_FIFO_CH20 20
673 #define MCP251863_ICODE_FIFO_CH21 21
674 #define MCP251863_ICODE_FIFO_CH22 22
675 #define MCP251863_ICODE_FIFO_CH23 23
676 #define MCP251863_ICODE_FIFO_CH24 24
677 #define MCP251863_ICODE_FIFO_CH25 25
678 #define MCP251863_ICODE_FIFO_CH26 26
679 #define MCP251863_ICODE_FIFO_CH27 27
680 #define MCP251863_ICODE_FIFO_CH28 28
681 #define MCP251863_ICODE_FIFO_CH29 29
682 #define MCP251863_ICODE_FIFO_CH30 30
683 #define MCP251863_ICODE_FIFO_CH31 31
686 #define MCP251863_ICODE_TOTAL_CHANNELS 32
687 #define MCP251863_ICODE_NO_INT 64
688 #define MCP251863_ICODE_CERRIF 65
689 #define MCP251863_ICODE_WAKIF 66
690 #define MCP251863_ICODE_RXOVIF 67
691 #define MCP251863_ICODE_ADDRERR_SERRIF 68
692 #define MCP251863_ICODE_MABOV_SERRIF 69
693 #define MCP251863_ICODE_TBCIF 70
694 #define MCP251863_ICODE_MODIF 71
695 #define MCP251863_ICODE_IVMIF 72
696 #define MCP251863_ICODE_TEFIF 73
697 #define MCP251863_ICODE_TXATIF 74
698 #define MCP251863_ICODE_RESERVED 75
704 #define MCP251863_RXCODE_FIFO_CH0 0
705 #define MCP251863_RXCODE_FIFO_CH1 1
706 #define MCP251863_RXCODE_FIFO_CH2 2
707 #define MCP251863_RXCODE_FIFO_CH3 3
708 #define MCP251863_RXCODE_FIFO_CH4 4
709 #define MCP251863_RXCODE_FIFO_CH5 5
710 #define MCP251863_RXCODE_FIFO_CH6 6
711 #define MCP251863_RXCODE_FIFO_CH7 7
713 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
714 #define MCP251863_RXCODE_FIFO_CH8 8
715 #define MCP251863_RXCODE_FIFO_CH9 9
716 #define MCP251863_RXCODE_FIFO_CH10 10
717 #define MCP251863_RXCODE_FIFO_CH11 11
718 #define MCP251863_RXCODE_FIFO_CH12 12
719 #define MCP251863_RXCODE_FIFO_CH13 13
720 #define MCP251863_RXCODE_FIFO_CH14 14
721 #define MCP251863_RXCODE_FIFO_CH15 15
724 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
725 #define MCP251863_RXCODE_FIFO_CH16 16
726 #define MCP251863_RXCODE_FIFO_CH17 17
727 #define MCP251863_RXCODE_FIFO_CH18 18
728 #define MCP251863_RXCODE_FIFO_CH19 19
729 #define MCP251863_RXCODE_FIFO_CH20 20
730 #define MCP251863_RXCODE_FIFO_CH21 21
731 #define MCP251863_RXCODE_FIFO_CH22 22
732 #define MCP251863_RXCODE_FIFO_CH23 23
733 #define MCP251863_RXCODE_FIFO_CH24 24
734 #define MCP251863_RXCODE_FIFO_CH25 25
735 #define MCP251863_RXCODE_FIFO_CH26 26
736 #define MCP251863_RXCODE_FIFO_CH27 27
737 #define MCP251863_RXCODE_FIFO_CH28 28
738 #define MCP251863_RXCODE_FIFO_CH29 29
739 #define MCP251863_RXCODE_FIFO_CH30 30
740 #define MCP251863_RXCODE_FIFO_CH31 31
743 #define MCP251863_RXCODE_TOTAL_CHANNELS 32
744 #define MCP251863_RXCODE_NO_INT 64
745 #define MCP251863_RXCODE_RESERVED 65
751 #define MCP251863_TXCODE_FIFO_CH0 0
752 #define MCP251863_TXCODE_FIFO_CH1 1
753 #define MCP251863_TXCODE_FIFO_CH2 2
754 #define MCP251863_TXCODE_FIFO_CH3 3
755 #define MCP251863_TXCODE_FIFO_CH4 4
756 #define MCP251863_TXCODE_FIFO_CH5 5
757 #define MCP251863_TXCODE_FIFO_CH6 6
758 #define MCP251863_TXCODE_FIFO_CH7 7
760 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
761 #define MCP251863_TXCODE_FIFO_CH8 8
762 #define MCP251863_TXCODE_FIFO_CH9 9
763 #define MCP251863_TXCODE_FIFO_CH10 10
764 #define MCP251863_TXCODE_FIFO_CH11 11
765 #define MCP251863_TXCODE_FIFO_CH12 12
766 #define MCP251863_TXCODE_FIFO_CH13 13
767 #define MCP251863_TXCODE_FIFO_CH14 14
768 #define MCP251863_TXCODE_FIFO_CH15 15
771 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
772 #define MCP251863_TXCODE_FIFO_CH16 16
773 #define MCP251863_TXCODE_FIFO_CH17 17
774 #define MCP251863_TXCODE_FIFO_CH18 18
775 #define MCP251863_TXCODE_FIFO_CH19 19
776 #define MCP251863_TXCODE_FIFO_CH20 20
777 #define MCP251863_TXCODE_FIFO_CH21 21
778 #define MCP251863_TXCODE_FIFO_CH22 22
779 #define MCP251863_TXCODE_FIFO_CH23 23
780 #define MCP251863_TXCODE_FIFO_CH24 24
781 #define MCP251863_TXCODE_FIFO_CH25 25
782 #define MCP251863_TXCODE_FIFO_CH26 26
783 #define MCP251863_TXCODE_FIFO_CH27 27
784 #define MCP251863_TXCODE_FIFO_CH28 28
785 #define MCP251863_TXCODE_FIFO_CH29 29
786 #define MCP251863_TXCODE_FIFO_CH30 30
787 #define MCP251863_TXCODE_FIFO_CH31 31
790 #define MCP251863_TXCODE_TOTAL_CHANNELS 32
791 #define MCP251863_TXCODE_NO_INT 64
792 #define MCP251863_TXCODE_RESERVED 65
798 #define MCP251863_SYSCLK_40M 0
799 #define MCP251863_SYSCLK_20M 1
800 #define MCP251863_SYSCLK_10M 2
806 #define MCP251863_CLKO_DIV1 0
807 #define MCP251863_CLKO_DIV2 1
808 #define MCP251863_CLKO_DIV4 2
809 #define MCP251863_CLKO_DIV10 3
811 #define N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )
812 #define N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )
813 #define N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )
823 #define MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
824 #define MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
842 #define MCP251863_MAP_MIKROBUS( cfg, mikrobus ) \
843 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
844 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
845 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
846 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
847 cfg.stby = MIKROBUS( mikrobus, MIKROBUS_AN ); \
848 cfg.clk = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
849 cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
1178 uint32_t unimplemented1 : 1;
1180 uint32_t unimplemented2 : 1;
1182 uint32_t tx_enable : 1;
1185 uint32_t freset : 1;
1186 uint32_t unimplemented3 : 5;
1189 uint32_t unimplemented4 : 1;
1190 uint32_t fifo_size : 5;
1191 uint32_t pay_load_size : 3;
1662 uint32_t unimplemented1 : 1;
1667 uint32_t fifo_index : 5;
1668 uint32_t unimplemented2 : 19;
3740 #endif // MCP251863_H
uint32_t spi_speed
Definition: mcp251863.h:1908
uint32_t unimplemented1
Definition: mcp251863.h:1400
uint32_t freset
Definition: mcp251863.h:1112
MCP251863 Click Transmit Event FIFO Control Register.
Definition: mcp251863.h:1130
uint32_t meid
Definition: mcp251863.h:1039
err_t mcp251863_read_word(mcp251863_t *ctx, uint16_t address, uint32_t *data_out)
SPI Read Word.
uint32_t rx_over_flow_if
Definition: mcp251863.h:1652
err_t mcp251863_write_half_word(mcp251863_t *ctx, uint16_t address, uint16_t data_in)
SPI Write Half Word.
uint8_t n_rec
Definition: mcp251863.h:1757
err_t mcp251863_transmit_channel_event_attempt_clear(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Event Clear.
err_t mcp251863_transmit_request_get(mcp251863_t *ctx, uint32_t *tx_req)
Get TXREQ register.
MCP251863 Click Interrupt Vector Register.
Definition: mcp251863.h:1512
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1082
mcp251863_rx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:982
uint32_t tx_not_full_if
Definition: mcp251863.h:1659
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:983
uint32_t unimplemented3
Definition: mcp251863.h:1226
uint32_t unimplemented4
Definition: mcp251863.h:1142
uint32_t unimplemented3
Definition: mcp251863.h:1268
uint32_t fdf
Definition: mcp251863.h:933
uint32_t tx_attempts
Definition: mcp251863.h:1115
pin_name_t sck
Definition: mcp251863.h:1899
err_t mcp251863_bit_time_configure_data_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 10MHz system clock.
uint32_t error_address
Definition: mcp251863.h:1706
uint32_t d_form_error
Definition: mcp251863.h:1816
uint32_t ivmie
Definition: mcp251863.h:1491
uint32_t swj
Definition: mcp251863.h:1399
MCP251863 Click FIFO Control Register.
Definition: mcp251863.h:1156
uint32_t unimplemented2
Definition: mcp251863.h:1482
MCP251863 Click configuration object.
Definition: mcp251863.h:1895
uint32_t wake_up_filter_time
Definition: mcp251863.h:1077
err_t mcp251863_ecc_event_enable(mcp251863_t *ctx, uint8_t flags)
ECC Event Enable.
uint32_t dedie
Definition: mcp251863.h:1295
uint32_t unimplemented1
Definition: mcp251863.h:1419
uint32_t n_ack_error
Definition: mcp251863.h:1807
uint32_t n_stuff_err
Definition: mcp251863.h:1736
err_t mcp251863_ecc_enable(mcp251863_t *ctx)
Enable ECC.
uint32_t unimplemented2
Definition: mcp251863.h:1138
uint32_t unimplemented2
Definition: mcp251863.h:1298
uint32_t brp
Definition: mcp251863.h:1424
MCP251863 Click CAN Receive Channel Configure.
Definition: mcp251863.h:1358
err_t mcp251863_gpio_transmit_pin_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain TXCAN.
err_t mcp251863_receive_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Receive FIFO Index Get.
err_t mcp251863_oscillator_status_get(mcp251863_t *ctx, mcp251863_osc_sta_t *status)
Get Oscillator Status.
err_t mcp251863_bit_time_configure_data_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 40MHz system clock.
err_t mcp251863_receive_channel_update(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Update.
err_t mcp251863_transmit_channel_abort(mcp251863_t *ctx, uint8_t channel)
Abort transmission of single FIFO.
uint32_t tx_enable
Definition: mcp251863.h:1165
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:947
uint32_t tefhfie
Definition: mcp251863.h:1133
err_t mcp251863_transmit_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Transmit FIFO Event Get.
uint32_t d_crc_err
Definition: mcp251863.h:1745
err_t mcp251863_device_net_filter_count_set(mcp251863_t *ctx, uint8_t dnfc)
Set Device Net Filter Count.
uint32_t tx_error_state_warning
Definition: mcp251863.h:1590
uint32_t RXOVIF
Definition: mcp251863.h:1544
MCP251863 Click Transmit/Receive Error Count Register.
Definition: mcp251863.h:1584
uint32_t wake_up_filter_enable
Definition: mcp251863.h:863
err_t mcp251863_oscillator_enable(mcp251863_t *ctx)
Enable oscillator to wake-up from sleep.
uint32_t esi
Definition: mcp251863.h:1819
err_t mcp251863_transmit_channel_flush(mcp251863_t *ctx, uint8_t channel)
TX Channel Flush.
MCP251863 Click Mask Object Register.
Definition: mcp251863.h:1051
uint32_t swj
Definition: mcp251863.h:1418
void mcp251863_oscillator_control_object_reset(mcp251863_div_ctl_t *ctrl)
Reset Oscillator Control.
MCP251863 Click Oscillator Control.
Definition: mcp251863.h:1244
uint32_t tx_error_state_passive
Definition: mcp251863.h:1592
uint32_t seq
Definition: mcp251863.h:935
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1319
mcp251863_bus_error_count_t error_count
Definition: mcp251863.h:1771
uint32_t tx_empty_ie
Definition: mcp251863.h:1177
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1083
uint32_t unimplemented2
Definition: mcp251863.h:1705
uint32_t sclk_ready
Definition: mcp251863.h:1722
uint16_t mcp251863_calculate_crc16(uint8_t *data_pointer, uint16_t size)
Calculate CRC16.
err_t mcp251863_module_event_icode_get(mcp251863_t *ctx, uint8_t *icode)
Get ICODE.
uint32_t rx_half_full_ie
Definition: mcp251863.h:1159
MCP251863 Click CAN Transmit Channel Configure.
Definition: mcp251863.h:1331
uint32_t unimplemented2
Definition: mcp251863.h:1688
uint32_t clk_out_divide
Definition: mcp251863.h:1248
uint32_t sof_output_enable
Definition: mcp251863.h:1277
uint32_t fdf
Definition: mcp251863.h:966
MCP251863 Click Time Stamp Configuration Register.
Definition: mcp251863.h:1458
uint32_t unimplemented1
Definition: mcp251863.h:1206
err_t mcp251863_ecc_error_address_get(mcp251863_t *ctx, uint16_t *address)
Get ECC Error Address.
uint32_t tseg2
Definition: mcp251863.h:1401
uint32_t fifo_index
Definition: mcp251863.h:1634
uint32_t unimplemented2
Definition: mcp251863.h:970
uint32_t pll_enable
Definition: mcp251863.h:1220
uint32_t unimplemented1
Definition: mcp251863.h:1515
uint8_t mcp251863_operation_mode_get(mcp251863_t *ctx)
Get Operation Mode.
uint32_t ecc_en
Definition: mcp251863.h:1293
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1081
err_t mcp251863_module_event_tx_code_get(mcp251863_t *ctx, uint8_t *tx_code)
Get TX Code.
uint32_t n_bit0_err
Definition: mcp251863.h:1732
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1076
uint32_t word
Definition: mcp251863.h:1574
uint8_t tx_flags
Definition: mcp251863.h:1848
uint32_t unimplemented1
Definition: mcp251863.h:1374
MCP251863 Click Data Bit Time Configuration Register.
Definition: mcp251863.h:1416
uint8_t rx_pay_load_size
Definition: mcp251863.h:887
uint32_t osc_disable
Definition: mcp251863.h:1246
uint16_t address
Definition: mcp251863.h:1833
err_t mcp251863_tef_status_get(mcp251863_t *ctx, uint8_t *status)
Transmit Event FIFO Status Get.
uint32_t freset
Definition: mcp251863.h:1141
err_t mcp251863_transmit_request_set(mcp251863_t *ctx, uint32_t tx_req)
Request transmissions using TXREQ register.
digital_out_t stby
Definition: mcp251863.h:1874
MCP251863 Click FIFO User Address Register.
Definition: mcp251863.h:1371
err_t mcp251863_time_stamp_enable(mcp251863_t *ctx)
Time Stamp Enable.
err_t mcp251863_transmit_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Enable.
MCP251863 Click CAN Mask Object ID.
Definition: mcp251863.h:1037
MCP251863 Click I/O Control Register.
Definition: mcp251863.h:1257
This file contains SPI specific macros, functions, etc.
uint32_t word
Definition: mcp251863.h:1146
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:867
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:998
err_t mcp251863_read_half_word(mcp251863_t *ctx, uint16_t address, uint16_t *data_out)
SPI Read Half Word.
err_t mcp251863_bit_time_configure_nominal_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 10MHz system clock.
err_t mcp251863_ecc_event_disable(mcp251863_t *ctx, uint8_t flags)
ECC Event Disable.
uint32_t filter_hit
Definition: mcp251863.h:969
MCP251863 Click Transmit Queue Control Register.
Definition: mcp251863.h:1101
uint32_t word
Definition: mcp251863.h:1300
uint8_t rec
Definition: mcp251863.h:1852
uint32_t CERRIF
Definition: mcp251863.h:1546
uint32_t txbo_err
Definition: mcp251863.h:1739
uint32_t lat0
Definition: mcp251863.h:1266
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1089
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:999
uint32_t fifo_size
Definition: mcp251863.h:1170
uint32_t word
Definition: mcp251863.h:1234
@ MCP251863_OK
Definition: mcp251863.h:1920
uint32_t uinc
Definition: mcp251863.h:1110
err_t mcp251863_transmit_band_width_sharing_set(mcp251863_t *ctx, uint8_t tx_bws)
Set Transmit Bandwidth Sharing Delay.
uint32_t rxie
Definition: mcp251863.h:1478
uint32_t tx_empty_ie
Definition: mcp251863.h:1105
err_t mcp251863_write_byte_safe(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI SFR Write Byte Safe.
MCP251863 Click Interrupt Configuration.
Definition: mcp251863.h:1500
uint32_t brs
Definition: mcp251863.h:965
uint32_t word
Definition: mcp251863.h:1792
uint32_t unimplemented1
Definition: mcp251863.h:1461
err_t mcp251863_transmit_channel_update(mcp251863_t *ctx, uint8_t channel, bool flush)
Transmit FIFO Update.
uint32_t esi
Definition: mcp251863.h:967
uint8_t ide
Definition: mcp251863.h:892
err_t mcp251863_filter_object_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_filt_obj_id_t *id)
Filter Object Configuration.
MCP251863 Click Transmit Event FIFO Status Register.
Definition: mcp251863.h:1606
uint32_t rx_error_count
Definition: mcp251863.h:1586
uint32_t TBCIF
Definition: mcp251863.h:1536
spi_master_t spi
Definition: mcp251863.h:1881
MCP251863 Click ECC Status Register.
Definition: mcp251863.h:1700
err_t mcp251863_time_stamp_disable(mcp251863_t *ctx)
Time Stamp Disable.
uint32_t tx_attempt_ie
Definition: mcp251863.h:1179
err_t mcp251863_error_count_transmit_get(mcp251863_t *ctx, uint8_t *tec)
Transmit Error Count Get.
uint32_t tseg2
Definition: mcp251863.h:1420
MCP251863 Click Oscillator Control Register.
Definition: mcp251863.h:1218
uint32_t unimplemented1
Definition: mcp251863.h:1685
MCP251863 Click Filter Control Register.
Definition: mcp251863.h:1203
uint32_t osc_disable
Definition: mcp251863.h:1222
err_t mcp251863_write_word(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI Write Word.
uint32_t tx_not_full_ie
Definition: mcp251863.h:1103
uint32_t sclk_divide
Definition: mcp251863.h:1224
uint32_t unimplemented2
Definition: mcp251863.h:1223
uint32_t tx_attempts
Definition: mcp251863.h:1347
uint32_t tefneie
Definition: mcp251863.h:1132
uint32_t unimplemented1
Definition: mcp251863.h:936
uint32_t n_form_error
Definition: mcp251863.h:1808
uint32_t esi
Definition: mcp251863.h:1746
uint32_t rx_error_state_warning
Definition: mcp251863.h:1589
mcp251863_rx_fifo_cfg_t rx_config
Definition: mcp251863.h:1858
uint32_t word
Definition: mcp251863.h:1120
uint32_t unimplemented3
Definition: mcp251863.h:1423
err_t mcp251863_time_stamp_set(mcp251863_t *ctx, uint32_t ts)
Time Stamp Set.
uint32_t word
Definition: mcp251863.h:1690
uint32_t word
Definition: mcp251863.h:1466
uint32_t d_bit1_error
Definition: mcp251863.h:1814
uint32_t mcp251863_msg_time_stamp_t
MCP251863 Click CAN Message Time Stamp.
Definition: mcp251863.h:908
err_t mcp251863_transmit_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Transmit FIFO Index Get.
mcp251863_mask_obj_t m_obj
Definition: mcp251863.h:1862
err_t mcp251863_transmit_event_get(mcp251863_t *ctx, uint32_t *txif)
Get pending interrupts of all transmit FIFOs.
uint32_t d_net_filter_count
Definition: mcp251863.h:1072
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1317
uint32_t unimplemented1
Definition: mcp251863.h:1439
uint8_t mcp251863_data_bytes_to_dlc(uint8_t num)
Data bytes to DLC conversion.
void mcp251863_configure_object_reset(mcp251863_can_cfg_t *config)
Reset Configure object to reset values.
mcp251863_bus_diag_t bus_diagnostics
Definition: mcp251863.h:1863
err_t mcp251863_generic_write(mcp251863_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
MCP251863 data writing function.
Definition: mcp251863.h:1059
uint32_t pll_ready
Definition: mcp251863.h:1227
uint32_t unimplemented2
Definition: mcp251863.h:1655
err_t mcp251863_write_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_in, uint16_t n_bytes)
SPI Write Byte Array.
err_t mcp251863_bit_time_configure_data_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.
uint32_t sid
Definition: mcp251863.h:1012
uint32_t tx_not_full_ie
Definition: mcp251863.h:1175
uint32_t unimplemented4
Definition: mcp251863.h:1228
uint32_t clear_auto_sleep_on_match
Definition: mcp251863.h:1262
mcp251863_func_data_t func_data
Definition: mcp251863.h:1886
uint32_t n_ack_err
Definition: mcp251863.h:1734
uint32_t n_crc_error
Definition: mcp251863.h:1810
uint32_t tx_attempts
Definition: mcp251863.h:1188
uint32_t iso_crc_enable
Definition: mcp251863.h:1073
uint32_t n_tx_error_count
Definition: mcp251863.h:1788
MCP251863 Click Interrupt Flag Register.
Definition: mcp251863.h:1557
uint8_t * rxd
Definition: mcp251863.h:1834
uint32_t esi
Definition: mcp251863.h:934
uint32_t n_form_err
Definition: mcp251863.h:1735
uint32_t tx_priority
Definition: mcp251863.h:1187
uint32_t IVMIF
Definition: mcp251863.h:1548
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:949
uint32_t dlc_mismatch
Definition: mcp251863.h:1747
uint32_t time_stamp_enable
Definition: mcp251863.h:1387
mcp251863_mask_obj_id_t bf
Definition: mcp251863.h:1052
uint32_t sid11
Definition: mcp251863.h:918
uint32_t msid
Definition: mcp251863.h:1038
uint32_t unimplemented1
Definition: mcp251863.h:1738
uint32_t msid11
Definition: mcp251863.h:1040
uint32_t pay_load_size
Definition: mcp251863.h:1118
@ MCP251863_ERROR
Definition: mcp251863.h:1921
uint32_t request_op_mode
Definition: mcp251863.h:1087
uint32_t tseg1
Definition: mcp251863.h:1422
err_t mcp251863_transmit_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Disable.
uint32_t pay_load_size
Definition: mcp251863.h:1171
uint32_t uinc
Definition: mcp251863.h:1166
uint32_t pay_load_size
Definition: mcp251863.h:1349
uint32_t unimplemented3
Definition: mcp251863.h:1519
uint32_t d_bit1_err
Definition: mcp251863.h:1741
uint32_t unimplemented2
Definition: mcp251863.h:1441
uint32_t txie
Definition: mcp251863.h:1477
uint32_t lat1
Definition: mcp251863.h:1267
uint32_t osc_ready
Definition: mcp251863.h:1229
uint16_t word
Definition: mcp251863.h:1559
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1079
uint32_t buffer_pointer
Definition: mcp251863.h:1205
uint32_t d_bit0_err
Definition: mcp251863.h:1740
err_t mcp251863_receive_channel_reset(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Reset.
uint32_t fifo_size
Definition: mcp251863.h:1335
err_t mcp251863_configure(mcp251863_t *ctx, mcp251863_can_cfg_t *config)
CAN Control register configuration.
uint32_t tbcie
Definition: mcp251863.h:1479
err_t mcp251863_reset(mcp251863_t *ctx)
Reset function.
uint32_t SPICRCIF
Definition: mcp251863.h:1542
uint32_t pll_enable
Definition: mcp251863.h:1245
uint32_t exide
Definition: mcp251863.h:1015
err_t mcp251863_tef_event_overflow_clear(mcp251863_t *ctx)
Transmit Event FIFO Event Clear.
uint32_t word
Definition: mcp251863.h:1709
err_t mcp251863_read_byte_array_with_crc(mcp251863_t *ctx, bool from_ram, bool *crc_is_correct)
SPI Read Byte Array with CRC.
err_t mcp251863_bus_diagnostics_get(mcp251863_t *ctx, mcp251863_bus_diag_t *bus_diag)
Get Bus Diagnostic Registers: all data_ at once, since we want to keep them in synch.
pin_name_t cs
Definition: mcp251863.h:1900
uint32_t unimplemented2
Definition: mcp251863.h:1464
uint32_t word
Definition: mcp251863.h:1376
uint32_t tseg1
Definition: mcp251863.h:1403
uint8_t iso_crc_enable
Definition: mcp251863.h:881
uint32_t unimplemented2
Definition: mcp251863.h:1265
uint32_t tef_not_empty_if
Definition: mcp251863.h:1608
uint32_t unimplemented4
Definition: mcp251863.h:1521
uint32_t unimplemented2
Definition: mcp251863.h:1820
uint32_t unimplemented3
Definition: mcp251863.h:1140
err_t mcp251863_transmit_message(mcp251863_t *ctx, uint8_t *data_in, uint16_t data_len)
Message Transmit function.
uint32_t rtr_enable
Definition: mcp251863.h:1332
err_t mcp251863_tef_configure(mcp251863_t *ctx, mcp251863_tef_cfg_t *config)
Configure Transmit Event FIFO.
uint32_t spicrcie
Definition: mcp251863.h:1485
uint32_t unimplemented1
Definition: mcp251863.h:1162
uint32_t enable
Definition: mcp251863.h:1207
uint32_t unimplemented1
Definition: mcp251863.h:1016
MCP251863 Click CAN TEF Message Object.
Definition: mcp251863.h:995
err_t mcp251863_filter_mask_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_mask_obj_id_t *mask)
Filter Mask Configuration.
uint32_t tdc_offset
Definition: mcp251863.h:1440
uint32_t eccie
Definition: mcp251863.h:1484
uint32_t unimplemented2
Definition: mcp251863.h:1106
uint8_t remote_frame_req
Definition: mcp251863.h:893
uint32_t osc_ready
Definition: mcp251863.h:1721
uint32_t txbo_error
Definition: mcp251863.h:1812
uint32_t sclk_divide
Definition: mcp251863.h:1247
uint32_t tx_attempt_if
Definition: mcp251863.h:1663
uint32_t clk_out_divide
Definition: mcp251863.h:1225
uint32_t word
Definition: mcp251863.h:1061
err_t mcp251863_gpio_mode_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Mode.
uint32_t unimplemented4
Definition: mcp251863.h:1169
uint32_t pin_mode1
Definition: mcp251863.h:1274
digital_in_t int_pin
Definition: mcp251863.h:1878
uint32_t eid
Definition: mcp251863.h:917
err_t mcp251863_gpio_pin_read(mcp251863_t *ctx, uint8_t pos, uint8_t *state)
Input Pin Read.
uint32_t wake_up_filter_time
Definition: mcp251863.h:864
uint32_t eid
Definition: mcp251863.h:1013
MCP251863 Click Transmit Queue Status Register.
Definition: mcp251863.h:1624
void mcp251863_transmit_queue_configure_object_reset(mcp251863_tx_que_cfg_t *config)
Reset Transmit Queue Configure object to reset values.
MCP251863 Click CAN Message Object ID.
Definition: mcp251863.h:915
uint32_t sid11_enable
Definition: mcp251863.h:1444
uint32_t gpio0
Definition: mcp251863.h:1270
uint32_t mcp251863_dlc_to_data_bytes(uint8_t dlc)
DLC to number of actual data_bytes conversion.
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1318
uint32_t unimplemented1
Definition: mcp251863.h:1653
uint32_t unimplemented1
Definition: mcp251863.h:919
uint32_t fifo_size
Definition: mcp251863.h:1360
MCP251863 Click CAN Configure.
Definition: mcp251863.h:859
err_t mcp251863_receive_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Enable.
uint32_t system_error_to_listen_only
Definition: mcp251863.h:868
err_t mcp251863_receive_message_get(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_msg_obj_t *rx_obj)
Get Received Message.
uint32_t unimplemented4
Definition: mcp251863.h:1272
uint32_t fifo_size
Definition: mcp251863.h:1117
err_t mcp251863_tef_reset(mcp251863_t *ctx)
Transmit Event FIFO Reset.
err_t mcp251863_transmit_abort_all(mcp251863_t *ctx)
Abort All transmissions.
uint32_t icode
Definition: mcp251863.h:1514
err_t mcp251863_time_stamp_get(mcp251863_t *ctx, uint32_t *time_stamp)
Time Stamp Get.
mcp251863_can_cfg_t config
Definition: mcp251863.h:1856
uint32_t word
Definition: mcp251863.h:1027
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1314
MCP251863 Click Interrupt Flags.
Definition: mcp251863.h:1533
uint32_t d_form_err
Definition: mcp251863.h:1743
MCP251863 Click Interrupt Enables.
Definition: mcp251863.h:1476
MCP251863 Click CAN TX Message Object Control.
Definition: mcp251863.h:928
uint32_t word
Definition: mcp251863.h:1596
err_t mcp251863_read_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_out, uint16_t n_words)
SPI Read Word Array.
MCP251863 Click Oscillator Status.
Definition: mcp251863.h:1719
mcp251863_rx_msg_obj_t rx_obj
Definition: mcp251863.h:1860
uint32_t txq_enable
Definition: mcp251863.h:1321
MCP251863 Click CAN Transmit Queue Configure.
Definition: mcp251863.h:1345
uint32_t tefie
Definition: mcp251863.h:1481
mcp251863_tx_msg_obj_t tx_obj
Definition: mcp251863.h:1859
void mcp251863_receive_channel_configure_object_reset(mcp251863_rx_fifo_cfg_t *config)
Reset Receive Channel Configure object to reset value.
uint32_t unimplemented3
Definition: mcp251863.h:1108
uint32_t brs
Definition: mcp251863.h:932
err_t mcp251863_transmit_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint16_t *status)
Transmit Channel Status Get.
uint32_t RXIF
Definition: mcp251863.h:1535
err_t mcp251863_fifo_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *data_out)
FIFO Index Get.
pin_name_t stby
Definition: mcp251863.h:1903
uint32_t filter_hit
Definition: mcp251863.h:1516
MCP251863 Click CAN Message Configuration.
Definition: mcp251863.h:880
uint32_t ide
Definition: mcp251863.h:930
void mcp251863_transmit_channel_configure_object_reset(mcp251863_tx_fifo_cfg_t *config)
Reset Transmit Channel Configure object to reset values.
uint32_t txd_num_bytes
Definition: mcp251863.h:1837
err_t mcp251863_gpio_direction_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Direction.
uint32_t fifo_size
Definition: mcp251863.h:1143
void mcp251863_cfg_setup(mcp251863_cfg_t *cfg)
MCP251863 configuration object setup function.
err_t mcp251863_filter_enable(mcp251863_t *ctx, uint8_t filter)
Filter Enable.
err_t mcp251863_ecc_parity_set(mcp251863_t *ctx, uint8_t parity)
Set ECC Parity.
uint32_t iso_crc_enable
Definition: mcp251863.h:861
uint32_t mide
Definition: mcp251863.h:1041
uint32_t tx_error_count
Definition: mcp251863.h:1587
uint32_t rxovie
Definition: mcp251863.h:1487
uint32_t unimplemented1
Definition: mcp251863.h:1627
err_t mcp251863_default_cfg(mcp251863_t *ctx)
MCP251863 default configuration function.
MCP251863 Click Transmitter Delay Compensation Register.
Definition: mcp251863.h:1436
MCP251863 Click CAN Filter Object ID.
Definition: mcp251863.h:1011
uint32_t unimplemented3
Definition: mcp251863.h:1635
uint32_t wakie
Definition: mcp251863.h:1490
uint8_t store_in_tef
Definition: mcp251863.h:882
uint32_t ECCIF
Definition: mcp251863.h:1541
uint32_t tef_ov_if
Definition: mcp251863.h:1611
uint32_t txq_enable
Definition: mcp251863.h:870
uint32_t unimplemented2
Definition: mcp251863.h:1421
uint32_t unimplemented1
Definition: mcp251863.h:1612
uint32_t d_crc_error
Definition: mcp251863.h:1818
uint32_t unimplemented3
Definition: mcp251863.h:1707
uint32_t unimplemented3
Definition: mcp251863.h:1167
err_t mcp251863_receive_message(mcp251863_t *ctx, uint8_t *data_out, uint16_t *data_len)
Message Receive function.
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1571
uint32_t tx_half_full_if
Definition: mcp251863.h:1660
uint8_t rx_fifo_size
Definition: mcp251863.h:886
uint32_t unimplemented2
Definition: mcp251863.h:1078
MCP251863 Click Nominal Bit Time Configuration Register.
Definition: mcp251863.h:1397
uint32_t rx_full_ie
Definition: mcp251863.h:1160
MCP251863 Click CAN Configure.
Definition: mcp251863.h:1310
uint8_t n_tec
Definition: mcp251863.h:1758
mcp251863_return_value_t
MCP251863 Click return value data.
Definition: mcp251863.h:1919
uint32_t word
Definition: mcp251863.h:1637
uint32_t hvdetsel
Definition: mcp251863.h:1269
uint32_t extended_id
Definition: mcp251863.h:889
uint32_t tx_attempt_if
Definition: mcp251863.h:1630
uint32_t n_bit1_err
Definition: mcp251863.h:1733
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:997
err_t mcp251863_transmit_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_fifo_cfg_t *config)
Configure Transmit FIFO.
uint32_t unimplemented4
Definition: mcp251863.h:1113
uint32_t unimplemented2
Definition: mcp251863.h:1402
MCP251863 Click Interrupt Register.
Definition: mcp251863.h:1569
uint32_t int_pin_open_drain
Definition: mcp251863.h:1278
err_t mcp251863_ram_init(mcp251863_t *ctx, uint8_t rx_data)
Initialize RAM.
uint32_t secif
Definition: mcp251863.h:1703
uint32_t tx_error_state_bus_off
Definition: mcp251863.h:1593
uint32_t tbc_prescaler
Definition: mcp251863.h:1460
uint32_t tx_code
Definition: mcp251863.h:1518
uint8_t mcp251863_id_t
MCP251863 Click Module ID.
Definition: mcp251863.h:902
uint32_t unimplemented1
Definition: mcp251863.h:1702
uint32_t rx_not_empty_if
Definition: mcp251863.h:1649
uint32_t rx_code
Definition: mcp251863.h:1520
err_t mcp251863_crc_event_get(mcp251863_t *ctx, uint8_t *flags)
CRC Event Get.
uint8_t * txd
Definition: mcp251863.h:1836
err_t mcp251863_crc_event_clear(mcp251863_t *ctx, uint8_t flags)
CRC Event Clear.
mcp251863_filt_obj_t f_obj
Definition: mcp251863.h:1861
pin_name_t chip_select
Definition: mcp251863.h:1883
uint32_t unimplemented3
Definition: mcp251863.h:1443
uint32_t word
Definition: mcp251863.h:1523
uint32_t word
Definition: mcp251863.h:1091
pin_name_t int_pin
Definition: mcp251863.h:1905
uint32_t unimplemented2
Definition: mcp251863.h:1629
uint32_t tx_error
Definition: mcp251863.h:1664
uint32_t tef_half_full_if
Definition: mcp251863.h:1609
uint32_t d_stuff_error
Definition: mcp251863.h:1817
uint32_t WAKIF
Definition: mcp251863.h:1547
err_t mcp251863_write_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_in, uint16_t n_words)
SPI Write Word Array.
err_t mcp251863_gpio_clock_output_configure(mcp251863_t *ctx, uint8_t mode)
Configure CLKO Pin.
uint8_t seq
Definition: mcp251863.h:894
err_t mcp251863_time_stamp_mode_configure(mcp251863_t *ctx, uint8_t mode)
Time Stamp Mode Configure.
void mcp251863_tef_configure_object_reset(mcp251863_tef_cfg_t *config)
Reset TefConfigure object to reset value.
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1832
uint32_t error_free_msg_count
Definition: mcp251863.h:1804
MCP251863 Click FIFO Status Register.
Definition: mcp251863.h:1647
uint32_t sid11
Definition: mcp251863.h:1014
uint32_t edge_filter_enable
Definition: mcp251863.h:1445
uint32_t tx_priority
Definition: mcp251863.h:1114
err_t mcp251863_crc_event_disable(mcp251863_t *ctx, uint8_t flags)
CRC Event Disnable.
uint8_t rx_flags
Definition: mcp251863.h:1849
uint32_t sclk_ready
Definition: mcp251863.h:1231
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1163
uint32_t SERRIF
Definition: mcp251863.h:1545
uint32_t word
Definition: mcp251863.h:1822
err_t mcp251863_transmit_event_attempt_get(mcp251863_t *ctx, uint32_t *txatif)
Get pending TXATIF of all transmit FIFOs.
uint32_t tx_aborted
Definition: mcp251863.h:1666
uint32_t txq_enable
Definition: mcp251863.h:1085
uint32_t parity
Definition: mcp251863.h:1297
uint32_t unimplemented2
Definition: mcp251863.h:1517
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1846
uint32_t tx_priority
Definition: mcp251863.h:1346
uint32_t crcerrif
Definition: mcp251863.h:1683
err_t mcp251863_bus_diagnostics_clear(mcp251863_t *ctx)
Clear Bus Diagnostic Registers.
uint32_t rtr
Definition: mcp251863.h:964
uint32_t store_in_tef
Definition: mcp251863.h:1320
uint32_t store_in_tef
Definition: mcp251863.h:1084
uint32_t time_stamp_enable
Definition: mcp251863.h:1137
uint32_t rx_not_empty_ie
Definition: mcp251863.h:1158
err_t mcp251863_bit_time_configure_nominal_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 40MHz system clock.
uint8_t switch_bit_rate
Definition: mcp251863.h:891
uint32_t unimplemented1
Definition: mcp251863.h:1221
uint32_t op_mode
Definition: mcp251863.h:1086
uint32_t abort_all_tx
Definition: mcp251863.h:1088
uint32_t tris1
Definition: mcp251863.h:1260
uint32_t tdc_value
Definition: mcp251863.h:1438
err_t mcp251863_operation_mode_select(mcp251863_t *ctx, uint8_t op_mode)
Select Operation Mode.
MCP251863 Click CAN Transmit Event FIFO Configure.
Definition: mcp251863.h:1386
err_t mcp251863_receive_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Receive FIFO Event Get.
uint32_t dlc
Definition: mcp251863.h:962
uint32_t tx_empty_if
Definition: mcp251863.h:1661
uint8_t tec
Definition: mcp251863.h:1851
uint32_t tef_full_if
Definition: mcp251863.h:1610
err_t mcp251863_gpio_standby_control_disable(mcp251863_t *ctx)
Disable Transceiver Standby Control.
uint32_t cerrie
Definition: mcp251863.h:1489
uint32_t word
Definition: mcp251863.h:1426
mcp251863_int_en_t ie
Definition: mcp251863.h:1572
uint32_t unimplemented6
Definition: mcp251863.h:1232
uint32_t tx_enable
Definition: mcp251863.h:1109
uint32_t unimplemented5
Definition: mcp251863.h:1275
err_t mcp251863_tef_event_get(mcp251863_t *ctx, uint8_t *flags)
Transmit Event FIFO Event Get.
uint32_t tx_empty_if
Definition: mcp251863.h:1628
uint32_t TEFIF
Definition: mcp251863.h:1538
uint32_t n_rx_error_count
Definition: mcp251863.h:1787
uint32_t unimplemented1
Definition: mcp251863.h:1136
err_t mcp251863_time_stamp_prescaler_set(mcp251863_t *ctx, uint16_t time_stamp)
Time Stamp Prescaler Set.
uint32_t word
Definition: mcp251863.h:1448
err_t mcp251863_module_event_get(mcp251863_t *ctx, uint16_t *flags)
Module Event Get.
uint32_t pay_load_size
Definition: mcp251863.h:1361
pin_name_t mosi
Definition: mcp251863.h:1898
err_t mcp251863_tef_event_enable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Enable.
uint8_t selected_bit_time
Definition: mcp251863.h:1847
uint32_t unimplemented1
Definition: mcp251863.h:1042
uint32_t unimplemented2
Definition: mcp251863.h:1742
uint32_t tdc_mode
Definition: mcp251863.h:1442
uint32_t fifo_size
Definition: mcp251863.h:1388
uint32_t unimplemented2
Definition: mcp251863.h:1164
uint32_t gpio1
Definition: mcp251863.h:1271
uint32_t TXATIF
Definition: mcp251863.h:1543
uint32_t fifo_index
Definition: mcp251863.h:1654
uint32_t TXIF
Definition: mcp251863.h:1534
uint32_t word
Definition: mcp251863.h:1193
err_t mcp251863_generic_read(mcp251863_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
MCP251863 data reading function.
MCP251863 Click CAN Control Register.
Definition: mcp251863.h:1070
uint32_t time_stamp_eof
Definition: mcp251863.h:1463
uint32_t tx_request
Definition: mcp251863.h:1184
uint32_t sid
Definition: mcp251863.h:916
uint32_t unimplemented1
Definition: mcp251863.h:1261
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1632
err_t mcp251863_ecc_event_get(mcp251863_t *ctx, uint8_t *flags)
ECC Event Get.
uint32_t tris0
Definition: mcp251863.h:1259
uint32_t word
Definition: mcp251863.h:1670
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1665
uint8_t byte
Definition: mcp251863.h:1209
err_t mcp251863_filter_disable(mcp251863_t *ctx, uint8_t filter)
Filter Disable.
uint8_t d_tec
Definition: mcp251863.h:1760
uint32_t tx_not_full_if
Definition: mcp251863.h:1626
uint32_t modie
Definition: mcp251863.h:1480
uint8_t d_rec
Definition: mcp251863.h:1759
uint32_t d_net_filter_count
Definition: mcp251863.h:860
uint32_t rtr
Definition: mcp251863.h:931
err_t mcp251863_receive_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Disable.
uint32_t n_crc_err
Definition: mcp251863.h:1737
uint32_t MODIF
Definition: mcp251863.h:1537
uint32_t d_net_filter_count
Definition: mcp251863.h:1311
MCP251863 Click CAN RX Message Object Control.
Definition: mcp251863.h:961
uint16_t word
Definition: mcp251863.h:1502
uint32_t xcr_stby_enable
Definition: mcp251863.h:1264
uint32_t unimplemented3
Definition: mcp251863.h:1080
err_t mcp251863_module_event_disable(mcp251863_t *ctx, uint16_t flags)
Module Event Disable.
uint32_t tx_aborted
Definition: mcp251863.h:1633
err_t mcp251863_receive_event_get(mcp251863_t *ctx, uint32_t *rxif)
Get pending interrupts of all receive FIFOs.
uint32_t wake_up_filter_time
Definition: mcp251863.h:1315
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:981
uint32_t user_address
Definition: mcp251863.h:1373
err_t mcp251863_module_event_rx_code_get(mcp251863_t *ctx, uint8_t *rx_code)
Get RX Code.
uint32_t dlc
Definition: mcp251863.h:929
uint32_t unimplemented1
Definition: mcp251863.h:1296
mcp251863_filt_obj_id_t bf
Definition: mcp251863.h:1026
uint32_t n_bit1_error
Definition: mcp251863.h:1806
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:862
uint32_t crc
Definition: mcp251863.h:1682
uint32_t rx_over_flow_ie
Definition: mcp251863.h:1161
uint32_t protocol_exception_event_disable
Definition: mcp251863.h:1074
uint32_t rx_full_if
Definition: mcp251863.h:1651
err_t mcp251863_transmit_channel_reset(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Reset.
uint32_t ide
Definition: mcp251863.h:963
err_t mcp251863_crc_value_get(mcp251863_t *ctx, uint16_t *crc)
Get CRC Value from device.
pin_name_t clk
Definition: mcp251863.h:1904
uint32_t ferrie
Definition: mcp251863.h:1687
uint32_t pay_load_size
Definition: mcp251863.h:1336
mcp251863_int_en_t ie
Definition: mcp251863.h:1501
uint32_t tbc_enable
Definition: mcp251863.h:1462
mcp251863_tx_fifo_cfg_t tx_config
Definition: mcp251863.h:1857
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:866
spi_master_mode_t spi_mode
Definition: mcp251863.h:1909
uint32_t word
Definition: mcp251863.h:1281
MCP251863 Click context object.
Definition: mcp251863.h:1872
err_t mcp251863_gpio_pin_set(mcp251863_t *ctx, uint8_t pos, uint8_t latch)
GPIO Output Pin Set.
err_t mcp251863_receive_channel_event_overflow_clear(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Event Clear.
MCP251863 Click ECC Control Register.
Definition: mcp251863.h:1291
MCP251863 Click CAN Bus Diagnostic flags.
Definition: mcp251863.h:1731
err_t mcp251863_tef_event_disable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Disable.
uint32_t teffulie
Definition: mcp251863.h:1134
uint8_t tx_fifo_size
Definition: mcp251863.h:883
uint32_t unimplemented1
Definition: mcp251863.h:1811
err_t mcp251863_module_event_enable(mcp251863_t *ctx, uint16_t flags)
Module Event Enable.
uint32_t unimplemented5
Definition: mcp251863.h:1116
err_t mcp251863_receive_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_fifo_cfg_t *config)
Configure Receive FIFO.
uint32_t rx_half_full_if
Definition: mcp251863.h:1650
uint32_t txatie
Definition: mcp251863.h:1486
err_t mcp251863_write_word_safe(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI RAM Write Word Safe.
uint32_t pll_ready
Definition: mcp251863.h:1720
uint32_t tx_half_full_ie
Definition: mcp251863.h:1176
err_t mcp251863_init(mcp251863_t *ctx, mcp251863_cfg_t *cfg)
MCP251863 initialization function.
uint32_t tx_attempts
Definition: mcp251863.h:1334
err_t mcp251863_error_count_state_get(mcp251863_t *ctx, uint8_t *tec, uint8_t *rec, uint8_t *flags)
Error Counts and Error State Get.
err_t mcp251863_tef_message_get(mcp251863_t *ctx, mcp251863_tef_msg_obj_t *tef_obj)
Get Transmit Event FIFO Message.
uint8_t op_mode
Definition: mcp251863.h:1853
err_t mcp251863_write_byte_array_with_crc(mcp251863_t *ctx, bool from_ram)
SPI Write Byte Array with CRC.
err_t mcp251863_ecc_event_clear(mcp251863_t *ctx, uint8_t flags)
ECC Event Clear.
MCP251863 Click CAN BUS DIAGNOSTICS.
Definition: mcp251863.h:1769
uint32_t tx_attempt_ie
Definition: mcp251863.h:1107
uint8_t fd_frame
Definition: mcp251863.h:890
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1316
MCP251863 Click CAN TX Message Object.
Definition: mcp251863.h:945
uint32_t unimplemented1
Definition: mcp251863.h:1104
uint32_t word
Definition: mcp251863.h:1406
MCP251863 Click CAN RX Message Object.
Definition: mcp251863.h:979
uint32_t unimplemented1
Definition: mcp251863.h:1594
uint32_t brp
Definition: mcp251863.h:1404
uint32_t unimplemented1
Definition: mcp251863.h:1539
MCP251863 Click Filter Object Register.
Definition: mcp251863.h:1025
err_t mcp251863_read_byte(mcp251863_t *ctx, uint16_t address, uint8_t *data_out)
SPI Read Byte function.
uint32_t unimplemented1
Definition: mcp251863.h:1075
err_t mcp251863_tef_update(mcp251863_t *ctx)
Transmit Event FIFO Update.
uint32_t freset
Definition: mcp251863.h:1168
uint32_t word
Definition: mcp251863.h:1053
err_t mcp251863_receive_event_overflow_get(mcp251863_t *ctx, uint32_t *rxovif)
Get pending RXOVIF of all receive FIFOs.
err_t mcp251863_crc_event_enable(mcp251863_t *ctx, uint8_t flags)
CRC Event Enable.
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:948
uint32_t d_stuff_err
Definition: mcp251863.h:1744
uint32_t rx_error_state_passive
Definition: mcp251863.h:1591
uint32_t serrie
Definition: mcp251863.h:1488
err_t mcp251863_receive_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint8_t *status)
Receive Channel Status Get.
MCP251863 Click CRC Regsiter.
Definition: mcp251863.h:1680
uint32_t tx_can_open_drain
Definition: mcp251863.h:1276
uint32_t store_in_tef
Definition: mcp251863.h:869
err_t mcp251863_ecc_disable(mcp251863_t *ctx)
Disable ECC.
MCP251863 Click CAN Bus Diagnostic Error Counts.
Definition: mcp251863.h:1756
uint8_t tx_pay_load_size
Definition: mcp251863.h:884
err_t mcp251863_module_event_filter_hit_get(mcp251863_t *ctx, uint8_t *filter_hit)
Get Filter Hit.
uint32_t dedif
Definition: mcp251863.h:1704
mcp251863_bus_diag_flags_t flag
Definition: mcp251863.h:1773
uint32_t tx_priority
Definition: mcp251863.h:1333
err_t mcp251863_error_state_get(mcp251863_t *ctx, uint8_t *flags)
Error State Get.
mcp251863_data_t glb_data
Definition: mcp251863.h:1885
uint32_t n_bit0_error
Definition: mcp251863.h:1805
uint32_t d_rx_error_count
Definition: mcp251863.h:1789
uint16_t n_bytes
Definition: mcp251863.h:1835
uint8_t error_flags
Definition: mcp251863.h:1850
err_t mcp251863_ecc_parity_get(mcp251863_t *ctx, uint8_t *parity)
Get ECC Parity.
uint32_t pin_mode0
Definition: mcp251863.h:1273
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1322
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1558
uint32_t d_ack_error
Definition: mcp251863.h:1815
err_t mcp251863_transmit_queue_configure(mcp251863_t *ctx, mcp251863_tx_que_cfg_t *config)
Configure Transmit Queue.
uint32_t unimplemented6
Definition: mcp251863.h:1279
uint32_t rtr_enable
Definition: mcp251863.h:1181
uint16_t standard_id
Definition: mcp251863.h:888
MCP251863 Click Diagnostic register 0.
Definition: mcp251863.h:1785
uint32_t iso_crc_enable
Definition: mcp251863.h:1312
uint32_t unimplemented5
Definition: mcp251863.h:1230
err_t mcp251863_filter_to_fifo_link(mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable)
Link Filter to FIFO.
digital_in_t clk
Definition: mcp251863.h:1877
uint32_t error_state_warning
Definition: mcp251863.h:1588
uint32_t unimplemented5
Definition: mcp251863.h:1144
err_t mcp251863_oscillator_control_set(mcp251863_t *ctx, mcp251863_div_ctl_t ctrl)
Set Oscillator Control.
uint32_t word
Definition: mcp251863.h:1614
uint16_t error_free_msg_count
Definition: mcp251863.h:1772
uint32_t unimplemented4
Definition: mcp251863.h:1446
uint32_t d_bit0_error
Definition: mcp251863.h:1813
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:1313
uint32_t tx_band_width_sharing
Definition: mcp251863.h:871
pin_name_t miso
Definition: mcp251863.h:1897
uint32_t tx_request
Definition: mcp251863.h:1111
MCP251863 Click Diagnostic register 1.
Definition: mcp251863.h:1802
err_t mcp251863_gpio_standby_control_enable(mcp251863_t *ctx)
Enable Transceiver Standby Control.
uint32_t unimplemented1
Definition: mcp251863.h:968
err_t mcp251863_read_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_out, uint16_t n_bytes)
SPI Read Byte Array.
err_t mcp251863_bit_time_configure(mcp251863_t *ctx, uint8_t bit_time, uint8_t clk)
Configure Bit Time registers (based on CAN clock speed).
uint32_t tefovie
Definition: mcp251863.h:1135
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:865
uint32_t tx_error
Definition: mcp251863.h:1631
uint32_t n_stuff_error
Definition: mcp251863.h:1809
uint32_t d_tx_error_count
Definition: mcp251863.h:1790
err_t mcp251863_module_event_clear(mcp251863_t *ctx, uint16_t flags)
Module Event Clear.
spi_master_chip_select_polarity_t cs_polarity
Definition: mcp251863.h:1910
uint32_t secie
Definition: mcp251863.h:1294
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1359
uint32_t tx_id
Definition: mcp251863.h:1854
err_t mcp251863_error_count_receive_get(mcp251863_t *ctx, uint8_t *rec)
Receive Error Count Get.
err_t mcp251863_write_byte(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI Write Byte.
uint32_t auto_sleep_enable
Definition: mcp251863.h:1263
err_t mcp251863_gpio_interrupt_pins_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain Interrupts.
uint32_t crcerrie
Definition: mcp251863.h:1686
uint32_t fifo_size
Definition: mcp251863.h:1348
uint8_t tx_priority
Definition: mcp251863.h:885
uint32_t uinc
Definition: mcp251863.h:1139
err_t mcp251863_transmit_channel_load(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_msg_obj_t *tx_obj, bool flush)
TX Channel Load.
uint32_t ferrif
Definition: mcp251863.h:1684
err_t mcp251863_bit_time_configure_nominal_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.