mcp251863  2.0.0.0
mcp251863.h
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22 
28 #ifndef MCP251863_H
29 #define MCP251863_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "mikrosdk_version.h"
36 
37 #ifdef __GNUC__
38 #if mikroSDK_GET_VERSION < 20800ul
39 #include "rcu_delays.h"
40 #else
41 #include "delays.h"
42 #endif
43 #endif
44 
45 #include "drv_digital_out.h"
46 #include "drv_digital_in.h"
47 #include "drv_spi_master.h"
48 #include "spi_specifics.h"
49 
60 #define MCP251863
61 
66 //#define REV_A
67 #define REV_B
68 
69 #ifdef REV_A
70  #define FIXED_FILTER_ADDRESS
71 #endif
72 
77 #ifndef FPGA
78  #define MCP251863_FIFO_08TO15_IMPLEMENTED
79  #define MCP251863_FIFO_16TO31_IMPLEMENTED
80 #endif
81 
86 #ifndef FPGA
87  #define MCP251863_FILT_08TO15_IMPLEMENTED
88  #define MCP251863_FILT_16TO31_IMPLEMENTED
89 #endif
90 
95 #ifdef MCP2520FD
96  #define CAN_INTERNAL_OSC_PRESENT
97 #endif
98 
103 #ifdef REV_B
104  #define CAN_RESTRICTED_MODE_PRESENT
105 #endif
106 
111 #ifdef REV_B
112  #define CAN_TXQUEUE_IMPLEMENTED
113 #endif
114 
120 #ifdef REV_A
121  #define USERADDRESS_TIMES_FOUR
122 #endif
123 
124 #ifdef MCP251863
125  #define N_MCP2518_CTRL_REGS 5
126 #endif
127 
128 #define MCP251863_MAX_TXQUEUE_ATTEMPTS 50
129 #define MCP251863_TX_REQUEST_ID 0x300
130 #define MCP251863_TX_RESPONSE_ID 0x301
131 
132 #define MCP251863_CRCBASE 0xFFFF
133 #define MCP251863_CRCUPPER 1
134 #define MCP251863_DRV_CANFDSPI_INDEX_0 0
135 #define MCP251863_SPI_DEFAULT_BUFFER_LENGTH 96
136 
137 #define MCP251863_ISO_CRC 1
138 
139 #define MCP251863_MAX_MSG_SIZE 76
140 
141 #define MCP251863_MAX_DATA_BYTES 64
142 
143 #define MCP251863_INS_RESET 0x00
144 #define MCP251863_INS_READ 0x03
145 #define MCP251863_INS_READ_CRC 0x0B
146 #define MCP251863_INS_WRITE 0x02
147 #define MCP251863_INS_WRITE_CRC 0x0A
148 #define MCP251863_INS_WRITE_SAFE 0x0C
149 
150 
151 #define MCP251863_FIFO_OFFSET ( 3 * 4 )
152 #define MCP251863_FILTER_OFFSET ( 2 * 4 )
153 
154 #ifdef CAN_TXQUEUE_IMPLEMENTED
155  #define MCP251863_REG_CITXQCON 0x050
156  #define MCP251863_REG_CITXQSTA 0x054
157  #define MCP251863_REG_CITXQUA 0x058
158 #endif
159 
160 #ifdef FIXED_FILTER_ADDRESS
161  #define MCP251863_REG_CIFLTCON 0x1D0
162  #define MCP251863_REG_CIFLTOBJ 0x1F0
163  #define MCP251863_REG_CIMASK 0x1F4
164 #else
165  #define MCP251863_REG_CIFLTCON ( MCP251863_REG_CIFIFOCON + ( MCP251863_FIFO_OFFSET * MCP251863_FIFO_TOTAL_CHANNELS ) )
166  #define MCP251863_REG_CIFLTOBJ ( MCP251863_REG_CIFLTCON + MCP251863_FIFO_TOTAL_CHANNELS )
167  #define MCP251863_REG_CIMASK ( MCP251863_REG_CIFLTOBJ + 4 )
168 #endif
169 
170 #define MCP251863_REG_OSC 0xE00
171 #define MCP251863_REG_IOCON 0xE04
172 #define MCP251863_REG_CRC 0xE08
173 #define MCP251863_REG_ECCCON 0xE0C
174 #define MCP251863_REG_ECCSTA 0xE10
175 
176 #define MCP251863_RAM_SIZE 2048
177 #define MCP251863_RAMADDR_START 0x400
178 #define MCP251863_RAMADDR_END ( MCP251863_RAMADDR_START + MCP251863_RAM_SIZE )
179 
180 #define MCP251863_LOW_POWER_MODE_EN 0x08
181 #define MCP251863_LOW_POWER_MODE_DIS 0x00
182 #define MCP251863_WAKEUP_INTERR_EN 0x40
183 
184 #define MCP251863_REG_CICON 0x000
185 #define MCP251863_REG_CINBTCFG 0x004
186 #define MCP251863_REG_CIDBTCFG 0x008
187 #define MCP251863_REG_CITDC 0x00C
188 
189 #define MCP251863_REG_CITBC 0x010
190 #define MCP251863_REG_CITSCON 0x014
191 #define MCP251863_REG_CIVEC 0x018
192 #define MCP251863_REG_CIINT 0x01C
193 #define MCP251863_REG_CIINTFLAG MCP251863_REG_CIINT
194 #define MCP251863_REG_CIINTENABLE ( MCP251863_REG_CIINT + 2 )
195 
196 #define MCP251863_REG_CIRXIF 0x020
197 #define MCP251863_REG_CITXIF 0x024
198 #define MCP251863_REG_CIRXOVIF 0x028
199 #define MCP251863_REG_CITXATIF 0x02C
200 
201 #define MCP251863_REG_CITXREQ 0x030
202 #define MCP251863_REG_CITREC 0x034
203 #define MCP251863_REG_CIBDIAG0 0x038
204 #define MCP251863_REG_CIBDIAG1 0x03C
205 
206 #define MCP251863_REG_CITEFCON 0x040
207 #define MCP251863_REG_CITEFSTA 0x044
208 #define MCP251863_REG_CITEFUA 0x048
209 #define MCP251863_REG_CIFIFOBA 0x04C
210 
211 #define MCP251863_REG_CIFIFOCON 0x050
212 #define MCP251863_REG_CIFIFOSTA 0x054
213 #define MCP251863_REG_CIFIFOUA 0x058
214  // mcp251863_reg
226 
246 #define MCP251863_FIFO_CH0 0
247 #define MCP251863_FIFO_CH1 1
248 #define MCP251863_FIFO_CH2 2
249 #define MCP251863_FIFO_CH3 3
250 #define MCP251863_FIFO_CH4 4
251 #define MCP251863_FIFO_CH5 5
252 #define MCP251863_FIFO_CH6 6
253 #define MCP251863_FIFO_CH7 7
254 
255 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
256  #define MCP251863_FIFO_CH8 8
257  #define MCP251863_FIFO_CH9 9
258  #define MCP251863_FIFO_CH10 10
259  #define MCP251863_FIFO_CH11 11
260  #define MCP251863_FIFO_CH12 12
261  #define MCP251863_FIFO_CH13 13
262  #define MCP251863_FIFO_CH14 14
263  #define MCP251863_FIFO_CH15 15
264 #endif
265 
266 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
267  #define MCP251863_FIFO_CH16 16
268  #define MCP251863_FIFO_CH17 17
269  #define MCP251863_FIFO_CH18 18
270  #define MCP251863_FIFO_CH19 19
271  #define MCP251863_FIFO_CH20 20
272  #define MCP251863_FIFO_CH21 21
273  #define MCP251863_FIFO_CH22 22
274  #define MCP251863_FIFO_CH23 23
275  #define MCP251863_FIFO_CH24 24
276  #define MCP251863_FIFO_CH25 25
277  #define MCP251863_FIFO_CH26 26
278  #define MCP251863_FIFO_CH27 27
279  #define MCP251863_FIFO_CH28 28
280  #define MCP251863_FIFO_CH29 29
281  #define MCP251863_FIFO_CH30 30
282  #define MCP251863_FIFO_CH31 31
283 #endif
284 
285 
286 #define MCP251863_FIFO_TOTAL_CHANNELS 32
287 
288 #ifdef CAN_TXQUEUE_IMPLEMENTED
289  #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1
290  #define CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0
291 #else
292  #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH0
293 #endif
294 
299 #define MCP251863_FILT0 0
300 #define MCP251863_FILT1 1
301 #define MCP251863_FILT2 2
302 #define MCP251863_FILT3 3
303 #define MCP251863_FILT4 4
304 #define MCP251863_FILT5 5
305 #define MCP251863_FILT6 6
306 #define MCP251863_FILT7 7
307 
308 #ifdef MCP251863_FILT_08TO15_IMPLEMENTED
309  #define MCP251863_FILT8 8
310  #define MCP251863_FILT9 9
311  #define MCP251863_FILT10 10
312  #define MCP251863_FILT11 11
313  #define MCP251863_FILT12 12
314  #define MCP251863_FILT13 13
315  #define MCP251863_FILT14 14
316  #define MCP251863_FILT15 15
317 #endif
318 
319 #ifdef MCP251863_FILT_16TO31_IMPLEMENTED
320  #define MCP251863_FILT16 16
321  #define MCP251863_FILT17 17
322  #define MCP251863_FILT18 18
323  #define MCP251863_FILT19 19
324  #define MCP251863_FILT20 20
325  #define MCP251863_FILT21 21
326  #define MCP251863_FILT22 22
327  #define MCP251863_FILT23 23
328  #define MCP251863_FILT24 24
329  #define MCP251863_FILT25 25
330  #define MCP251863_FILT26 26
331  #define MCP251863_FILT27 27
332  #define MCP251863_FILT28 28
333  #define MCP251863_FILT29 29
334  #define MCP251863_FILT30 30
335  #define MCP251863_FILT31 31
336 #endif
337 
338 #define MCP251863_FILT_TOTAL 32
339 
344 #define MCP251863_NORMAL_MODE 0x00
345 #define MCP251863_SLEEP_MODE 0x01
346 #define MCP251863_INT_LOOP_MODE 0x02
347 #define MCP251863_LISTEN_ONLY_MODE 0x03
348 #define MCP251863_CONFIG_MODE 0x04
349 #define MCP251863_EXT_LOOP_MODE 0x05
350 #define MCP251863_CLASSIC_MODE 0x06
351 #define MCP251863_RESTRICT_MODE 0x07
352 #define MCP251863_INVALID_MODE 0xFF
353 
358 #define MCP251863_TXBWS_NO_DELAY 0
359 #define MCP251863_TXBWS_2 1
360 #define MCP251863_TXBWS_4 2
361 #define MCP251863_TXBWS_8 3
362 #define MCP251863_TXBWS_16 4
363 #define MCP251863_TXBWS_32 5
364 #define MCP251863_TXBWS_64 6
365 #define MCP251863_TXBWS_128 7
366 #define MCP251863_TXBWS_256 8
367 #define MCP251863_TXBWS_512 9
368 #define MCP251863_TXBWS_1024 10
369 #define MCP251863_TXBWS_2048 11
370 #define MCP251863_TXBWS_4096 12
371 
376 #define MCP251863_WFT00 0
377 #define MCP251863_WFT01 1
378 #define MCP251863_WFT10 2
379 #define MCP251863_WFT11 3
380 
385 #define MCP251863_DNET_FILT_DISABLE 0
386 #define MCP251863_DNET_FILT_SIZE_1_BIT 1
387 #define MCP251863_DNET_FILT_SIZE_2_BIT 2
388 #define MCP251863_DNET_FILT_SIZE_3_BIT 3
389 #define MCP251863_DNET_FILT_SIZE_4_BIT 4
390 #define MCP251863_DNET_FILT_SIZE_5_BIT 5
391 #define MCP251863_DNET_FILT_SIZE_6_BIT 6
392 #define MCP251863_DNET_FILT_SIZE_7_BIT 7
393 #define MCP251863_DNET_FILT_SIZE_8_BIT 8
394 #define MCP251863_DNET_FILT_SIZE_9_BIT 9
395 #define MCP251863_DNET_FILT_SIZE_10_BIT 10
396 #define MCP251863_DNET_FILT_SIZE_11_BIT 11
397 #define MCP251863_DNET_FILT_SIZE_12_BIT 12
398 #define MCP251863_DNET_FILT_SIZE_13_BIT 13
399 #define MCP251863_DNET_FILT_SIZE_14_BIT 14
400 #define MCP251863_DNET_FILT_SIZE_15_BIT 15
401 #define MCP251863_DNET_FILT_SIZE_16_BIT 16
402 #define MCP251863_DNET_FILT_SIZE_17_BIT 17
403 #define MCP251863_DNET_FILT_SIZE_18_BIT 18
404 
409 #define MCP251863_PLSIZE_8 0
410 #define MCP251863_PLSIZE_12 1
411 #define MCP251863_PLSIZE_16 2
412 #define MCP251863_PLSIZE_20 3
413 #define MCP251863_PLSIZE_24 4
414 #define MCP251863_PLSIZE_32 5
415 #define MCP251863_PLSIZE_48 6
416 #define MCP251863_PLSIZE_64 7
417 
422 #define MCP251863_DLC_0 0
423 #define MCP251863_DLC_1 1
424 #define MCP251863_DLC_2 2
425 #define MCP251863_DLC_3 3
426 #define MCP251863_DLC_4 4
427 #define MCP251863_DLC_5 5
428 #define MCP251863_DLC_6 6
429 #define MCP251863_DLC_7 7
430 #define MCP251863_DLC_8 8
431 #define MCP251863_DLC_12 9
432 #define MCP251863_DLC_16 10
433 #define MCP251863_DLC_20 11
434 #define MCP251863_DLC_24 12
435 #define MCP251863_DLC_32 13
436 #define MCP251863_DLC_48 14
437 #define MCP251863_DLC_64 15
438 
443 #define MCP251863_RX_FIFO_EMPTY 0
444 #define MCP251863_RX_FIFO_STATUS_MASK 0x0F
445 #define MCP251863_RX_FIFO_NOT_EMPTY 0x01
446 #define MCP251863_RX_FIFO_HALF_FULL 0x02
447 #define MCP251863_RX_FIFO_FULL 0x04
448 #define MCP251863_RX_FIFO_OVERFLOW 0x08
449 
454 #define MCP251863_TX_FIFO_FULL 0
455 #define MCP251863_TX_FIFO_STATUS_MASK 0x1F7
456 #define MCP251863_TX_FIFO_NOT_FULL 0x01
457 #define MCP251863_TX_FIFO_HALF_FULL 0x02
458 #define MCP251863_TX_FIFO_EMPTY 0x04
459 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10
460 #define MCP251863_TX_FIFO_ERROR 0x20
461 #define MCP251863_TX_FIFO_ARBITRATION_LOST 0x40
462 #define MCP251863_TX_FIFO_ABORTED 0x80
463 #define MCP251863_TX_FIFO_TRANSMITTING 0x100
464 
469 #define MCP251863_TEF_FIFO_EMPTY 0
470 #define MCP251863_TEF_FIFO_STATUS_MASK 0x0F
471 #define MCP251863_TEF_FIFO_NOT_EMPTY 0x01
472 #define MCP251863_TEF_FIFO_HALF_FULL 0x02
473 #define MCP251863_TEF_FIFO_FULL 0x04
474 #define MCP251863_TEF_FIFO_OVERFLOW 0x08
475 
480 #define MCP251863_TX_FIFO_NO_EVENT 0
481 #define MCP251863_TX_FIFO_ALL_EVENTS 0x17
482 #define MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01
483 #define MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02
484 #define MCP251863_TX_FIFO_EMPTY_EVENT 0x04
485 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10
486 
487 #define MCP251863_RX_FIFO_NO_EVENT 0
488 #define MCP251863_RX_FIFO_ALL_EVENTS 0x0F
489 #define MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01
490 #define MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02
491 #define MCP251863_RX_FIFO_FULL_EVENT 0x04
492 #define MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08
493 
494 #define MCP251863_TEF_FIFO_NO_EVENT 0
495 #define MCP251863_TEF_FIFO_ALL_EVENTS 0x0F
496 #define MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01
497 #define MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02
498 #define MCP251863_TEF_FIFO_FULL_EVENT 0x04
499 #define MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08
500 
501 #define MCP251863_NO_EVENT 0
502 #define MCP251863_ALL_EVENTS 0xFF1F
503 #define MCP251863_TX_EVENT 0x0001
504 #define MCP251863_RX_EVENT 0x0002
505 #define MCP251863_TIME_BASE_COUNTER_EVENT 0x0004
506 #define MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008
507 #define MCP251863_TEF_EVENT 0x0010
508 
509 #define MCP251863_RAM_ECC_EVENT 0x0100
510 #define MCP251863_SPI_CRC_EVENT 0x0200
511 #define MCP251863_TX_ATTEMPTS_EVENT 0x0400
512 #define MCP251863_RX_OVERFLOW_EVENT 0x0800
513 #define MCP251863_SYSTEM_ERROR_EVENT 0x1000
514 #define MCP251863_BUS_ERROR_EVENT 0x2000
515 #define MCP251863_BUS_WAKEUP_EVENT 0x4000
516 #define MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000
517 
518 #define MCP251863_500K_1M 0
519 #define MCP251863_500K_2M 1
520 #define MCP251863_500K_3M 2
521 #define MCP251863_500K_4M 3
522 #define MCP251863_500K_5M 4
523 #define MCP251863_500K_6M7 5
524 #define MCP251863_500K_8M 6
525 #define MCP251863_500K_10M 7
526 #define MCP251863_250K_500K 8
527 #define MCP251863_250K_833K 9
528 #define MCP251863_250K_1M 10
529 #define MCP251863_250K_1M5 11
530 #define MCP251863_250K_2M 12
531 #define MCP251863_250K_3M 13
532 #define MCP251863_250K_4M 14
533 #define MCP251863_1000K_4M 15
534 #define MCP251863_1000K_8M 16
535 #define MCP251863_125K_500K 17
536 
537 #define MCP251863_NBT_125K 0
538 #define MCP251863_NBT_250K 1
539 #define MCP251863_NBT_500K 2
540 #define MCP251863_NBT_1M 3
541 
542 #define MCP251863_DBT_500K 0
543 #define MCP251863_DBT_833K 1
544 #define MCP251863_DBT_1M 2
545 #define MCP251863_DBT_1M5 3
546 #define MCP251863_DBT_2M 4
547 #define MCP251863_DBT_3M 5
548 #define MCP251863_DBT_4M 6
549 #define MCP251863_DBT_5M 7
550 #define MCP251863_DBT_6M7 8
551 #define MCP251863_DBT_8M 9
552 #define MCP251863_DBT_10M 10
553 
554 #define MCP251863_SSP_MODE_OFF 0
555 #define MCP251863_SSP_MODE_MANUAL 1
556 #define MCP251863_SSP_MODE_AUTO 2
557 
558 #define MCP251863_ERROR_FREE_STATE 0
559 #define MCP251863_ERROR_ALL 0x3F
560 #define MCP251863_TX_RX_WARNING_STATE 0x01
561 #define MCP251863_RX_WARNING_STATE 0x02
562 #define MCP251863_TX_WARNING_STATE 0x04
563 #define MCP251863_RX_BUS_PASSIVE_STATE 0x08
564 #define MCP251863_TX_BUS_PASSIVE_STATE 0x10
565 #define MCP251863_TX_BUS_OFF_STATE 0x20
566 
567 #define MCP251863_TS_SOF 0x00
568 #define MCP251863_TS_EOF 0x01
569 #define MCP251863_TS_RES 0x02
570 
571 #define MCP2518_ECC_NO_EVENT 0x00
572 #define MCP2518_ECC_ALL_EVENTS 0x06
573 #define MCP2518_ECC_SEC_EVENT 0x02
574 #define MCP2518_ECC_DED_EVENT 0x04
575 
576 #define MCP251863_CRC_NO_EVENT 0x00
577 #define MCP251863_CRC_ALL_EVENTS 0x03
578 #define MCP251863_CRC_CRCERR_EVENT 0x01
579 #define MCP251863_CRC_FORMERR_EVENT 0x02
580 
585 #define MCP251863_PIN_0 0
586 #define MCP251863_PIN_1 1
587 
588 #define MCP251863_PINMODE_INT 0
589 #define MCP251863_PINMODE_GPIO 1
590 
591 #define MCP251863_PINOUT 0
592 #define MCP251863_PININ 1
593 
594 #define MCP251863_PINLOW 0
595 #define MCP251863_PINHIGH 1
596 
597 #define MCP251863_PUSHPULL 0
598 #define MCP251863_OPENDRAIN 1
599 
600 #define MCP251863_CLKO_CLOCK 0
601 #define MCP251863_CLKO_SOF 1
602 
607 #define MCP251863_TXREQ_CH0 0x00000001
608 #define MCP251863_TXREQ_CH1 0x00000002
609 #define MCP251863_TXREQ_CH2 0x00000004
610 #define MCP251863_TXREQ_CH3 0x00000008
611 #define MCP251863_TXREQ_CH4 0x00000010
612 #define MCP251863_TXREQ_CH5 0x00000020
613 #define MCP251863_TXREQ_CH6 0x00000040
614 #define MCP251863_TXREQ_CH7 0x00000080
615 
616 #define MCP251863_TXREQ_CH8 0x00000100
617 #define MCP251863_TXREQ_CH9 0x00000200
618 #define MCP251863_TXREQ_CH10 0x00000400
619 #define MCP251863_TXREQ_CH11 0x00000800
620 #define MCP251863_TXREQ_CH12 0x00001000
621 #define MCP251863_TXREQ_CH13 0x00002000
622 #define MCP251863_TXREQ_CH14 0x00004000
623 #define MCP251863_TXREQ_CH15 0x00008000
624 
625 #define MCP251863_TXREQ_CH16 0x00010000
626 #define MCP251863_TXREQ_CH17 0x00020000
627 #define MCP251863_TXREQ_CH18 0x00040000
628 #define MCP251863_TXREQ_CH19 0x00080000
629 #define MCP251863_TXREQ_CH20 0x00100000
630 #define MCP251863_TXREQ_CH21 0x00200000
631 #define MCP251863_TXREQ_CH22 0x00400000
632 #define MCP251863_TXREQ_CH23 0x00800000
633 
634 #define MCP251863_TXREQ_CH24 0x01000000
635 #define MCP251863_TXREQ_CH25 0x02000000
636 #define MCP251863_TXREQ_CH26 0x04000000
637 #define MCP251863_TXREQ_CH27 0x08000000
638 #define MCP251863_TXREQ_CH28 0x10000000
639 #define MCP251863_TXREQ_CH29 0x20000000
640 #define MCP251863_TXREQ_CH30 0x40000000
641 #define MCP251863_TXREQ_CH31 0x80000000
642 
647 #define MCP251863_ICODE_FIFO_CH0 0
648 #define MCP251863_ICODE_FIFO_CH1 1
649 #define MCP251863_ICODE_FIFO_CH2 2
650 #define MCP251863_ICODE_FIFO_CH3 3
651 #define MCP251863_ICODE_FIFO_CH4 4
652 #define MCP251863_ICODE_FIFO_CH5 5
653 #define MCP251863_ICODE_FIFO_CH6 6
654 #define MCP251863_ICODE_FIFO_CH7 7
655 
656 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
657  #define MCP251863_ICODE_FIFO_CH8 8
658  #define MCP251863_ICODE_FIFO_CH9 9
659  #define MCP251863_ICODE_FIFO_CH10 10
660  #define MCP251863_ICODE_FIFO_CH11 11
661  #define MCP251863_ICODE_FIFO_CH12 12
662  #define MCP251863_ICODE_FIFO_CH13 13
663  #define MCP251863_ICODE_FIFO_CH14 14
664  #define MCP251863_ICODE_FIFO_CH15 15
665 #endif
666 
667 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
668  #define MCP251863_ICODE_FIFO_CH16 16
669  #define MCP251863_ICODE_FIFO_CH17 17
670  #define MCP251863_ICODE_FIFO_CH18 18
671  #define MCP251863_ICODE_FIFO_CH19 19
672  #define MCP251863_ICODE_FIFO_CH20 20
673  #define MCP251863_ICODE_FIFO_CH21 21
674  #define MCP251863_ICODE_FIFO_CH22 22
675  #define MCP251863_ICODE_FIFO_CH23 23
676  #define MCP251863_ICODE_FIFO_CH24 24
677  #define MCP251863_ICODE_FIFO_CH25 25
678  #define MCP251863_ICODE_FIFO_CH26 26
679  #define MCP251863_ICODE_FIFO_CH27 27
680  #define MCP251863_ICODE_FIFO_CH28 28
681  #define MCP251863_ICODE_FIFO_CH29 29
682  #define MCP251863_ICODE_FIFO_CH30 30
683  #define MCP251863_ICODE_FIFO_CH31 31
684 #endif
685 
686 #define MCP251863_ICODE_TOTAL_CHANNELS 32
687 #define MCP251863_ICODE_NO_INT 64
688 #define MCP251863_ICODE_CERRIF 65
689 #define MCP251863_ICODE_WAKIF 66
690 #define MCP251863_ICODE_RXOVIF 67
691 #define MCP251863_ICODE_ADDRERR_SERRIF 68
692 #define MCP251863_ICODE_MABOV_SERRIF 69
693 #define MCP251863_ICODE_TBCIF 70
694 #define MCP251863_ICODE_MODIF 71
695 #define MCP251863_ICODE_IVMIF 72
696 #define MCP251863_ICODE_TEFIF 73
697 #define MCP251863_ICODE_TXATIF 74
698 #define MCP251863_ICODE_RESERVED 75
699 
704 #define MCP251863_RXCODE_FIFO_CH0 0
705 #define MCP251863_RXCODE_FIFO_CH1 1
706 #define MCP251863_RXCODE_FIFO_CH2 2
707 #define MCP251863_RXCODE_FIFO_CH3 3
708 #define MCP251863_RXCODE_FIFO_CH4 4
709 #define MCP251863_RXCODE_FIFO_CH5 5
710 #define MCP251863_RXCODE_FIFO_CH6 6
711 #define MCP251863_RXCODE_FIFO_CH7 7
712 
713 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
714  #define MCP251863_RXCODE_FIFO_CH8 8
715  #define MCP251863_RXCODE_FIFO_CH9 9
716  #define MCP251863_RXCODE_FIFO_CH10 10
717  #define MCP251863_RXCODE_FIFO_CH11 11
718  #define MCP251863_RXCODE_FIFO_CH12 12
719  #define MCP251863_RXCODE_FIFO_CH13 13
720  #define MCP251863_RXCODE_FIFO_CH14 14
721  #define MCP251863_RXCODE_FIFO_CH15 15
722 #endif
723 
724 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
725  #define MCP251863_RXCODE_FIFO_CH16 16
726  #define MCP251863_RXCODE_FIFO_CH17 17
727  #define MCP251863_RXCODE_FIFO_CH18 18
728  #define MCP251863_RXCODE_FIFO_CH19 19
729  #define MCP251863_RXCODE_FIFO_CH20 20
730  #define MCP251863_RXCODE_FIFO_CH21 21
731  #define MCP251863_RXCODE_FIFO_CH22 22
732  #define MCP251863_RXCODE_FIFO_CH23 23
733  #define MCP251863_RXCODE_FIFO_CH24 24
734  #define MCP251863_RXCODE_FIFO_CH25 25
735  #define MCP251863_RXCODE_FIFO_CH26 26
736  #define MCP251863_RXCODE_FIFO_CH27 27
737  #define MCP251863_RXCODE_FIFO_CH28 28
738  #define MCP251863_RXCODE_FIFO_CH29 29
739  #define MCP251863_RXCODE_FIFO_CH30 30
740  #define MCP251863_RXCODE_FIFO_CH31 31
741 #endif
742 
743 #define MCP251863_RXCODE_TOTAL_CHANNELS 32
744 #define MCP251863_RXCODE_NO_INT 64
745 #define MCP251863_RXCODE_RESERVED 65
746 
751 #define MCP251863_TXCODE_FIFO_CH0 0
752 #define MCP251863_TXCODE_FIFO_CH1 1
753 #define MCP251863_TXCODE_FIFO_CH2 2
754 #define MCP251863_TXCODE_FIFO_CH3 3
755 #define MCP251863_TXCODE_FIFO_CH4 4
756 #define MCP251863_TXCODE_FIFO_CH5 5
757 #define MCP251863_TXCODE_FIFO_CH6 6
758 #define MCP251863_TXCODE_FIFO_CH7 7
759 
760 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
761  #define MCP251863_TXCODE_FIFO_CH8 8
762  #define MCP251863_TXCODE_FIFO_CH9 9
763  #define MCP251863_TXCODE_FIFO_CH10 10
764  #define MCP251863_TXCODE_FIFO_CH11 11
765  #define MCP251863_TXCODE_FIFO_CH12 12
766  #define MCP251863_TXCODE_FIFO_CH13 13
767  #define MCP251863_TXCODE_FIFO_CH14 14
768  #define MCP251863_TXCODE_FIFO_CH15 15
769 #endif
770 
771 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
772  #define MCP251863_TXCODE_FIFO_CH16 16
773  #define MCP251863_TXCODE_FIFO_CH17 17
774  #define MCP251863_TXCODE_FIFO_CH18 18
775  #define MCP251863_TXCODE_FIFO_CH19 19
776  #define MCP251863_TXCODE_FIFO_CH20 20
777  #define MCP251863_TXCODE_FIFO_CH21 21
778  #define MCP251863_TXCODE_FIFO_CH22 22
779  #define MCP251863_TXCODE_FIFO_CH23 23
780  #define MCP251863_TXCODE_FIFO_CH24 24
781  #define MCP251863_TXCODE_FIFO_CH25 25
782  #define MCP251863_TXCODE_FIFO_CH26 26
783  #define MCP251863_TXCODE_FIFO_CH27 27
784  #define MCP251863_TXCODE_FIFO_CH28 28
785  #define MCP251863_TXCODE_FIFO_CH29 29
786  #define MCP251863_TXCODE_FIFO_CH30 30
787  #define MCP251863_TXCODE_FIFO_CH31 31
788 #endif
789 
790 #define MCP251863_TXCODE_TOTAL_CHANNELS 32
791 #define MCP251863_TXCODE_NO_INT 64
792 #define MCP251863_TXCODE_RESERVED 65
793 
798 #define MCP251863_SYSCLK_40M 0
799 #define MCP251863_SYSCLK_20M 1
800 #define MCP251863_SYSCLK_10M 2
801 
806 #define MCP251863_CLKO_DIV1 0
807 #define MCP251863_CLKO_DIV2 1
808 #define MCP251863_CLKO_DIV4 2
809 #define MCP251863_CLKO_DIV10 3
810 
811 #define N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )
812 #define N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )
813 #define N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )
814 
823 #define MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
824 #define MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
825  // mcp251863_set
827 
842 #define MCP251863_MAP_MIKROBUS( cfg, mikrobus ) \
843  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
844  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
845  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
846  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
847  cfg.stby = MIKROBUS( mikrobus, MIKROBUS_AN ); \
848  cfg.clk = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
849  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
850  // mcp251863_map // mcp251863
853 
858 typedef struct
859 {
861  uint32_t iso_crc_enable;
869  uint32_t store_in_tef;
870  uint32_t txq_enable;
872 
874 
879 typedef struct
880 {
881  uint8_t iso_crc_enable;
882  uint8_t store_in_tef;
883  uint8_t tx_fifo_size;
885  uint8_t tx_priority;
886  uint8_t rx_fifo_size;
888  uint16_t standard_id;
889  uint32_t extended_id;
890  uint8_t fd_frame;
892  uint8_t ide;
894  uint8_t seq;
895 
897 
902 typedef uint8_t mcp251863_id_t;
903 
908 typedef uint32_t mcp251863_msg_time_stamp_t;
909 
914 typedef struct
915 {
916  uint32_t sid : 11;
917  uint32_t eid : 18;
918  uint32_t sid11 : 1;
919  uint32_t unimplemented1 : 2;
920 
922 
927 typedef struct
928 {
929  uint32_t dlc;
930  uint32_t ide;
931  uint32_t rtr;
932  uint32_t brs;
933  uint32_t fdf;
934  uint32_t esi;
935  uint32_t seq;
936  uint32_t unimplemented1;
937 
939 
944 typedef union
945 {
946  struct {
950  } bf;
951  uint32_t word[ 3 ];
952  uint8_t byte[ 12 ];
953 
955 
960 typedef struct
961 {
962  uint32_t dlc : 4;
963  uint32_t ide : 1;
964  uint32_t rtr : 1;
965  uint32_t brs : 1;
966  uint32_t fdf : 1;
967  uint32_t esi : 1;
968  uint32_t unimplemented1 : 2;
969  uint32_t filter_hit : 5;
970  uint32_t unimplemented2 : 16;
971 
973 
978 typedef union
979 {
980  struct {
984  } bf;
985  uint32_t word[ 3 ];
986  uint8_t byte[ 12 ];
987 
989 
994 typedef union
995 {
996  struct {
1000  } bf;
1001  uint32_t word[ 3 ];
1002  uint8_t byte[ 12 ];
1003 
1005 
1010 typedef struct
1011 {
1012  uint32_t sid;
1013  uint32_t eid;
1014  uint32_t sid11;
1015  uint32_t exide;
1016  uint32_t unimplemented1;
1017 
1019 
1024 typedef union
1025 {
1027  uint32_t word;
1028  uint8_t byte[ 4 ];
1029 
1031 
1036 typedef struct
1037 {
1038  uint32_t msid;
1039  uint32_t meid;
1040  uint32_t msid11;
1041  uint32_t mide;
1042  uint32_t unimplemented1;
1043 
1045 
1050 typedef union
1051 {
1053  uint32_t word;
1054  uint8_t byte[ 4 ];
1055 
1057 
1058 typedef union
1059 {
1060  uint8_t byte[ 4 ];
1061  uint32_t word;
1062 
1063 } mcp251863_reg_t;
1064 
1069 typedef union
1070 {
1071  struct {
1072  uint32_t d_net_filter_count : 5;
1073  uint32_t iso_crc_enable : 1;
1075  uint32_t unimplemented1 : 1;
1077  uint32_t wake_up_filter_time : 2;
1078  uint32_t unimplemented2 : 1;
1080  uint32_t unimplemented3 : 3;
1082  uint32_t esi_in_gateway_mode : 1;
1084  uint32_t store_in_tef : 1;
1085  uint32_t txq_enable : 1;
1086  uint32_t op_mode : 3;
1087  uint32_t request_op_mode : 3;
1088  uint32_t abort_all_tx : 1;
1090  } bf;
1091  uint32_t word;
1092  uint8_t byte[ 4 ];
1093 
1094 } mcp251863_ctl_t;
1095 
1100 typedef union
1101 {
1102  struct {
1103  uint32_t tx_not_full_ie : 1;
1104  uint32_t unimplemented1 : 1;
1105  uint32_t tx_empty_ie : 1;
1106  uint32_t unimplemented2 : 1;
1107  uint32_t tx_attempt_ie : 1;
1108  uint32_t unimplemented3 : 2;
1109  uint32_t tx_enable : 1;
1110  uint32_t uinc : 1;
1111  uint32_t tx_request : 1;
1112  uint32_t freset : 1;
1113  uint32_t unimplemented4 : 5;
1114  uint32_t tx_priority : 5;
1115  uint32_t tx_attempts : 2;
1116  uint32_t unimplemented5 : 1;
1117  uint32_t fifo_size : 5;
1118  uint32_t pay_load_size : 3;
1119  } tx_bf;
1120  uint32_t word;
1121  uint8_t byte[ 4 ];
1122 
1124 
1129 typedef union
1130 {
1131  struct {
1132  uint32_t tefneie : 1;
1133  uint32_t tefhfie : 1;
1134  uint32_t teffulie : 1;
1135  uint32_t tefovie : 1;
1136  uint32_t unimplemented1 : 1;
1137  uint32_t time_stamp_enable : 1;
1138  uint32_t unimplemented2 : 2;
1139  uint32_t uinc : 1;
1140  uint32_t unimplemented3 : 1;
1141  uint32_t freset : 1;
1142  uint32_t unimplemented4 : 13;
1143  uint32_t fifo_size : 5;
1144  uint32_t unimplemented5 : 3;
1145  } bf;
1146  uint32_t word;
1147  uint8_t byte[ 4 ];
1148 
1150 
1155 typedef union
1156 {
1157  struct {
1158  uint32_t rx_not_empty_ie : 1;
1159  uint32_t rx_half_full_ie : 1;
1160  uint32_t rx_full_ie : 1;
1161  uint32_t rx_over_flow_ie : 1;
1162  uint32_t unimplemented1 : 1;
1163  uint32_t rx_time_stamp_enable : 1;
1164  uint32_t unimplemented2 : 1;
1165  uint32_t tx_enable : 1;
1166  uint32_t uinc : 1;
1167  uint32_t unimplemented3 : 1;
1168  uint32_t freset : 1;
1169  uint32_t unimplemented4 : 13;
1170  uint32_t fifo_size : 5;
1171  uint32_t pay_load_size : 3;
1172  } rx_bf;
1173 
1174  struct {
1175  uint32_t tx_not_full_ie : 1;
1176  uint32_t tx_half_full_ie : 1;
1177  uint32_t tx_empty_ie : 1;
1178  uint32_t unimplemented1 : 1;
1179  uint32_t tx_attempt_ie : 1;
1180  uint32_t unimplemented2 : 1;
1181  uint32_t rtr_enable : 1;
1182  uint32_t tx_enable : 1;
1183  uint32_t uinc : 1;
1184  uint32_t tx_request : 1;
1185  uint32_t freset : 1;
1186  uint32_t unimplemented3 : 5;
1187  uint32_t tx_priority : 5;
1188  uint32_t tx_attempts : 2;
1189  uint32_t unimplemented4 : 1;
1190  uint32_t fifo_size : 5;
1191  uint32_t pay_load_size : 3;
1192  } tx_bf;
1193  uint32_t word;
1194  uint8_t byte[ 4 ];
1195 
1197 
1202 typedef union
1203 {
1204  struct {
1205  uint32_t buffer_pointer : 5;
1206  uint32_t unimplemented1 : 2;
1207  uint32_t enable : 1;
1208  } bf;
1209  uint8_t byte;
1210 
1212 
1217 typedef union
1218 {
1219  struct {
1220  uint32_t pll_enable : 1;
1221  uint32_t unimplemented1 : 1;
1222  uint32_t osc_disable : 1;
1223  uint32_t unimplemented2 : 1;
1224  uint32_t sclk_divide : 1;
1225  uint32_t clk_out_divide : 2;
1226  uint32_t unimplemented3 : 1;
1227  uint32_t pll_ready : 1;
1228  uint32_t unimplemented4 : 1;
1229  uint32_t osc_ready : 1;
1230  uint32_t unimplemented5 : 1;
1231  uint32_t sclk_ready : 1;
1232  uint32_t unimplemented6 : 19;
1233  } bf;
1234  uint32_t word;
1235  uint8_t byte[ 4 ];
1236 
1238 
1243 typedef struct
1244 {
1245  uint32_t pll_enable;
1246  uint32_t osc_disable;
1247  uint32_t sclk_divide;
1248  uint32_t clk_out_divide;
1249 
1251 
1256 typedef union
1257 {
1258  struct {
1259  uint32_t tris0 : 1;
1260  uint32_t tris1 : 1;
1261  uint32_t unimplemented1 : 2;
1263  uint32_t auto_sleep_enable : 1;
1264  uint32_t xcr_stby_enable : 1;
1265  uint32_t unimplemented2 : 1;
1266  uint32_t lat0 : 1;
1267  uint32_t lat1 : 1;
1268  uint32_t unimplemented3 : 5;
1269  uint32_t hvdetsel : 1;
1270  uint32_t gpio0 : 1;
1271  uint32_t gpio1 : 1;
1272  uint32_t unimplemented4 : 6;
1273  uint32_t pin_mode0 : 1;
1274  uint32_t pin_mode1 : 1;
1275  uint32_t unimplemented5 : 2;
1276  uint32_t tx_can_open_drain : 1;
1277  uint32_t sof_output_enable : 1;
1278  uint32_t int_pin_open_drain : 1;
1279  uint32_t unimplemented6 : 1;
1280  } bf;
1281  uint32_t word;
1282  uint8_t byte[ 4 ];
1283 
1285 
1290 typedef union
1291 {
1292  struct {/* can_fd_ubp */
1293  uint32_t ecc_en : 1;
1294  uint32_t secie : 1;
1295  uint32_t dedie : 1;
1296  uint32_t unimplemented1 : 5;
1297  uint32_t parity : 7;
1298  uint32_t unimplemented2 : 17;
1299  } bf;
1300  uint32_t word;
1301  uint8_t byte[ 4 ];
1302 
1304 
1309 typedef struct
1310 {
1311  uint32_t d_net_filter_count : 5;
1312  uint32_t iso_crc_enable : 1;
1315  uint32_t wake_up_filter_time : 2;
1318  uint32_t esi_in_gateway_mode : 1;
1320  uint32_t store_in_tef : 1;
1321  uint32_t txq_enable : 1;
1323 
1325 
1330 typedef struct
1331 {
1332  uint32_t rtr_enable;
1333  uint32_t tx_priority;
1334  uint32_t tx_attempts;
1335  uint32_t fifo_size;
1336  uint32_t pay_load_size;
1337 
1339 
1344 typedef struct
1345 {
1346  uint32_t tx_priority : 5;
1347  uint32_t tx_attempts : 2;
1348  uint32_t fifo_size : 5;
1349  uint32_t pay_load_size : 3;
1350 
1352 
1357 typedef struct
1358 {
1360  uint32_t fifo_size;
1361  uint32_t pay_load_size;
1362 
1364 
1365 
1370 typedef union
1371 {
1372  struct {
1373  uint32_t user_address : 12;
1374  uint32_t unimplemented1 : 20;
1375  } bf;
1376  uint32_t word;
1377  uint8_t byte[ 4 ];
1378 
1380 
1385 typedef struct
1386 {
1388  uint32_t fifo_size;
1389 
1391 
1396 typedef union
1397 {
1398  struct {
1399  uint32_t swj : 7;
1400  uint32_t unimplemented1 : 1;
1401  uint32_t tseg2 : 7;
1402  uint32_t unimplemented2 : 1;
1403  uint32_t tseg1 : 8;
1404  uint32_t brp : 8;
1405  } bf;
1406  uint32_t word;
1407  uint8_t byte[ 4 ];
1408 
1410 
1415 typedef union
1416 {
1417  struct {
1418  uint32_t swj : 4;
1419  uint32_t unimplemented1 : 4;
1420  uint32_t tseg2 : 4;
1421  uint32_t unimplemented2 : 4;
1422  uint32_t tseg1 : 5;
1423  uint32_t unimplemented3 : 3;
1424  uint32_t brp : 8;
1425  } bf;
1426  uint32_t word;
1427  uint8_t byte[ 4 ];
1428 
1430 
1435 typedef union
1436 {
1437  struct {
1438  uint32_t tdc_value : 6;
1439  uint32_t unimplemented1 : 2;
1440  uint32_t tdc_offset : 7;
1441  uint32_t unimplemented2 : 1;
1442  uint32_t tdc_mode : 2;
1443  uint32_t unimplemented3 : 6;
1444  uint32_t sid11_enable : 1;
1445  uint32_t edge_filter_enable : 1;
1446  uint32_t unimplemented4 : 6;
1447  } bf;
1448  uint32_t word;
1449  uint8_t byte[ 4 ];
1450 
1452 
1457 typedef union
1458 {
1459  struct {
1460  uint32_t tbc_prescaler : 10;
1461  uint32_t unimplemented1 : 6;
1462  uint32_t tbc_enable : 1;
1463  uint32_t time_stamp_eof : 1;
1464  uint32_t unimplemented2 : 14;
1465  } bf;
1466  uint32_t word;
1467  uint8_t byte[ 4 ];
1468 
1470 
1475 typedef struct
1476 {
1477  uint32_t txie : 1;
1478  uint32_t rxie : 1;
1479  uint32_t tbcie : 1;
1480  uint32_t modie : 1;
1481  uint32_t tefie : 1;
1482  uint32_t unimplemented2 : 3;
1483 
1484  uint32_t eccie : 1;
1485  uint32_t spicrcie : 1;
1486  uint32_t txatie : 1;
1487  uint32_t rxovie : 1;
1488  uint32_t serrie : 1;
1489  uint32_t cerrie : 1;
1490  uint32_t wakie : 1;
1491  uint32_t ivmie : 1;
1492 
1494 
1499 typedef union
1500 {
1502  uint16_t word;
1503  uint8_t byte[ 2 ];
1504 
1506 
1511 typedef union
1512 {
1513  struct {
1514  uint32_t icode : 7;
1515  uint32_t unimplemented1 : 1;
1516  uint32_t filter_hit : 5;
1517  uint32_t unimplemented2 : 3;
1518  uint32_t tx_code : 7;
1519  uint32_t unimplemented3 : 1;
1520  uint32_t rx_code : 7;
1521  uint32_t unimplemented4 : 1;
1522  } bf;
1523  uint32_t word;
1524  uint8_t byte[ 4 ];
1525 
1527 
1532 typedef struct
1533 {
1534  uint32_t TXIF : 1;
1535  uint32_t RXIF : 1;
1536  uint32_t TBCIF : 1;
1537  uint32_t MODIF : 1;
1538  uint32_t TEFIF : 1;
1539  uint32_t unimplemented1 : 3;
1540 
1541  uint32_t ECCIF : 1;
1542  uint32_t SPICRCIF : 1;
1543  uint32_t TXATIF : 1;
1544  uint32_t RXOVIF : 1;
1545  uint32_t SERRIF : 1;
1546  uint32_t CERRIF : 1;
1547  uint32_t WAKIF : 1;
1548  uint32_t IVMIF : 1;
1549 
1551 
1556 typedef union
1557 {
1559  uint16_t word;
1560  uint8_t byte[ 2 ];
1561 
1563 
1568 typedef union
1569 {
1570  struct {
1573  } bf;
1574  uint32_t word;
1575  uint8_t byte[ 4 ];
1576 
1577 } mcp251863_int_t;
1578 
1583 typedef union
1584 {
1585  struct {
1586  uint32_t rx_error_count : 8;
1587  uint32_t tx_error_count : 8;
1588  uint32_t error_state_warning : 1;
1594  uint32_t unimplemented1 : 10;
1595  } bf;
1596  uint32_t word;
1597  uint8_t byte[ 4 ];
1598 
1600 
1605 typedef union
1606 {
1607  struct {
1608  uint32_t tef_not_empty_if : 1;
1609  uint32_t tef_half_full_if : 1;
1610  uint32_t tef_full_if : 1;
1611  uint32_t tef_ov_if : 1;
1612  uint32_t unimplemented1 : 28;
1613  } bf;
1614  uint32_t word;
1615  uint8_t byte[ 4 ];
1616 
1617 } mcp251863_tef_t;
1618 
1623 typedef union
1624 {
1625  struct {
1626  uint32_t tx_not_full_if : 1;
1627  uint32_t unimplemented1 : 1;
1628  uint32_t tx_empty_if : 1;
1629  uint32_t unimplemented2 : 1;
1630  uint32_t tx_attempt_if : 1;
1631  uint32_t tx_error : 1;
1632  uint32_t tx_lost_arbitration : 1;
1633  uint32_t tx_aborted : 1;
1634  uint32_t fifo_index : 5;
1635  uint32_t unimplemented3 : 19;
1636  } tx_bf;
1637  uint32_t word;
1638  uint8_t byte[ 4 ];
1639 
1641 
1646 typedef union
1647 {
1648  struct {
1649  uint32_t rx_not_empty_if : 1;
1650  uint32_t rx_half_full_if : 1;
1651  uint32_t rx_full_if : 1;
1652  uint32_t rx_over_flow_if : 1;
1653  uint32_t unimplemented1 : 4;
1654  uint32_t fifo_index : 5;
1655  uint32_t unimplemented2 : 19;
1656  } rx_bf;
1657 
1658  struct {
1659  uint32_t tx_not_full_if : 1;
1660  uint32_t tx_half_full_if : 1;
1661  uint32_t tx_empty_if : 1;
1662  uint32_t unimplemented1 : 1;
1663  uint32_t tx_attempt_if : 1;
1664  uint32_t tx_error : 1;
1665  uint32_t tx_lost_arbitration : 1;
1666  uint32_t tx_aborted : 1;
1667  uint32_t fifo_index : 5;
1668  uint32_t unimplemented2 : 19;
1669  } tx_bf;
1670  uint32_t word;
1671  uint8_t byte[ 4 ];
1672 
1674 
1679 typedef union
1680 {
1681  struct {
1682  uint32_t crc : 16;
1683  uint32_t crcerrif : 1;
1684  uint32_t ferrif : 1;
1685  uint32_t unimplemented1 : 6;
1686  uint32_t crcerrie : 1;
1687  uint32_t ferrie : 1;
1688  uint32_t unimplemented2 : 6;
1689  } bf;
1690  uint32_t word;
1691  uint8_t byte[ 4 ];
1692 
1693 } mcp251863_crc_t;
1694 
1699 typedef union
1700 {
1701  struct {
1702  uint32_t unimplemented1 : 1;
1703  uint32_t secif : 1;
1704  uint32_t dedif : 1;
1705  uint32_t unimplemented2 : 13;
1706  uint32_t error_address : 12;
1707  uint32_t unimplemented3 : 4;
1708  } bf;
1709  uint32_t word;
1710  uint8_t byte[ 4 ];
1711 
1713 
1718 typedef struct
1719 {
1720  uint32_t pll_ready : 1;
1721  uint32_t osc_ready : 1;
1722  uint32_t sclk_ready : 1;
1723 
1725 
1730 typedef struct
1731 {
1732  uint32_t n_bit0_err : 1;
1733  uint32_t n_bit1_err : 1;
1734  uint32_t n_ack_err : 1;
1735  uint32_t n_form_err : 1;
1736  uint32_t n_stuff_err : 1;
1737  uint32_t n_crc_err : 1;
1738  uint32_t unimplemented1 : 1;
1739  uint32_t txbo_err : 1;
1740  uint32_t d_bit0_err : 1;
1741  uint32_t d_bit1_err : 1;
1742  uint32_t unimplemented2 : 1;
1743  uint32_t d_form_err : 1;
1744  uint32_t d_stuff_err : 1;
1745  uint32_t d_crc_err : 1;
1746  uint32_t esi : 1;
1747  uint32_t dlc_mismatch : 1;
1748 
1750 
1755 typedef struct
1756 {
1757  uint8_t n_rec;
1758  uint8_t n_tec;
1759  uint8_t d_rec;
1760  uint8_t d_tec;
1761 
1763 
1768 typedef union
1769 {
1770  struct {
1774  } bf;
1775  uint32_t word[ 2 ];
1776  uint8_t byte[ 8 ];
1777 
1779 
1784 typedef union
1785 {
1786  struct {
1787  uint32_t n_rx_error_count : 8;
1788  uint32_t n_tx_error_count : 8;
1789  uint32_t d_rx_error_count : 8;
1790  uint32_t d_tx_error_count : 8;
1791  } bf;
1792  uint32_t word;
1793  uint8_t byte[ 4 ];
1794 
1796 
1801 typedef union
1802 {
1803  struct {
1804  uint32_t error_free_msg_count : 16;
1805  uint32_t n_bit0_error : 1;
1806  uint32_t n_bit1_error : 1;
1807  uint32_t n_ack_error : 1;
1808  uint32_t n_form_error : 1;
1809  uint32_t n_stuff_error : 1;
1810  uint32_t n_crc_error : 1;
1811  uint32_t unimplemented1 : 1;
1812  uint32_t txbo_error : 1;
1813  uint32_t d_bit0_error : 1;
1814  uint32_t d_bit1_error : 1;
1815  uint32_t d_ack_error : 1;
1816  uint32_t d_form_error : 1;
1817  uint32_t d_stuff_error : 1;
1818  uint32_t d_crc_error : 1;
1819  uint32_t esi : 1;
1820  uint32_t unimplemented2 : 1;
1821  } bf;
1822  uint32_t word;
1823  uint8_t byte[ 4 ];
1824 
1826 
1831 typedef struct
1832 {
1833  uint16_t address;
1834  uint8_t *rxd;
1835  uint16_t n_bytes;
1836  uint8_t *txd;
1837  uint32_t txd_num_bytes;
1838 
1840 
1845 typedef struct
1846 {
1848  uint8_t tx_flags;
1849  uint8_t rx_flags;
1850  uint8_t error_flags;
1851  uint8_t tec;
1852  uint8_t rec;
1853  uint8_t op_mode;
1854  uint32_t tx_id;
1855 
1864 
1866 
1871 typedef struct
1872 {
1873  // Output pins
1874  digital_out_t stby;
1876  // Input pins
1877  digital_in_t clk;
1878  digital_in_t int_pin;
1880  // Modules
1881  spi_master_t spi;
1883  pin_name_t chip_select;
1887 
1888 } mcp251863_t;
1889 
1894 typedef struct
1895 {
1896  // Communication gpio pins
1897  pin_name_t miso;
1898  pin_name_t mosi;
1899  pin_name_t sck;
1900  pin_name_t cs;
1902  // Additional gpio pins
1903  pin_name_t stby;
1904  pin_name_t clk;
1905  pin_name_t int_pin;
1907  // static variable
1908  uint32_t spi_speed;
1909  spi_master_mode_t spi_mode;
1910  spi_master_chip_select_polarity_t cs_polarity;
1912 } mcp251863_cfg_t;
1913 
1918 typedef enum
1919 {
1921  MCP251863_ERROR = -1
1922 
1924 
1941 
1956 
1971 
1986 err_t mcp251863_generic_write ( mcp251863_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
1987 
2002 err_t mcp251863_generic_read ( mcp251863_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
2003 
2016 err_t mcp251863_transmit_message ( mcp251863_t *ctx, uint8_t *data_in, uint16_t data_len );
2017 
2030 err_t mcp251863_receive_message ( mcp251863_t *ctx, uint8_t *data_out, uint16_t *data_len );
2031 
2043 
2056 err_t mcp251863_read_byte ( mcp251863_t *ctx, uint16_t address, uint8_t *data_out );
2057 
2070 err_t mcp251863_write_byte ( mcp251863_t *ctx, uint16_t address, uint8_t data_in );
2071 
2084 err_t mcp251863_read_word ( mcp251863_t *ctx, uint16_t address, uint32_t *data_out );
2085 
2098 err_t mcp251863_write_word ( mcp251863_t *ctx, uint16_t address, uint32_t data_in );
2099 
2112 err_t mcp251863_read_half_word ( mcp251863_t *ctx, uint16_t address, uint16_t *data_out );
2113 
2126 err_t mcp251863_write_half_word ( mcp251863_t *ctx, uint16_t address, uint16_t data_in );
2127 
2143 err_t mcp251863_write_byte_safe ( mcp251863_t *ctx, uint16_t address, uint8_t data_in );
2144 
2160 err_t mcp251863_write_word_safe ( mcp251863_t *ctx, uint16_t address, uint32_t data_in );
2161 
2175 err_t mcp251863_read_byte_array ( mcp251863_t *ctx, uint16_t address, uint8_t *data_out, uint16_t n_bytes );
2176 
2189 err_t mcp251863_read_byte_array_with_crc ( mcp251863_t *ctx, bool from_ram, bool *crc_is_correct );
2190 
2204 err_t mcp251863_write_byte_array ( mcp251863_t *ctx, uint16_t address, uint8_t *data_in, uint16_t n_bytes );
2205 
2217 err_t mcp251863_write_byte_array_with_crc ( mcp251863_t *ctx, bool from_ram );
2218 
2232 err_t mcp251863_read_word_array ( mcp251863_t *ctx, uint16_t address, uint32_t *data_out, uint16_t n_words );
2233 
2247 err_t mcp251863_write_word_array ( mcp251863_t *ctx, uint16_t address, uint32_t *data_in, uint16_t n_words );
2248 
2261 
2269 
2282 err_t mcp251863_operation_mode_select ( mcp251863_t *ctx, uint8_t op_mode );
2283 
2292 
2306 
2314 
2327 
2335 
2349 err_t mcp251863_transmit_channel_load ( mcp251863_t *ctx, uint8_t channel, mcp251863_tx_msg_obj_t *tx_obj, bool flush );
2350 
2362 err_t mcp251863_transmit_channel_flush ( mcp251863_t *ctx, uint8_t channel );
2363 
2376 err_t mcp251863_transmit_channel_status_get ( mcp251863_t *ctx, uint8_t channel, uint16_t *status );
2377 
2389 int8_t mcp251863_transmit_channel_reset ( mcp251863_t *ctx, uint8_t channel );
2390 
2403 err_t mcp251863_transmit_channel_update ( mcp251863_t *ctx, uint8_t channel, bool flush );
2404 
2416 err_t mcp251863_transmit_request_set ( mcp251863_t *ctx, uint32_t tx_req );
2417 
2429 err_t mcp251863_transmit_request_get ( mcp251863_t *ctx, uint32_t* tx_req );
2430 
2442 err_t mcp251863_transmit_channel_abort ( mcp251863_t *ctx, uint8_t channel );
2443 
2455 
2468 
2482 
2496 
2510 err_t mcp251863_filter_to_fifo_link ( mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable );
2511 
2523 err_t mcp251863_filter_enable ( mcp251863_t *ctx, uint8_t filter );
2524 
2537 err_t mcp251863_filter_disable ( mcp251863_t *ctx, uint8_t filter );
2538 
2552 
2565 err_t mcp251863_receive_channel_configure ( mcp251863_t *ctx, uint8_t channel,
2566  mcp251863_rx_fifo_cfg_t *config );
2567 
2575 
2588 err_t mcp251863_receive_channel_status_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *status );
2589 
2605 err_t mcp251863_receive_message_get ( mcp251863_t *ctx, uint8_t channel, mcp251863_rx_msg_obj_t *rx_obj );
2606 
2618 err_t mcp251863_receive_channel_reset ( mcp251863_t *ctx, uint8_t channel );
2619 
2631 err_t mcp251863_receive_channel_update ( mcp251863_t *ctx, uint8_t channel );
2632 
2644 err_t mcp251863_tef_status_get ( mcp251863_t *ctx, uint8_t *status );
2645 
2660 
2672 
2684 
2697 
2707 
2719 err_t mcp251863_module_event_get ( mcp251863_t *ctx, uint16_t *flags );
2720 
2733 err_t mcp251863_module_event_enable ( mcp251863_t *ctx, uint16_t flags );
2734 
2747 err_t mcp251863_module_event_disable ( mcp251863_t *ctx, uint16_t flags );
2748 
2762 err_t mcp251863_module_event_clear ( mcp251863_t *ctx, uint16_t flags );
2763 
2775 err_t mcp251863_module_event_rx_code_get ( mcp251863_t *ctx, uint8_t *rx_code );
2776 
2788 err_t mcp251863_module_event_tx_code_get ( mcp251863_t *ctx, uint8_t *tx_code );
2789 
2801 err_t mcp251863_module_event_filter_hit_get ( mcp251863_t *ctx, uint8_t* filter_hit );
2802 
2814 err_t mcp251863_module_event_icode_get ( mcp251863_t *ctx, uint8_t *icode );
2815 
2828 err_t mcp251863_transmit_channel_event_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *flags );
2829 
2841 err_t mcp251863_transmit_event_get ( mcp251863_t *ctx, uint32_t *txif );
2842 
2854 err_t mcp251863_transmit_event_attempt_get ( mcp251863_t *ctx, uint32_t *txatif );
2855 
2868 err_t mcp251863_transmit_channel_index_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *idx );
2869 
2883 err_t mcp251863_transmit_channel_event_enable( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2884 
2898 err_t mcp251863_transmit_channel_event_disable ( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2899 
2913 
2926 err_t mcp251863_receive_channel_event_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *flags );
2927 
2939 err_t mcp251863_receive_event_get ( mcp251863_t *ctx, uint32_t *rxif );
2940 
2952 err_t mcp251863_receive_event_overflow_get ( mcp251863_t *ctx, uint32_t *rxovif );
2953 
2963 int8_t mcp251863_receive_channel_index_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *idx );
2964 
2978 err_t mcp251863_receive_channel_event_enable ( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2979 
2993 err_t mcp251863_receive_channel_event_disable ( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2994 
3008 
3021 err_t mcp251863_tef_event_get ( mcp251863_t *ctx, uint8_t* flags );
3022 
3035 err_t mcp251863_tef_event_enable ( mcp251863_t *ctx, uint8_t flags );
3036 
3049 err_t mcp251863_tef_event_disable ( mcp251863_t *ctx, uint8_t flags );
3050 
3064 
3077 
3089 err_t mcp251863_error_count_receive_get ( mcp251863_t *ctx, uint8_t *rec );
3090 
3102 err_t mcp251863_error_state_get ( mcp251863_t *ctx, uint8_t *flags );
3103 
3117 err_t mcp251863_error_count_state_get ( mcp251863_t *ctx, uint8_t *tec, uint8_t *rec, uint8_t *flags );
3118 
3132 
3144 
3157 
3170 
3183 err_t mcp251863_ecc_event_get ( mcp251863_t *ctx, uint8_t *flags );
3184 
3196 err_t mcp251863_ecc_parity_set ( mcp251863_t *ctx, uint8_t parity );
3197 
3209 err_t mcp251863_ecc_parity_get ( mcp251863_t *ctx, uint8_t *parity );
3210 
3222 err_t mcp251863_ecc_error_address_get ( mcp251863_t *ctx, uint16_t *address );
3223 
3236 err_t mcp251863_ecc_event_enable ( mcp251863_t *ctx, uint8_t flags );
3237 
3250 err_t mcp251863_ecc_event_disable ( mcp251863_t *ctx, uint8_t flags );
3251 
3264 err_t mcp251863_ecc_event_clear ( mcp251863_t *ctx, uint8_t flags );
3265 
3278 err_t mcp251863_crc_event_enable ( mcp251863_t *ctx, uint8_t flags );
3279 
3292 err_t mcp251863_crc_event_disable ( mcp251863_t *ctx, uint8_t flags );
3293 
3306 err_t mcp251863_crc_event_clear ( mcp251863_t *ctx, uint8_t flags );
3307 
3319 err_t mcp251863_crc_event_get ( mcp251863_t *ctx, uint8_t *flags );
3320 
3332 err_t mcp251863_crc_value_get ( mcp251863_t *ctx, uint16_t *crc );
3333 
3345 err_t mcp251863_ram_init ( mcp251863_t *ctx, uint8_t rx_data );
3346 
3359 
3372 
3384 err_t mcp251863_time_stamp_get ( mcp251863_t *ctx, uint32_t *time_stamp );
3385 
3397 err_t mcp251863_time_stamp_set ( mcp251863_t *ctx, uint32_t ts );
3398 
3412 
3424 err_t mcp251863_time_stamp_prescaler_set ( mcp251863_t *ctx, uint16_t time_stamp );
3425 
3439 
3455 
3463 
3476 
3489 err_t mcp251863_bit_time_configure ( mcp251863_t *ctx, uint8_t bit_time, uint8_t clk );
3490 
3503 
3516 
3529 
3542 
3555 
3568 
3582 err_t mcp251863_gpio_mode_configure ( mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1 );
3583 
3597 err_t mcp251863_gpio_direction_configure ( mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1 );
3598 
3611 
3624 
3638 
3652 
3666 err_t mcp251863_gpio_pin_set ( mcp251863_t *ctx, uint8_t pos, uint8_t latch );
3667 
3680 err_t mcp251863_gpio_pin_read ( mcp251863_t *ctx, uint8_t pos, uint8_t *state );
3681 
3695 
3702 uint32_t mcp251863_dlc_to_data_bytes ( uint8_t dlc );
3703 
3716 err_t mcp251863_fifo_index_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *data_out );
3717 
3727 uint16_t mcp251863_calculate_crc16 ( uint8_t *data_pointer, uint16_t size );
3728 
3735 uint8_t mcp251863_data_bytes_to_dlc ( uint8_t num );
3736 
3737 #ifdef __cplusplus
3738 }
3739 #endif
3740 #endif // MCP251863_H
3741  // mcp251863
3743 
3744 // ------------------------------------------------------------------------ END
mcp251863_cfg_t::spi_speed
uint32_t spi_speed
Definition: mcp251863.h:1908
mcp251863_nbt_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1400
mcp251863_tx_que_ctl_t::freset
uint32_t freset
Definition: mcp251863.h:1112
mcp251863_tef_ctl_t
MCP251863 Click Transmit Event FIFO Control Register.
Definition: mcp251863.h:1130
mcp251863_mask_obj_id_t::meid
uint32_t meid
Definition: mcp251863.h:1039
mcp251863_read_word
err_t mcp251863_read_word(mcp251863_t *ctx, uint16_t address, uint32_t *data_out)
SPI Read Word.
mcp251863_fifo_stat_t::rx_over_flow_if
uint32_t rx_over_flow_if
Definition: mcp251863.h:1652
mcp251863_write_half_word
err_t mcp251863_write_half_word(mcp251863_t *ctx, uint16_t address, uint16_t data_in)
SPI Write Half Word.
mcp251863_bus_error_count_t::n_rec
uint8_t n_rec
Definition: mcp251863.h:1757
mcp251863_transmit_channel_event_attempt_clear
err_t mcp251863_transmit_channel_event_attempt_clear(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Event Clear.
mcp251863_transmit_request_get
err_t mcp251863_transmit_request_get(mcp251863_t *ctx, uint32_t *tx_req)
Get TXREQ register.
mcp251863_int_vec_t
MCP251863 Click Interrupt Vector Register.
Definition: mcp251863.h:1512
mcp251863_ctl_t::esi_in_gateway_mode
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1082
mcp251863_rx_msg_obj_t::ctrl
mcp251863_rx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:982
mcp251863_fifo_stat_t::tx_not_full_if
uint32_t tx_not_full_if
Definition: mcp251863.h:1659
mcp251863_rx_msg_obj_t::time_stamp
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:983
mcp251863_osc_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1226
mcp251863_tef_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1142
mcp251863_io_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1268
mcp251863_tx_msg_obj_ctl_t::fdf
uint32_t fdf
Definition: mcp251863.h:933
mcp251863_tx_que_ctl_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1115
mcp251863_cfg_t::sck
pin_name_t sck
Definition: mcp251863.h:1899
mcp251863_bit_time_configure_data_10_mhz
err_t mcp251863_bit_time_configure_data_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 10MHz system clock.
mcp251863_ecc_sta_t::error_address
uint32_t error_address
Definition: mcp251863.h:1706
mcp251863_bus_diag1_t::d_form_error
uint32_t d_form_error
Definition: mcp251863.h:1816
mcp251863_int_en_t::ivmie
uint32_t ivmie
Definition: mcp251863.h:1491
mcp251863_nbt_cfg_t::swj
uint32_t swj
Definition: mcp251863.h:1399
mcp251863_fifo_ctl_t
MCP251863 Click FIFO Control Register.
Definition: mcp251863.h:1156
mcp251863_int_en_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1482
mcp251863_cfg_t
MCP251863 Click configuration object.
Definition: mcp251863.h:1895
mcp251863_ctl_t::wake_up_filter_time
uint32_t wake_up_filter_time
Definition: mcp251863.h:1077
mcp251863_ecc_event_enable
err_t mcp251863_ecc_event_enable(mcp251863_t *ctx, uint8_t flags)
ECC Event Enable.
mcp251863_ecc_ctl_t::dedie
uint32_t dedie
Definition: mcp251863.h:1295
mcp251863_dbt_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1419
mcp251863_bus_diag1_t::n_ack_error
uint32_t n_ack_error
Definition: mcp251863.h:1807
mcp251863_bus_diag_flags_t::n_stuff_err
uint32_t n_stuff_err
Definition: mcp251863.h:1736
mcp251863_ecc_enable
err_t mcp251863_ecc_enable(mcp251863_t *ctx)
Enable ECC.
mcp251863_tef_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1138
mcp251863_ecc_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1298
mcp251863_dbt_cfg_t::brp
uint32_t brp
Definition: mcp251863.h:1424
mcp251863_rx_fifo_cfg_t
MCP251863 Click CAN Receive Channel Configure.
Definition: mcp251863.h:1358
mcp251863_gpio_transmit_pin_open_drain_configure
err_t mcp251863_gpio_transmit_pin_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain TXCAN.
mcp251863_oscillator_status_get
err_t mcp251863_oscillator_status_get(mcp251863_t *ctx, mcp251863_osc_sta_t *status)
Get Oscillator Status.
mcp251863_bit_time_configure_data_40_mhz
err_t mcp251863_bit_time_configure_data_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 40MHz system clock.
mcp251863_receive_channel_update
err_t mcp251863_receive_channel_update(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Update.
mcp251863_transmit_channel_abort
err_t mcp251863_transmit_channel_abort(mcp251863_t *ctx, uint8_t channel)
Abort transmission of single FIFO.
mcp251863_fifo_ctl_t::tx_enable
uint32_t tx_enable
Definition: mcp251863.h:1165
mcp251863_tx_msg_obj_t::id
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:947
mcp251863_tef_ctl_t::tefhfie
uint32_t tefhfie
Definition: mcp251863.h:1133
mcp251863_transmit_channel_event_get
err_t mcp251863_transmit_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Transmit FIFO Event Get.
mcp251863_bus_diag_flags_t::d_crc_err
uint32_t d_crc_err
Definition: mcp251863.h:1745
mcp251863_device_net_filter_count_set
err_t mcp251863_device_net_filter_count_set(mcp251863_t *ctx, uint8_t dnfc)
Set Device Net Filter Count.
mcp251863_trec_t::tx_error_state_warning
uint32_t tx_error_state_warning
Definition: mcp251863.h:1590
mcp251863_int_flags_stat_t::RXOVIF
uint32_t RXOVIF
Definition: mcp251863.h:1544
mcp251863_trec_t
MCP251863 Click Transmit/Receive Error Count Register.
Definition: mcp251863.h:1584
mcp251863_can_cfg_t::wake_up_filter_enable
uint32_t wake_up_filter_enable
Definition: mcp251863.h:863
mcp251863_oscillator_enable
err_t mcp251863_oscillator_enable(mcp251863_t *ctx)
Enable oscillator to wake-up from sleep.
mcp251863_bus_diag1_t::esi
uint32_t esi
Definition: mcp251863.h:1819
mcp251863_transmit_channel_flush
err_t mcp251863_transmit_channel_flush(mcp251863_t *ctx, uint8_t channel)
TX Channel Flush.
mcp251863_mask_obj_t
MCP251863 Click Mask Object Register.
Definition: mcp251863.h:1051
mcp251863_dbt_cfg_t::swj
uint32_t swj
Definition: mcp251863.h:1418
mcp251863_oscillator_control_object_reset
void mcp251863_oscillator_control_object_reset(mcp251863_div_ctl_t *ctrl)
Reset Oscillator Control.
mcp251863_div_ctl_t
MCP251863 Click Oscillator Control.
Definition: mcp251863.h:1244
mcp251863_trec_t::tx_error_state_passive
uint32_t tx_error_state_passive
Definition: mcp251863.h:1592
mcp251863_tx_msg_obj_ctl_t::seq
uint32_t seq
Definition: mcp251863.h:935
T_MCP251863_cfg_t::system_error_to_listen_only
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1319
mcp251863_bus_diag_t::error_count
mcp251863_bus_error_count_t error_count
Definition: mcp251863.h:1771
mcp251863_fifo_ctl_t::tx_empty_ie
uint32_t tx_empty_ie
Definition: mcp251863.h:1177
mcp251863_ctl_t::system_error_to_listen_only
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1083
mcp251863_ecc_sta_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1705
mcp251863_osc_sta_t::sclk_ready
uint32_t sclk_ready
Definition: mcp251863.h:1722
mcp251863_calculate_crc16
uint16_t mcp251863_calculate_crc16(uint8_t *data_pointer, uint16_t size)
Calculate CRC16.
mcp251863_module_event_icode_get
err_t mcp251863_module_event_icode_get(mcp251863_t *ctx, uint8_t *icode)
Get ICODE.
mcp251863_fifo_ctl_t::rx_half_full_ie
uint32_t rx_half_full_ie
Definition: mcp251863.h:1159
mcp251863_tx_fifo_cfg_t
MCP251863 Click CAN Transmit Channel Configure.
Definition: mcp251863.h:1331
mcp251863_crc_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1688
mcp251863_div_ctl_t::clk_out_divide
uint32_t clk_out_divide
Definition: mcp251863.h:1248
mcp251863_io_ctl_t::sof_output_enable
uint32_t sof_output_enable
Definition: mcp251863.h:1277
mcp251863_rx_msg_obj_ctl_t::fdf
uint32_t fdf
Definition: mcp251863.h:966
mcp251863_ts_cfg_t
MCP251863 Click Time Stamp Configuration Register.
Definition: mcp251863.h:1458
mcp251863_filt_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1206
mcp251863_ecc_error_address_get
err_t mcp251863_ecc_error_address_get(mcp251863_t *ctx, uint16_t *address)
Get ECC Error Address.
mcp251863_nbt_cfg_t::tseg2
uint32_t tseg2
Definition: mcp251863.h:1401
mcp251863_tx_que_stat_t::fifo_index
uint32_t fifo_index
Definition: mcp251863.h:1634
mcp251863_rx_msg_obj_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:970
mcp251863_osc_ctl_t::pll_enable
uint32_t pll_enable
Definition: mcp251863.h:1220
mcp251863_int_vec_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1515
mcp251863_ecc_ctl_t::ecc_en
uint32_t ecc_en
Definition: mcp251863.h:1293
mcp251863_ctl_t::restrict_re_tx_attempts
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1081
mcp251863_module_event_tx_code_get
err_t mcp251863_module_event_tx_code_get(mcp251863_t *ctx, uint8_t *tx_code)
Get TX Code.
mcp251863_bus_diag_flags_t::n_bit0_err
uint32_t n_bit0_err
Definition: mcp251863.h:1732
mcp251863_ctl_t::wake_up_filter_enable
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1076
mcp251863_int_t::word
uint32_t word
Definition: mcp251863.h:1574
mcp251863_data_t::tx_flags
uint8_t tx_flags
Definition: mcp251863.h:1848
mcp251863_fifo_user_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1374
mcp251863_dbt_cfg_t
MCP251863 Click Data Bit Time Configuration Register.
Definition: mcp251863.h:1416
mcp251863_config_t::rx_pay_load_size
uint8_t rx_pay_load_size
Definition: mcp251863.h:887
mcp251863_div_ctl_t::osc_disable
uint32_t osc_disable
Definition: mcp251863.h:1246
mcp251863_func_data_t::address
uint16_t address
Definition: mcp251863.h:1833
mcp251863_tef_status_get
err_t mcp251863_tef_status_get(mcp251863_t *ctx, uint8_t *status)
Transmit Event FIFO Status Get.
mcp251863_tef_ctl_t::freset
uint32_t freset
Definition: mcp251863.h:1141
mcp251863_transmit_request_set
err_t mcp251863_transmit_request_set(mcp251863_t *ctx, uint32_t tx_req)
Request transmissions using TXREQ register.
mcp251863_t::stby
digital_out_t stby
Definition: mcp251863.h:1874
mcp251863_fifo_user_cfg_t
MCP251863 Click FIFO User Address Register.
Definition: mcp251863.h:1371
mcp251863_time_stamp_enable
err_t mcp251863_time_stamp_enable(mcp251863_t *ctx)
Time Stamp Enable.
mcp251863_transmit_channel_event_enable
err_t mcp251863_transmit_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Enable.
mcp251863_mask_obj_id_t
MCP251863 Click CAN Mask Object ID.
Definition: mcp251863.h:1037
mcp251863_io_ctl_t
MCP251863 Click I/O Control Register.
Definition: mcp251863.h:1257
spi_specifics.h
This file contains SPI specific macros, functions, etc.
mcp251863_tef_ctl_t::word
uint32_t word
Definition: mcp251863.h:1146
mcp251863_can_cfg_t::esi_in_gateway_mode
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:867
mcp251863_tef_msg_obj_t::ctrl
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:998
mcp251863_read_half_word
err_t mcp251863_read_half_word(mcp251863_t *ctx, uint16_t address, uint16_t *data_out)
SPI Read Half Word.
mcp251863_bit_time_configure_nominal_10_mhz
err_t mcp251863_bit_time_configure_nominal_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 10MHz system clock.
mcp251863_ecc_event_disable
err_t mcp251863_ecc_event_disable(mcp251863_t *ctx, uint8_t flags)
ECC Event Disable.
mcp251863_gpio_clock_output_configure
err_t mcp251863_gpio_clock_output_configure(mcp251863_t *ctx, int8_t mode)
Configure CLKO Pin.
mcp251863_rx_msg_obj_ctl_t::filter_hit
uint32_t filter_hit
Definition: mcp251863.h:969
mcp251863_tx_que_ctl_t
MCP251863 Click Transmit Queue Control Register.
Definition: mcp251863.h:1101
mcp251863_ecc_ctl_t::word
uint32_t word
Definition: mcp251863.h:1300
mcp251863_data_t::rec
uint8_t rec
Definition: mcp251863.h:1852
mcp251863_int_flags_stat_t::CERRIF
uint32_t CERRIF
Definition: mcp251863.h:1546
mcp251863_bus_diag_flags_t::txbo_err
uint32_t txbo_err
Definition: mcp251863.h:1739
mcp251863_io_ctl_t::lat0
uint32_t lat0
Definition: mcp251863.h:1266
mcp251863_ctl_t::tx_band_width_sharing
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1089
mcp251863_tef_msg_obj_t::time_stamp
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:999
mcp251863_fifo_ctl_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1170
mcp251863_osc_ctl_t::word
uint32_t word
Definition: mcp251863.h:1234
MCP251863_OK
@ MCP251863_OK
Definition: mcp251863.h:1920
mcp251863_tx_que_ctl_t::uinc
uint32_t uinc
Definition: mcp251863.h:1110
mcp251863_transmit_band_width_sharing_set
err_t mcp251863_transmit_band_width_sharing_set(mcp251863_t *ctx, uint8_t tx_bws)
Set Transmit Bandwidth Sharing Delay.
mcp251863_int_en_t::rxie
uint32_t rxie
Definition: mcp251863.h:1478
mcp251863_tx_que_ctl_t::tx_empty_ie
uint32_t tx_empty_ie
Definition: mcp251863.h:1105
mcp251863_write_byte_safe
err_t mcp251863_write_byte_safe(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI SFR Write Byte Safe.
mcp251863_int_cfg_t
MCP251863 Click Interrupt Configuration.
Definition: mcp251863.h:1500
mcp251863_rx_msg_obj_ctl_t::brs
uint32_t brs
Definition: mcp251863.h:965
mcp251863_bus_diag0_t::word
uint32_t word
Definition: mcp251863.h:1792
mcp251863_ts_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1461
mcp251863_transmit_channel_update
err_t mcp251863_transmit_channel_update(mcp251863_t *ctx, uint8_t channel, bool flush)
Transmit FIFO Update.
mcp251863_rx_msg_obj_ctl_t::esi
uint32_t esi
Definition: mcp251863.h:967
mcp251863_config_t::ide
uint8_t ide
Definition: mcp251863.h:892
mcp251863_filter_object_configure
err_t mcp251863_filter_object_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_filt_obj_id_t *id)
Filter Object Configuration.
mcp251863_tef_t
MCP251863 Click Transmit Event FIFO Status Register.
Definition: mcp251863.h:1606
mcp251863_trec_t::rx_error_count
uint32_t rx_error_count
Definition: mcp251863.h:1586
mcp251863_int_flags_stat_t::TBCIF
uint32_t TBCIF
Definition: mcp251863.h:1536
mcp251863_t::spi
spi_master_t spi
Definition: mcp251863.h:1881
mcp251863_ecc_sta_t
MCP251863 Click ECC Status Register.
Definition: mcp251863.h:1700
mcp251863_time_stamp_disable
err_t mcp251863_time_stamp_disable(mcp251863_t *ctx)
Time Stamp Disable.
mcp251863_fifo_ctl_t::tx_attempt_ie
uint32_t tx_attempt_ie
Definition: mcp251863.h:1179
mcp251863_error_count_transmit_get
err_t mcp251863_error_count_transmit_get(mcp251863_t *ctx, uint8_t *tec)
Transmit Error Count Get.
mcp251863_dbt_cfg_t::tseg2
uint32_t tseg2
Definition: mcp251863.h:1420
mcp251863_osc_ctl_t
MCP251863 Click Oscillator Control Register.
Definition: mcp251863.h:1218
mcp251863_crc_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1685
mcp251863_filt_ctl_t
MCP251863 Click Filter Control Register.
Definition: mcp251863.h:1203
mcp251863_osc_ctl_t::osc_disable
uint32_t osc_disable
Definition: mcp251863.h:1222
mcp251863_write_word
err_t mcp251863_write_word(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI Write Word.
mcp251863_tx_que_ctl_t::tx_not_full_ie
uint32_t tx_not_full_ie
Definition: mcp251863.h:1103
mcp251863_osc_ctl_t::sclk_divide
uint32_t sclk_divide
Definition: mcp251863.h:1224
mcp251863_osc_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1223
mcp251863_tx_que_cfg_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1347
mcp251863_tef_ctl_t::tefneie
uint32_t tefneie
Definition: mcp251863.h:1132
mcp251863_tx_msg_obj_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:936
mcp251863_bus_diag1_t::n_form_error
uint32_t n_form_error
Definition: mcp251863.h:1808
mcp251863_bus_diag_flags_t::esi
uint32_t esi
Definition: mcp251863.h:1746
mcp251863_trec_t::rx_error_state_warning
uint32_t rx_error_state_warning
Definition: mcp251863.h:1589
mcp251863_data_t::rx_config
mcp251863_rx_fifo_cfg_t rx_config
Definition: mcp251863.h:1858
mcp251863_tx_que_ctl_t::word
uint32_t word
Definition: mcp251863.h:1120
mcp251863_dbt_cfg_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1423
mcp251863_time_stamp_set
err_t mcp251863_time_stamp_set(mcp251863_t *ctx, uint32_t ts)
Time Stamp Set.
mcp251863_crc_t::word
uint32_t word
Definition: mcp251863.h:1690
mcp251863_ts_cfg_t::word
uint32_t word
Definition: mcp251863.h:1466
mcp251863_bus_diag1_t::d_bit1_error
uint32_t d_bit1_error
Definition: mcp251863.h:1814
mcp251863_msg_time_stamp_t
uint32_t mcp251863_msg_time_stamp_t
MCP251863 Click CAN Message Time Stamp.
Definition: mcp251863.h:908
mcp251863_transmit_channel_index_get
err_t mcp251863_transmit_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Transmit FIFO Index Get.
mcp251863_data_t::m_obj
mcp251863_mask_obj_t m_obj
Definition: mcp251863.h:1862
mcp251863_transmit_event_get
err_t mcp251863_transmit_event_get(mcp251863_t *ctx, uint32_t *txif)
Get pending interrupts of all transmit FIFOs.
mcp251863_ctl_t::d_net_filter_count
uint32_t d_net_filter_count
Definition: mcp251863.h:1072
T_MCP251863_cfg_t::restrict_re_tx_attempts
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1317
mcp251863_tdc_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1439
mcp251863_data_bytes_to_dlc
uint8_t mcp251863_data_bytes_to_dlc(uint8_t num)
Data bytes to DLC conversion.
mcp251863_configure_object_reset
void mcp251863_configure_object_reset(mcp251863_can_cfg_t *config)
Reset Configure object to reset values.
mcp251863_data_t::bus_diagnostics
mcp251863_bus_diag_t bus_diagnostics
Definition: mcp251863.h:1863
mcp251863_generic_write
err_t mcp251863_generic_write(mcp251863_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
MCP251863 data writing function.
mcp251863_reg_t
Definition: mcp251863.h:1059
mcp251863_osc_ctl_t::pll_ready
uint32_t pll_ready
Definition: mcp251863.h:1227
mcp251863_fifo_stat_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1655
mcp251863_write_byte_array
err_t mcp251863_write_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_in, uint16_t n_bytes)
SPI Write Byte Array.
mcp251863_bit_time_configure_data_20_mhz
err_t mcp251863_bit_time_configure_data_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.
mcp251863_filt_obj_id_t::sid
uint32_t sid
Definition: mcp251863.h:1012
mcp251863_fifo_ctl_t::tx_not_full_ie
uint32_t tx_not_full_ie
Definition: mcp251863.h:1175
mcp251863_osc_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1228
mcp251863_io_ctl_t::clear_auto_sleep_on_match
uint32_t clear_auto_sleep_on_match
Definition: mcp251863.h:1262
mcp251863_t::func_data
mcp251863_func_data_t func_data
Definition: mcp251863.h:1886
mcp251863_bus_diag_flags_t::n_ack_err
uint32_t n_ack_err
Definition: mcp251863.h:1734
mcp251863_bus_diag1_t::n_crc_error
uint32_t n_crc_error
Definition: mcp251863.h:1810
mcp251863_fifo_ctl_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1188
mcp251863_ctl_t::iso_crc_enable
uint32_t iso_crc_enable
Definition: mcp251863.h:1073
mcp251863_bus_diag0_t::n_tx_error_count
uint32_t n_tx_error_count
Definition: mcp251863.h:1788
mcp251863_int_flag_t
MCP251863 Click Interrupt Flag Register.
Definition: mcp251863.h:1557
mcp251863_func_data_t::rxd
uint8_t * rxd
Definition: mcp251863.h:1834
mcp251863_tx_msg_obj_ctl_t::esi
uint32_t esi
Definition: mcp251863.h:934
mcp251863_bus_diag_flags_t::n_form_err
uint32_t n_form_err
Definition: mcp251863.h:1735
mcp251863_fifo_ctl_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1187
mcp251863_int_flags_stat_t::IVMIF
uint32_t IVMIF
Definition: mcp251863.h:1548
mcp251863_tx_msg_obj_t::time_stamp
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:949
mcp251863_bus_diag_flags_t::dlc_mismatch
uint32_t dlc_mismatch
Definition: mcp251863.h:1747
mcp251863_tef_cfg_t::time_stamp_enable
uint32_t time_stamp_enable
Definition: mcp251863.h:1387
mcp251863_mask_obj_t::bf
mcp251863_mask_obj_id_t bf
Definition: mcp251863.h:1052
mcp251863_msg_obj_id_t::sid11
uint32_t sid11
Definition: mcp251863.h:918
mcp251863_mask_obj_id_t::msid
uint32_t msid
Definition: mcp251863.h:1038
mcp251863_bus_diag_flags_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1738
mcp251863_mask_obj_id_t::msid11
uint32_t msid11
Definition: mcp251863.h:1040
mcp251863_tx_que_ctl_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1118
MCP251863_ERROR
@ MCP251863_ERROR
Definition: mcp251863.h:1921
mcp251863_ctl_t::request_op_mode
uint32_t request_op_mode
Definition: mcp251863.h:1087
mcp251863_dbt_cfg_t::tseg1
uint32_t tseg1
Definition: mcp251863.h:1422
mcp251863_transmit_channel_event_disable
err_t mcp251863_transmit_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Disable.
mcp251863_fifo_ctl_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1171
mcp251863_fifo_ctl_t::uinc
uint32_t uinc
Definition: mcp251863.h:1166
mcp251863_tx_que_cfg_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1349
mcp251863_int_vec_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1519
mcp251863_bus_diag_flags_t::d_bit1_err
uint32_t d_bit1_err
Definition: mcp251863.h:1741
mcp251863_tdc_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1441
mcp251863_receive_channel_index_get
int8_t mcp251863_receive_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Receive FIFO Index Get.
mcp251863_int_en_t::txie
uint32_t txie
Definition: mcp251863.h:1477
mcp251863_io_ctl_t::lat1
uint32_t lat1
Definition: mcp251863.h:1267
mcp251863_osc_ctl_t::osc_ready
uint32_t osc_ready
Definition: mcp251863.h:1229
mcp251863_int_flag_t::word
uint16_t word
Definition: mcp251863.h:1559
mcp251863_ctl_t::bit_rate_switch_disable
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1079
mcp251863_filt_ctl_t::buffer_pointer
uint32_t buffer_pointer
Definition: mcp251863.h:1205
mcp251863_bus_diag_flags_t::d_bit0_err
uint32_t d_bit0_err
Definition: mcp251863.h:1740
mcp251863_receive_channel_reset
err_t mcp251863_receive_channel_reset(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Reset.
mcp251863_tx_fifo_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1335
mcp251863_configure
err_t mcp251863_configure(mcp251863_t *ctx, mcp251863_can_cfg_t *config)
CAN Control register configuration.
mcp251863_int_en_t::tbcie
uint32_t tbcie
Definition: mcp251863.h:1479
mcp251863_reset
err_t mcp251863_reset(mcp251863_t *ctx)
Reset function.
mcp251863_int_flags_stat_t::SPICRCIF
uint32_t SPICRCIF
Definition: mcp251863.h:1542
mcp251863_div_ctl_t::pll_enable
uint32_t pll_enable
Definition: mcp251863.h:1245
mcp251863_filt_obj_id_t::exide
uint32_t exide
Definition: mcp251863.h:1015
mcp251863_tef_event_overflow_clear
err_t mcp251863_tef_event_overflow_clear(mcp251863_t *ctx)
Transmit Event FIFO Event Clear.
mcp251863_ecc_sta_t::word
uint32_t word
Definition: mcp251863.h:1709
mcp251863_read_byte_array_with_crc
err_t mcp251863_read_byte_array_with_crc(mcp251863_t *ctx, bool from_ram, bool *crc_is_correct)
SPI Read Byte Array with CRC.
mcp251863_bus_diagnostics_get
err_t mcp251863_bus_diagnostics_get(mcp251863_t *ctx, mcp251863_bus_diag_t *bus_diag)
Get Bus Diagnostic Registers: all data_ at once, since we want to keep them in synch.
mcp251863_cfg_t::cs
pin_name_t cs
Definition: mcp251863.h:1900
mcp251863_ts_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1464
mcp251863_fifo_user_cfg_t::word
uint32_t word
Definition: mcp251863.h:1376
mcp251863_nbt_cfg_t::tseg1
uint32_t tseg1
Definition: mcp251863.h:1403
mcp251863_config_t::iso_crc_enable
uint8_t iso_crc_enable
Definition: mcp251863.h:881
mcp251863_io_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1265
mcp251863_tef_t::tef_not_empty_if
uint32_t tef_not_empty_if
Definition: mcp251863.h:1608
mcp251863_int_vec_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1521
mcp251863_bus_diag1_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1820
mcp251863_tef_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1140
mcp251863_transmit_message
err_t mcp251863_transmit_message(mcp251863_t *ctx, uint8_t *data_in, uint16_t data_len)
Message Transmit function.
mcp251863_tx_fifo_cfg_t::rtr_enable
uint32_t rtr_enable
Definition: mcp251863.h:1332
mcp251863_tef_configure
err_t mcp251863_tef_configure(mcp251863_t *ctx, mcp251863_tef_cfg_t *config)
Configure Transmit Event FIFO.
mcp251863_int_en_t::spicrcie
uint32_t spicrcie
Definition: mcp251863.h:1485
mcp251863_fifo_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1162
mcp251863_filt_ctl_t::enable
uint32_t enable
Definition: mcp251863.h:1207
mcp251863_filt_obj_id_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1016
mcp251863_tef_msg_obj_t
MCP251863 Click CAN TEF Message Object.
Definition: mcp251863.h:995
mcp251863_filter_mask_configure
err_t mcp251863_filter_mask_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_mask_obj_id_t *mask)
Filter Mask Configuration.
mcp251863_tdc_cfg_t::tdc_offset
uint32_t tdc_offset
Definition: mcp251863.h:1440
mcp251863_int_en_t::eccie
uint32_t eccie
Definition: mcp251863.h:1484
mcp251863_tx_que_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1106
mcp251863_config_t::remote_frame_req
uint8_t remote_frame_req
Definition: mcp251863.h:893
mcp251863_osc_sta_t::osc_ready
uint32_t osc_ready
Definition: mcp251863.h:1721
mcp251863_bus_diag1_t::txbo_error
uint32_t txbo_error
Definition: mcp251863.h:1812
mcp251863_div_ctl_t::sclk_divide
uint32_t sclk_divide
Definition: mcp251863.h:1247
mcp251863_fifo_stat_t::tx_attempt_if
uint32_t tx_attempt_if
Definition: mcp251863.h:1663
mcp251863_osc_ctl_t::clk_out_divide
uint32_t clk_out_divide
Definition: mcp251863.h:1225
mcp251863_reg_t::word
uint32_t word
Definition: mcp251863.h:1061
mcp251863_gpio_mode_configure
err_t mcp251863_gpio_mode_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Mode.
mcp251863_fifo_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1169
mcp251863_io_ctl_t::pin_mode1
uint32_t pin_mode1
Definition: mcp251863.h:1274
mcp251863_t::int_pin
digital_in_t int_pin
Definition: mcp251863.h:1878
mcp251863_msg_obj_id_t::eid
uint32_t eid
Definition: mcp251863.h:917
mcp251863_gpio_pin_read
err_t mcp251863_gpio_pin_read(mcp251863_t *ctx, uint8_t pos, uint8_t *state)
Input Pin Read.
mcp251863_can_cfg_t::wake_up_filter_time
uint32_t wake_up_filter_time
Definition: mcp251863.h:864
mcp251863_filt_obj_id_t::eid
uint32_t eid
Definition: mcp251863.h:1013
mcp251863_tx_que_stat_t
MCP251863 Click Transmit Queue Status Register.
Definition: mcp251863.h:1624
mcp251863_transmit_queue_configure_object_reset
void mcp251863_transmit_queue_configure_object_reset(mcp251863_tx_que_cfg_t *config)
Reset Transmit Queue Configure object to reset values.
mcp251863_msg_obj_id_t
MCP251863 Click CAN Message Object ID.
Definition: mcp251863.h:915
mcp251863_tdc_cfg_t::sid11_enable
uint32_t sid11_enable
Definition: mcp251863.h:1444
mcp251863_io_ctl_t::gpio0
uint32_t gpio0
Definition: mcp251863.h:1270
mcp251863_dlc_to_data_bytes
uint32_t mcp251863_dlc_to_data_bytes(uint8_t dlc)
DLC to number of actual data_bytes conversion.
T_MCP251863_cfg_t::esi_in_gateway_mode
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1318
mcp251863_fifo_stat_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1653
mcp251863_msg_obj_id_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:919
mcp251863_rx_fifo_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1360
mcp251863_can_cfg_t
MCP251863 Click CAN Configure.
Definition: mcp251863.h:859
mcp251863_receive_channel_event_enable
err_t mcp251863_receive_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Enable.
mcp251863_can_cfg_t::system_error_to_listen_only
uint32_t system_error_to_listen_only
Definition: mcp251863.h:868
mcp251863_receive_message_get
err_t mcp251863_receive_message_get(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_msg_obj_t *rx_obj)
Get Received Message.
mcp251863_io_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1272
mcp251863_tx_que_ctl_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1117
mcp251863_tef_reset
err_t mcp251863_tef_reset(mcp251863_t *ctx)
Transmit Event FIFO Reset.
mcp251863_transmit_abort_all
err_t mcp251863_transmit_abort_all(mcp251863_t *ctx)
Abort All transmissions.
mcp251863_int_vec_t::icode
uint32_t icode
Definition: mcp251863.h:1514
mcp251863_time_stamp_get
err_t mcp251863_time_stamp_get(mcp251863_t *ctx, uint32_t *time_stamp)
Time Stamp Get.
mcp251863_data_t::config
mcp251863_can_cfg_t config
Definition: mcp251863.h:1856
mcp251863_filt_obj_t::word
uint32_t word
Definition: mcp251863.h:1027
T_MCP251863_cfg_t::wake_up_filter_enable
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1314
mcp251863_int_flags_stat_t
MCP251863 Click Interrupt Flags.
Definition: mcp251863.h:1533
mcp251863_bus_diag_flags_t::d_form_err
uint32_t d_form_err
Definition: mcp251863.h:1743
mcp251863_int_en_t
MCP251863 Click Interrupt Enables.
Definition: mcp251863.h:1476
mcp251863_tx_msg_obj_ctl_t
MCP251863 Click CAN TX Message Object Control.
Definition: mcp251863.h:928
mcp251863_trec_t::word
uint32_t word
Definition: mcp251863.h:1596
mcp251863_read_word_array
err_t mcp251863_read_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_out, uint16_t n_words)
SPI Read Word Array.
mcp251863_osc_sta_t
MCP251863 Click Oscillator Status.
Definition: mcp251863.h:1719
mcp251863_data_t::rx_obj
mcp251863_rx_msg_obj_t rx_obj
Definition: mcp251863.h:1860
T_MCP251863_cfg_t::txq_enable
uint32_t txq_enable
Definition: mcp251863.h:1321
mcp251863_tx_que_cfg_t
MCP251863 Click CAN Transmit Queue Configure.
Definition: mcp251863.h:1345
mcp251863_int_en_t::tefie
uint32_t tefie
Definition: mcp251863.h:1481
mcp251863_data_t::tx_obj
mcp251863_tx_msg_obj_t tx_obj
Definition: mcp251863.h:1859
mcp251863_receive_channel_configure_object_reset
void mcp251863_receive_channel_configure_object_reset(mcp251863_rx_fifo_cfg_t *config)
Reset Receive Channel Configure object to reset value.
mcp251863_tx_que_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1108
mcp251863_tx_msg_obj_ctl_t::brs
uint32_t brs
Definition: mcp251863.h:932
mcp251863_transmit_channel_status_get
err_t mcp251863_transmit_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint16_t *status)
Transmit Channel Status Get.
mcp251863_int_flags_stat_t::RXIF
uint32_t RXIF
Definition: mcp251863.h:1535
mcp251863_fifo_index_get
err_t mcp251863_fifo_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *data_out)
FIFO Index Get.
mcp251863_cfg_t::stby
pin_name_t stby
Definition: mcp251863.h:1903
mcp251863_int_vec_t::filter_hit
uint32_t filter_hit
Definition: mcp251863.h:1516
mcp251863_config_t
MCP251863 Click CAN Message Configuration.
Definition: mcp251863.h:880
mcp251863_tx_msg_obj_ctl_t::ide
uint32_t ide
Definition: mcp251863.h:930
mcp251863_transmit_channel_configure_object_reset
void mcp251863_transmit_channel_configure_object_reset(mcp251863_tx_fifo_cfg_t *config)
Reset Transmit Channel Configure object to reset values.
mcp251863_func_data_t::txd_num_bytes
uint32_t txd_num_bytes
Definition: mcp251863.h:1837
mcp251863_gpio_direction_configure
err_t mcp251863_gpio_direction_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Direction.
mcp251863_tef_ctl_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1143
mcp251863_cfg_setup
void mcp251863_cfg_setup(mcp251863_cfg_t *cfg)
MCP251863 configuration object setup function.
mcp251863_filter_enable
err_t mcp251863_filter_enable(mcp251863_t *ctx, uint8_t filter)
Filter Enable.
mcp251863_ecc_parity_set
err_t mcp251863_ecc_parity_set(mcp251863_t *ctx, uint8_t parity)
Set ECC Parity.
mcp251863_can_cfg_t::iso_crc_enable
uint32_t iso_crc_enable
Definition: mcp251863.h:861
mcp251863_mask_obj_id_t::mide
uint32_t mide
Definition: mcp251863.h:1041
mcp251863_trec_t::tx_error_count
uint32_t tx_error_count
Definition: mcp251863.h:1587
mcp251863_int_en_t::rxovie
uint32_t rxovie
Definition: mcp251863.h:1487
mcp251863_tx_que_stat_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1627
mcp251863_default_cfg
err_t mcp251863_default_cfg(mcp251863_t *ctx)
MCP251863 default configuration function.
mcp251863_tdc_cfg_t
MCP251863 Click Transmitter Delay Compensation Register.
Definition: mcp251863.h:1436
mcp251863_filt_obj_id_t
MCP251863 Click CAN Filter Object ID.
Definition: mcp251863.h:1011
mcp251863_tx_que_stat_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1635
mcp251863_int_en_t::wakie
uint32_t wakie
Definition: mcp251863.h:1490
mcp251863_config_t::store_in_tef
uint8_t store_in_tef
Definition: mcp251863.h:882
mcp251863_int_flags_stat_t::ECCIF
uint32_t ECCIF
Definition: mcp251863.h:1541
mcp251863_tef_t::tef_ov_if
uint32_t tef_ov_if
Definition: mcp251863.h:1611
mcp251863_can_cfg_t::txq_enable
uint32_t txq_enable
Definition: mcp251863.h:870
mcp251863_dbt_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1421
mcp251863_tef_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1612
mcp251863_bus_diag1_t::d_crc_error
uint32_t d_crc_error
Definition: mcp251863.h:1818
mcp251863_ecc_sta_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1707
mcp251863_fifo_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1167
mcp251863_receive_message
err_t mcp251863_receive_message(mcp251863_t *ctx, uint8_t *data_out, uint16_t *data_len)
Message Receive function.
mcp251863_int_t::if_stat
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1571
mcp251863_fifo_stat_t::tx_half_full_if
uint32_t tx_half_full_if
Definition: mcp251863.h:1660
mcp251863_config_t::rx_fifo_size
uint8_t rx_fifo_size
Definition: mcp251863.h:886
mcp251863_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1078
mcp251863_nbt_cfg_t
MCP251863 Click Nominal Bit Time Configuration Register.
Definition: mcp251863.h:1397
mcp251863_fifo_ctl_t::rx_full_ie
uint32_t rx_full_ie
Definition: mcp251863.h:1160
mcp251863_operation_mode_get
err_t mcp251863_operation_mode_get(mcp251863_t *ctx)
Get Operation Mode.
T_MCP251863_cfg_t
MCP251863 Click CAN Configure.
Definition: mcp251863.h:1310
mcp251863_bus_error_count_t::n_tec
uint8_t n_tec
Definition: mcp251863.h:1758
mcp251863_return_value_t
mcp251863_return_value_t
MCP251863 Click return value data.
Definition: mcp251863.h:1919
mcp251863_tx_que_stat_t::word
uint32_t word
Definition: mcp251863.h:1637
mcp251863_io_ctl_t::hvdetsel
uint32_t hvdetsel
Definition: mcp251863.h:1269
mcp251863_config_t::extended_id
uint32_t extended_id
Definition: mcp251863.h:889
mcp251863_tx_que_stat_t::tx_attempt_if
uint32_t tx_attempt_if
Definition: mcp251863.h:1630
mcp251863_bus_diag_flags_t::n_bit1_err
uint32_t n_bit1_err
Definition: mcp251863.h:1733
mcp251863_tef_msg_obj_t::id
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:997
mcp251863_transmit_channel_configure
err_t mcp251863_transmit_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_fifo_cfg_t *config)
Configure Transmit FIFO.
mcp251863_tx_que_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1113
mcp251863_nbt_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1402
mcp251863_int_t
MCP251863 Click Interrupt Register.
Definition: mcp251863.h:1569
mcp251863_io_ctl_t::int_pin_open_drain
uint32_t int_pin_open_drain
Definition: mcp251863.h:1278
mcp251863_ram_init
err_t mcp251863_ram_init(mcp251863_t *ctx, uint8_t rx_data)
Initialize RAM.
mcp251863_ecc_sta_t::secif
uint32_t secif
Definition: mcp251863.h:1703
mcp251863_trec_t::tx_error_state_bus_off
uint32_t tx_error_state_bus_off
Definition: mcp251863.h:1593
mcp251863_transmit_channel_reset
int8_t mcp251863_transmit_channel_reset(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Reset.
mcp251863_ts_cfg_t::tbc_prescaler
uint32_t tbc_prescaler
Definition: mcp251863.h:1460
mcp251863_int_vec_t::tx_code
uint32_t tx_code
Definition: mcp251863.h:1518
mcp251863_id_t
uint8_t mcp251863_id_t
MCP251863 Click Module ID.
Definition: mcp251863.h:902
mcp251863_ecc_sta_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1702
mcp251863_fifo_stat_t::rx_not_empty_if
uint32_t rx_not_empty_if
Definition: mcp251863.h:1649
mcp251863_int_vec_t::rx_code
uint32_t rx_code
Definition: mcp251863.h:1520
mcp251863_crc_event_get
err_t mcp251863_crc_event_get(mcp251863_t *ctx, uint8_t *flags)
CRC Event Get.
mcp251863_func_data_t::txd
uint8_t * txd
Definition: mcp251863.h:1836
mcp251863_crc_event_clear
err_t mcp251863_crc_event_clear(mcp251863_t *ctx, uint8_t flags)
CRC Event Clear.
mcp251863_data_t::f_obj
mcp251863_filt_obj_t f_obj
Definition: mcp251863.h:1861
mcp251863_t::chip_select
pin_name_t chip_select
Definition: mcp251863.h:1883
mcp251863_tdc_cfg_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1443
mcp251863_int_vec_t::word
uint32_t word
Definition: mcp251863.h:1523
mcp251863_ctl_t::word
uint32_t word
Definition: mcp251863.h:1091
mcp251863_cfg_t::int_pin
pin_name_t int_pin
Definition: mcp251863.h:1905
mcp251863_tx_que_stat_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1629
mcp251863_fifo_stat_t::tx_error
uint32_t tx_error
Definition: mcp251863.h:1664
mcp251863_tef_t::tef_half_full_if
uint32_t tef_half_full_if
Definition: mcp251863.h:1609
mcp251863_bus_diag1_t::d_stuff_error
uint32_t d_stuff_error
Definition: mcp251863.h:1817
mcp251863_int_flags_stat_t::WAKIF
uint32_t WAKIF
Definition: mcp251863.h:1547
mcp251863_write_word_array
err_t mcp251863_write_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_in, uint16_t n_words)
SPI Write Word Array.
mcp251863_config_t::seq
uint8_t seq
Definition: mcp251863.h:894
mcp251863_time_stamp_mode_configure
err_t mcp251863_time_stamp_mode_configure(mcp251863_t *ctx, uint8_t mode)
Time Stamp Mode Configure.
mcp251863_tef_configure_object_reset
void mcp251863_tef_configure_object_reset(mcp251863_tef_cfg_t *config)
Reset TefConfigure object to reset value.
mcp251863_func_data_t
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1832
mcp251863_bus_diag1_t::error_free_msg_count
uint32_t error_free_msg_count
Definition: mcp251863.h:1804
mcp251863_fifo_stat_t
MCP251863 Click FIFO Status Register.
Definition: mcp251863.h:1647
mcp251863_filt_obj_id_t::sid11
uint32_t sid11
Definition: mcp251863.h:1014
mcp251863_tdc_cfg_t::edge_filter_enable
uint32_t edge_filter_enable
Definition: mcp251863.h:1445
mcp251863_tx_que_ctl_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1114
mcp251863_crc_event_disable
err_t mcp251863_crc_event_disable(mcp251863_t *ctx, uint8_t flags)
CRC Event Disnable.
mcp251863_data_t::rx_flags
uint8_t rx_flags
Definition: mcp251863.h:1849
mcp251863_osc_ctl_t::sclk_ready
uint32_t sclk_ready
Definition: mcp251863.h:1231
mcp251863_fifo_ctl_t::rx_time_stamp_enable
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1163
mcp251863_int_flags_stat_t::SERRIF
uint32_t SERRIF
Definition: mcp251863.h:1545
mcp251863_bus_diag1_t::word
uint32_t word
Definition: mcp251863.h:1822
mcp251863_transmit_event_attempt_get
err_t mcp251863_transmit_event_attempt_get(mcp251863_t *ctx, uint32_t *txatif)
Get pending TXATIF of all transmit FIFOs.
mcp251863_fifo_stat_t::tx_aborted
uint32_t tx_aborted
Definition: mcp251863.h:1666
mcp251863_ctl_t::txq_enable
uint32_t txq_enable
Definition: mcp251863.h:1085
mcp251863_ecc_ctl_t::parity
uint32_t parity
Definition: mcp251863.h:1297
mcp251863_int_vec_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1517
mcp251863_data_t
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1846
mcp251863_tx_que_cfg_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1346
mcp251863_crc_t::crcerrif
uint32_t crcerrif
Definition: mcp251863.h:1683
mcp251863_bus_diagnostics_clear
err_t mcp251863_bus_diagnostics_clear(mcp251863_t *ctx)
Clear Bus Diagnostic Registers.
mcp251863_rx_msg_obj_ctl_t::rtr
uint32_t rtr
Definition: mcp251863.h:964
T_MCP251863_cfg_t::store_in_tef
uint32_t store_in_tef
Definition: mcp251863.h:1320
mcp251863_ctl_t::store_in_tef
uint32_t store_in_tef
Definition: mcp251863.h:1084
mcp251863_tef_ctl_t::time_stamp_enable
uint32_t time_stamp_enable
Definition: mcp251863.h:1137
mcp251863_fifo_ctl_t::rx_not_empty_ie
uint32_t rx_not_empty_ie
Definition: mcp251863.h:1158
mcp251863_bit_time_configure_nominal_40_mhz
err_t mcp251863_bit_time_configure_nominal_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 40MHz system clock.
mcp251863_config_t::switch_bit_rate
uint8_t switch_bit_rate
Definition: mcp251863.h:891
mcp251863_osc_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1221
mcp251863_ctl_t::op_mode
uint32_t op_mode
Definition: mcp251863.h:1086
mcp251863_ctl_t::abort_all_tx
uint32_t abort_all_tx
Definition: mcp251863.h:1088
mcp251863_io_ctl_t::tris1
uint32_t tris1
Definition: mcp251863.h:1260
mcp251863_tdc_cfg_t::tdc_value
uint32_t tdc_value
Definition: mcp251863.h:1438
mcp251863_operation_mode_select
err_t mcp251863_operation_mode_select(mcp251863_t *ctx, uint8_t op_mode)
Select Operation Mode.
mcp251863_tef_cfg_t
MCP251863 Click CAN Transmit Event FIFO Configure.
Definition: mcp251863.h:1386
mcp251863_receive_channel_event_get
err_t mcp251863_receive_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Receive FIFO Event Get.
mcp251863_rx_msg_obj_ctl_t::dlc
uint32_t dlc
Definition: mcp251863.h:962
mcp251863_fifo_stat_t::tx_empty_if
uint32_t tx_empty_if
Definition: mcp251863.h:1661
mcp251863_data_t::tec
uint8_t tec
Definition: mcp251863.h:1851
mcp251863_tef_t::tef_full_if
uint32_t tef_full_if
Definition: mcp251863.h:1610
mcp251863_gpio_standby_control_disable
err_t mcp251863_gpio_standby_control_disable(mcp251863_t *ctx)
Disable Transceiver Standby Control.
mcp251863_int_en_t::cerrie
uint32_t cerrie
Definition: mcp251863.h:1489
mcp251863_dbt_cfg_t::word
uint32_t word
Definition: mcp251863.h:1426
mcp251863_int_t::ie
mcp251863_int_en_t ie
Definition: mcp251863.h:1572
mcp251863_osc_ctl_t::unimplemented6
uint32_t unimplemented6
Definition: mcp251863.h:1232
mcp251863_tx_que_ctl_t::tx_enable
uint32_t tx_enable
Definition: mcp251863.h:1109
mcp251863_io_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1275
mcp251863_tef_event_get
err_t mcp251863_tef_event_get(mcp251863_t *ctx, uint8_t *flags)
Transmit Event FIFO Event Get.
mcp251863_tx_que_stat_t::tx_empty_if
uint32_t tx_empty_if
Definition: mcp251863.h:1628
mcp251863_int_flags_stat_t::TEFIF
uint32_t TEFIF
Definition: mcp251863.h:1538
mcp251863_bus_diag0_t::n_rx_error_count
uint32_t n_rx_error_count
Definition: mcp251863.h:1787
mcp251863_tef_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1136
mcp251863_time_stamp_prescaler_set
err_t mcp251863_time_stamp_prescaler_set(mcp251863_t *ctx, uint16_t time_stamp)
Time Stamp Prescaler Set.
mcp251863_tdc_cfg_t::word
uint32_t word
Definition: mcp251863.h:1448
mcp251863_module_event_get
err_t mcp251863_module_event_get(mcp251863_t *ctx, uint16_t *flags)
Module Event Get.
mcp251863_rx_fifo_cfg_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1361
mcp251863_cfg_t::mosi
pin_name_t mosi
Definition: mcp251863.h:1898
mcp251863_tef_event_enable
err_t mcp251863_tef_event_enable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Enable.
mcp251863_data_t::selected_bit_time
uint8_t selected_bit_time
Definition: mcp251863.h:1847
mcp251863_mask_obj_id_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1042
mcp251863_bus_diag_flags_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1742
mcp251863_tdc_cfg_t::tdc_mode
uint32_t tdc_mode
Definition: mcp251863.h:1442
mcp251863_tef_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1388
mcp251863_fifo_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1164
mcp251863_io_ctl_t::gpio1
uint32_t gpio1
Definition: mcp251863.h:1271
mcp251863_int_flags_stat_t::TXATIF
uint32_t TXATIF
Definition: mcp251863.h:1543
mcp251863_fifo_stat_t::fifo_index
uint32_t fifo_index
Definition: mcp251863.h:1654
mcp251863_int_flags_stat_t::TXIF
uint32_t TXIF
Definition: mcp251863.h:1534
mcp251863_fifo_ctl_t::word
uint32_t word
Definition: mcp251863.h:1193
mcp251863_generic_read
err_t mcp251863_generic_read(mcp251863_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
MCP251863 data reading function.
mcp251863_ctl_t
MCP251863 Click CAN Control Register.
Definition: mcp251863.h:1070
mcp251863_ts_cfg_t::time_stamp_eof
uint32_t time_stamp_eof
Definition: mcp251863.h:1463
mcp251863_fifo_ctl_t::tx_request
uint32_t tx_request
Definition: mcp251863.h:1184
mcp251863_msg_obj_id_t::sid
uint32_t sid
Definition: mcp251863.h:916
mcp251863_io_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1261
mcp251863_tx_que_stat_t::tx_lost_arbitration
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1632
mcp251863_ecc_event_get
err_t mcp251863_ecc_event_get(mcp251863_t *ctx, uint8_t *flags)
ECC Event Get.
mcp251863_io_ctl_t::tris0
uint32_t tris0
Definition: mcp251863.h:1259
mcp251863_fifo_stat_t::word
uint32_t word
Definition: mcp251863.h:1670
mcp251863_fifo_stat_t::tx_lost_arbitration
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1665
mcp251863_filt_ctl_t::byte
uint8_t byte
Definition: mcp251863.h:1209
mcp251863_filter_disable
err_t mcp251863_filter_disable(mcp251863_t *ctx, uint8_t filter)
Filter Disable.
mcp251863_bus_error_count_t::d_tec
uint8_t d_tec
Definition: mcp251863.h:1760
mcp251863_tx_que_stat_t::tx_not_full_if
uint32_t tx_not_full_if
Definition: mcp251863.h:1626
mcp251863_int_en_t::modie
uint32_t modie
Definition: mcp251863.h:1480
mcp251863_bus_error_count_t::d_rec
uint8_t d_rec
Definition: mcp251863.h:1759
mcp251863_can_cfg_t::d_net_filter_count
uint32_t d_net_filter_count
Definition: mcp251863.h:860
mcp251863_tx_msg_obj_ctl_t::rtr
uint32_t rtr
Definition: mcp251863.h:931
mcp251863_receive_channel_event_disable
err_t mcp251863_receive_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Disable.
mcp251863_bus_diag_flags_t::n_crc_err
uint32_t n_crc_err
Definition: mcp251863.h:1737
mcp251863_int_flags_stat_t::MODIF
uint32_t MODIF
Definition: mcp251863.h:1537
T_MCP251863_cfg_t::d_net_filter_count
uint32_t d_net_filter_count
Definition: mcp251863.h:1311
mcp251863_rx_msg_obj_ctl_t
MCP251863 Click CAN RX Message Object Control.
Definition: mcp251863.h:961
mcp251863_int_cfg_t::word
uint16_t word
Definition: mcp251863.h:1502
mcp251863_io_ctl_t::xcr_stby_enable
uint32_t xcr_stby_enable
Definition: mcp251863.h:1264
mcp251863_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1080
mcp251863_module_event_disable
err_t mcp251863_module_event_disable(mcp251863_t *ctx, uint16_t flags)
Module Event Disable.
mcp251863_tx_que_stat_t::tx_aborted
uint32_t tx_aborted
Definition: mcp251863.h:1633
mcp251863_receive_event_get
err_t mcp251863_receive_event_get(mcp251863_t *ctx, uint32_t *rxif)
Get pending interrupts of all receive FIFOs.
T_MCP251863_cfg_t::wake_up_filter_time
uint32_t wake_up_filter_time
Definition: mcp251863.h:1315
mcp251863_rx_msg_obj_t::id
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:981
mcp251863_fifo_user_cfg_t::user_address
uint32_t user_address
Definition: mcp251863.h:1373
mcp251863_module_event_rx_code_get
err_t mcp251863_module_event_rx_code_get(mcp251863_t *ctx, uint8_t *rx_code)
Get RX Code.
mcp251863_tx_msg_obj_ctl_t::dlc
uint32_t dlc
Definition: mcp251863.h:929
mcp251863_ecc_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1296
mcp251863_filt_obj_t::bf
mcp251863_filt_obj_id_t bf
Definition: mcp251863.h:1026
mcp251863_bus_diag1_t::n_bit1_error
uint32_t n_bit1_error
Definition: mcp251863.h:1806
mcp251863_can_cfg_t::protocol_expection_event_disable
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:862
mcp251863_crc_t::crc
uint32_t crc
Definition: mcp251863.h:1682
mcp251863_fifo_ctl_t::rx_over_flow_ie
uint32_t rx_over_flow_ie
Definition: mcp251863.h:1161
mcp251863_ctl_t::protocol_exception_event_disable
uint32_t protocol_exception_event_disable
Definition: mcp251863.h:1074
mcp251863_fifo_stat_t::rx_full_if
uint32_t rx_full_if
Definition: mcp251863.h:1651
mcp251863_rx_msg_obj_ctl_t::ide
uint32_t ide
Definition: mcp251863.h:963
mcp251863_crc_value_get
err_t mcp251863_crc_value_get(mcp251863_t *ctx, uint16_t *crc)
Get CRC Value from device.
mcp251863_cfg_t::clk
pin_name_t clk
Definition: mcp251863.h:1904
mcp251863_crc_t::ferrie
uint32_t ferrie
Definition: mcp251863.h:1687
mcp251863_tx_fifo_cfg_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1336
mcp251863_int_cfg_t::ie
mcp251863_int_en_t ie
Definition: mcp251863.h:1501
mcp251863_ts_cfg_t::tbc_enable
uint32_t tbc_enable
Definition: mcp251863.h:1462
mcp251863_data_t::tx_config
mcp251863_tx_fifo_cfg_t tx_config
Definition: mcp251863.h:1857
mcp251863_can_cfg_t::restrict_re_tx_attempts
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:866
mcp251863_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: mcp251863.h:1909
mcp251863_io_ctl_t::word
uint32_t word
Definition: mcp251863.h:1281
mcp251863_t
MCP251863 Click context object.
Definition: mcp251863.h:1872
mcp251863_gpio_pin_set
err_t mcp251863_gpio_pin_set(mcp251863_t *ctx, uint8_t pos, uint8_t latch)
GPIO Output Pin Set.
mcp251863_receive_channel_event_overflow_clear
err_t mcp251863_receive_channel_event_overflow_clear(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Event Clear.
mcp251863_ecc_ctl_t
MCP251863 Click ECC Control Register.
Definition: mcp251863.h:1291
mcp251863_bus_diag_flags_t
MCP251863 Click CAN Bus Diagnostic flags.
Definition: mcp251863.h:1731
mcp251863_tef_event_disable
err_t mcp251863_tef_event_disable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Disable.
mcp251863_tef_ctl_t::teffulie
uint32_t teffulie
Definition: mcp251863.h:1134
mcp251863_config_t::tx_fifo_size
uint8_t tx_fifo_size
Definition: mcp251863.h:883
mcp251863_bus_diag1_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1811
mcp251863_module_event_enable
err_t mcp251863_module_event_enable(mcp251863_t *ctx, uint16_t flags)
Module Event Enable.
mcp251863_tx_que_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1116
mcp251863_receive_channel_configure
err_t mcp251863_receive_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_fifo_cfg_t *config)
Configure Receive FIFO.
mcp251863_fifo_stat_t::rx_half_full_if
uint32_t rx_half_full_if
Definition: mcp251863.h:1650
mcp251863_int_en_t::txatie
uint32_t txatie
Definition: mcp251863.h:1486
mcp251863_write_word_safe
err_t mcp251863_write_word_safe(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI RAM Write Word Safe.
mcp251863_osc_sta_t::pll_ready
uint32_t pll_ready
Definition: mcp251863.h:1720
mcp251863_fifo_ctl_t::tx_half_full_ie
uint32_t tx_half_full_ie
Definition: mcp251863.h:1176
mcp251863_init
err_t mcp251863_init(mcp251863_t *ctx, mcp251863_cfg_t *cfg)
MCP251863 initialization function.
mcp251863_tx_fifo_cfg_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1334
mcp251863_error_count_state_get
err_t mcp251863_error_count_state_get(mcp251863_t *ctx, uint8_t *tec, uint8_t *rec, uint8_t *flags)
Error Counts and Error State Get.
mcp251863_tef_message_get
err_t mcp251863_tef_message_get(mcp251863_t *ctx, mcp251863_tef_msg_obj_t *tef_obj)
Get Transmit Event FIFO Message.
mcp251863_data_t::op_mode
uint8_t op_mode
Definition: mcp251863.h:1853
mcp251863_write_byte_array_with_crc
err_t mcp251863_write_byte_array_with_crc(mcp251863_t *ctx, bool from_ram)
SPI Write Byte Array with CRC.
mcp251863_ecc_event_clear
err_t mcp251863_ecc_event_clear(mcp251863_t *ctx, uint8_t flags)
ECC Event Clear.
mcp251863_bus_diag_t
MCP251863 Click CAN BUS DIAGNOSTICS.
Definition: mcp251863.h:1769
mcp251863_tx_que_ctl_t::tx_attempt_ie
uint32_t tx_attempt_ie
Definition: mcp251863.h:1107
mcp251863_config_t::fd_frame
uint8_t fd_frame
Definition: mcp251863.h:890
T_MCP251863_cfg_t::bit_rate_switch_disable
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1316
mcp251863_tx_msg_obj_t
MCP251863 Click CAN TX Message Object.
Definition: mcp251863.h:945
mcp251863_tx_que_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1104
mcp251863_nbt_cfg_t::word
uint32_t word
Definition: mcp251863.h:1406
mcp251863_rx_msg_obj_t
MCP251863 Click CAN RX Message Object.
Definition: mcp251863.h:979
mcp251863_trec_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1594
mcp251863_nbt_cfg_t::brp
uint32_t brp
Definition: mcp251863.h:1404
mcp251863_int_flags_stat_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1539
mcp251863_filt_obj_t
MCP251863 Click Filter Object Register.
Definition: mcp251863.h:1025
mcp251863_read_byte
err_t mcp251863_read_byte(mcp251863_t *ctx, uint16_t address, uint8_t *data_out)
SPI Read Byte function.
mcp251863_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1075
mcp251863_tef_update
err_t mcp251863_tef_update(mcp251863_t *ctx)
Transmit Event FIFO Update.
mcp251863_fifo_ctl_t::freset
uint32_t freset
Definition: mcp251863.h:1168
mcp251863_mask_obj_t::word
uint32_t word
Definition: mcp251863.h:1053
mcp251863_receive_event_overflow_get
err_t mcp251863_receive_event_overflow_get(mcp251863_t *ctx, uint32_t *rxovif)
Get pending RXOVIF of all receive FIFOs.
mcp251863_crc_event_enable
err_t mcp251863_crc_event_enable(mcp251863_t *ctx, uint8_t flags)
CRC Event Enable.
mcp251863_tx_msg_obj_t::ctrl
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:948
mcp251863_bus_diag_flags_t::d_stuff_err
uint32_t d_stuff_err
Definition: mcp251863.h:1744
mcp251863_trec_t::rx_error_state_passive
uint32_t rx_error_state_passive
Definition: mcp251863.h:1591
mcp251863_int_en_t::serrie
uint32_t serrie
Definition: mcp251863.h:1488
mcp251863_receive_channel_status_get
err_t mcp251863_receive_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint8_t *status)
Receive Channel Status Get.
mcp251863_crc_t
MCP251863 Click CRC Regsiter.
Definition: mcp251863.h:1680
mcp251863_io_ctl_t::tx_can_open_drain
uint32_t tx_can_open_drain
Definition: mcp251863.h:1276
mcp251863_can_cfg_t::store_in_tef
uint32_t store_in_tef
Definition: mcp251863.h:869
mcp251863_ecc_disable
err_t mcp251863_ecc_disable(mcp251863_t *ctx)
Disable ECC.
mcp251863_bus_error_count_t
MCP251863 Click CAN Bus Diagnostic Error Counts.
Definition: mcp251863.h:1756
mcp251863_config_t::tx_pay_load_size
uint8_t tx_pay_load_size
Definition: mcp251863.h:884
mcp251863_module_event_filter_hit_get
err_t mcp251863_module_event_filter_hit_get(mcp251863_t *ctx, uint8_t *filter_hit)
Get Filter Hit.
mcp251863_ecc_sta_t::dedif
uint32_t dedif
Definition: mcp251863.h:1704
mcp251863_bus_diag_t::flag
mcp251863_bus_diag_flags_t flag
Definition: mcp251863.h:1773
mcp251863_tx_fifo_cfg_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1333
mcp251863_error_state_get
err_t mcp251863_error_state_get(mcp251863_t *ctx, uint8_t *flags)
Error State Get.
mcp251863_t::glb_data
mcp251863_data_t glb_data
Definition: mcp251863.h:1885
mcp251863_bus_diag1_t::n_bit0_error
uint32_t n_bit0_error
Definition: mcp251863.h:1805
mcp251863_bus_diag0_t::d_rx_error_count
uint32_t d_rx_error_count
Definition: mcp251863.h:1789
mcp251863_func_data_t::n_bytes
uint16_t n_bytes
Definition: mcp251863.h:1835
mcp251863_data_t::error_flags
uint8_t error_flags
Definition: mcp251863.h:1850
mcp251863_ecc_parity_get
err_t mcp251863_ecc_parity_get(mcp251863_t *ctx, uint8_t *parity)
Get ECC Parity.
mcp251863_io_ctl_t::pin_mode0
uint32_t pin_mode0
Definition: mcp251863.h:1273
T_MCP251863_cfg_t::tx_band_width_sharing
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1322
mcp251863_int_flag_t::if_stat
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1558
mcp251863_bus_diag1_t::d_ack_error
uint32_t d_ack_error
Definition: mcp251863.h:1815
mcp251863_transmit_queue_configure
err_t mcp251863_transmit_queue_configure(mcp251863_t *ctx, mcp251863_tx_que_cfg_t *config)
Configure Transmit Queue.
mcp251863_io_ctl_t::unimplemented6
uint32_t unimplemented6
Definition: mcp251863.h:1279
mcp251863_fifo_ctl_t::rtr_enable
uint32_t rtr_enable
Definition: mcp251863.h:1181
mcp251863_config_t::standard_id
uint16_t standard_id
Definition: mcp251863.h:888
mcp251863_bus_diag0_t
MCP251863 Click Diagnostic register 0.
Definition: mcp251863.h:1785
T_MCP251863_cfg_t::iso_crc_enable
uint32_t iso_crc_enable
Definition: mcp251863.h:1312
mcp251863_osc_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1230
mcp251863_filter_to_fifo_link
err_t mcp251863_filter_to_fifo_link(mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable)
Link Filter to FIFO.
mcp251863_t::clk
digital_in_t clk
Definition: mcp251863.h:1877
mcp251863_trec_t::error_state_warning
uint32_t error_state_warning
Definition: mcp251863.h:1588
mcp251863_tef_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1144
mcp251863_oscillator_control_set
err_t mcp251863_oscillator_control_set(mcp251863_t *ctx, mcp251863_div_ctl_t ctrl)
Set Oscillator Control.
mcp251863_tef_t::word
uint32_t word
Definition: mcp251863.h:1614
mcp251863_bus_diag_t::error_free_msg_count
uint16_t error_free_msg_count
Definition: mcp251863.h:1772
mcp251863_tdc_cfg_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1446
mcp251863_bus_diag1_t::d_bit0_error
uint32_t d_bit0_error
Definition: mcp251863.h:1813
T_MCP251863_cfg_t::protocol_expection_event_disable
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:1313
mcp251863_can_cfg_t::tx_band_width_sharing
uint32_t tx_band_width_sharing
Definition: mcp251863.h:871
mcp251863_cfg_t::miso
pin_name_t miso
Definition: mcp251863.h:1897
mcp251863_tx_que_ctl_t::tx_request
uint32_t tx_request
Definition: mcp251863.h:1111
mcp251863_bus_diag1_t
MCP251863 Click Diagnostic register 1.
Definition: mcp251863.h:1802
mcp251863_gpio_standby_control_enable
err_t mcp251863_gpio_standby_control_enable(mcp251863_t *ctx)
Enable Transceiver Standby Control.
mcp251863_rx_msg_obj_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:968
mcp251863_read_byte_array
err_t mcp251863_read_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_out, uint16_t n_bytes)
SPI Read Byte Array.
mcp251863_bit_time_configure
err_t mcp251863_bit_time_configure(mcp251863_t *ctx, uint8_t bit_time, uint8_t clk)
Configure Bit Time registers (based on CAN clock speed).
mcp251863_tef_ctl_t::tefovie
uint32_t tefovie
Definition: mcp251863.h:1135
mcp251863_can_cfg_t::bit_rate_switch_disable
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:865
mcp251863_tx_que_stat_t::tx_error
uint32_t tx_error
Definition: mcp251863.h:1631
mcp251863_bus_diag1_t::n_stuff_error
uint32_t n_stuff_error
Definition: mcp251863.h:1809
mcp251863_bus_diag0_t::d_tx_error_count
uint32_t d_tx_error_count
Definition: mcp251863.h:1790
mcp251863_module_event_clear
err_t mcp251863_module_event_clear(mcp251863_t *ctx, uint16_t flags)
Module Event Clear.
mcp251863_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: mcp251863.h:1910
mcp251863_ecc_ctl_t::secie
uint32_t secie
Definition: mcp251863.h:1294
mcp251863_rx_fifo_cfg_t::rx_time_stamp_enable
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1359
mcp251863_data_t::tx_id
uint32_t tx_id
Definition: mcp251863.h:1854
mcp251863_error_count_receive_get
err_t mcp251863_error_count_receive_get(mcp251863_t *ctx, uint8_t *rec)
Receive Error Count Get.
mcp251863_write_byte
err_t mcp251863_write_byte(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI Write Byte.
mcp251863_io_ctl_t::auto_sleep_enable
uint32_t auto_sleep_enable
Definition: mcp251863.h:1263
mcp251863_gpio_interrupt_pins_open_drain_configure
err_t mcp251863_gpio_interrupt_pins_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain Interrupts.
mcp251863_crc_t::crcerrie
uint32_t crcerrie
Definition: mcp251863.h:1686
mcp251863_tx_que_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1348
mcp251863_config_t::tx_priority
uint8_t tx_priority
Definition: mcp251863.h:885
mcp251863_tef_ctl_t::uinc
uint32_t uinc
Definition: mcp251863.h:1139
mcp251863_transmit_channel_load
err_t mcp251863_transmit_channel_load(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_msg_obj_t *tx_obj, bool flush)
TX Channel Load.
mcp251863_crc_t::ferrif
uint32_t ferrif
Definition: mcp251863.h:1684
mcp251863_bit_time_configure_nominal_20_mhz
err_t mcp251863_bit_time_configure_nominal_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.