mcp251863  2.0.0.0
mcp251863.h
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22 
28 #ifndef MCP251863_H
29 #define MCP251863_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
39 #ifdef PREINIT_SUPPORTED
40 #include "preinit.h"
41 #endif
42 
43 #ifdef MikroCCoreVersion
44  #if MikroCCoreVersion >= 1
45  #include "delays.h"
46  #endif
47 #endif
48 
49 #include "drv_digital_out.h"
50 #include "drv_digital_in.h"
51 #include "drv_spi_master.h"
52 #include "spi_specifics.h"
53 
64 #define MCP251863
65 
70 //#define REV_A
71 #define REV_B
72 
73 #ifdef REV_A
74  #define FIXED_FILTER_ADDRESS
75 #endif
76 
81 #ifndef FPGA
82  #define MCP251863_FIFO_08TO15_IMPLEMENTED
83  #define MCP251863_FIFO_16TO31_IMPLEMENTED
84 #endif
85 
90 #ifndef FPGA
91  #define MCP251863_FILT_08TO15_IMPLEMENTED
92  #define MCP251863_FILT_16TO31_IMPLEMENTED
93 #endif
94 
99 #ifdef MCP2520FD
100  #define CAN_INTERNAL_OSC_PRESENT
101 #endif
102 
107 #ifdef REV_B
108  #define CAN_RESTRICTED_MODE_PRESENT
109 #endif
110 
115 #ifdef REV_B
116  #define CAN_TXQUEUE_IMPLEMENTED
117 #endif
118 
124 #ifdef REV_A
125  #define USERADDRESS_TIMES_FOUR
126 #endif
127 
128 #ifdef MCP251863
129  #define N_MCP2518_CTRL_REGS 5
130 #endif
131 
132 #define MCP251863_MAX_TXQUEUE_ATTEMPTS 50
133 #define MCP251863_TX_REQUEST_ID 0x300
134 #define MCP251863_TX_RESPONSE_ID 0x301
135 
136 #define MCP251863_CRCBASE 0xFFFF
137 #define MCP251863_CRCUPPER 1
138 #define MCP251863_DRV_CANFDSPI_INDEX_0 0
139 #define MCP251863_SPI_DEFAULT_BUFFER_LENGTH 96
140 
141 #define MCP251863_ISO_CRC 1
142 
143 #define MCP251863_MAX_MSG_SIZE 76
144 
145 #define MCP251863_MAX_DATA_BYTES 64
146 
147 #define MCP251863_INS_RESET 0x00
148 #define MCP251863_INS_READ 0x03
149 #define MCP251863_INS_READ_CRC 0x0B
150 #define MCP251863_INS_WRITE 0x02
151 #define MCP251863_INS_WRITE_CRC 0x0A
152 #define MCP251863_INS_WRITE_SAFE 0x0C
153 
154 
155 #define MCP251863_FIFO_OFFSET ( 3 * 4 )
156 #define MCP251863_FILTER_OFFSET ( 2 * 4 )
157 
158 #ifdef CAN_TXQUEUE_IMPLEMENTED
159  #define MCP251863_REG_CITXQCON 0x050
160  #define MCP251863_REG_CITXQSTA 0x054
161  #define MCP251863_REG_CITXQUA 0x058
162 #endif
163 
164 #ifdef FIXED_FILTER_ADDRESS
165  #define MCP251863_REG_CIFLTCON 0x1D0
166  #define MCP251863_REG_CIFLTOBJ 0x1F0
167  #define MCP251863_REG_CIMASK 0x1F4
168 #else
169  #define MCP251863_REG_CIFLTCON ( MCP251863_REG_CIFIFOCON + ( MCP251863_FIFO_OFFSET * MCP251863_FIFO_TOTAL_CHANNELS ) )
170  #define MCP251863_REG_CIFLTOBJ ( MCP251863_REG_CIFLTCON + MCP251863_FIFO_TOTAL_CHANNELS )
171  #define MCP251863_REG_CIMASK ( MCP251863_REG_CIFLTOBJ + 4 )
172 #endif
173 
174 #define MCP251863_REG_OSC 0xE00
175 #define MCP251863_REG_IOCON 0xE04
176 #define MCP251863_REG_CRC 0xE08
177 #define MCP251863_REG_ECCCON 0xE0C
178 #define MCP251863_REG_ECCSTA 0xE10
179 
180 #define MCP251863_RAM_SIZE 2048
181 #define MCP251863_RAMADDR_START 0x400
182 #define MCP251863_RAMADDR_END ( MCP251863_RAMADDR_START + MCP251863_RAM_SIZE )
183 
184 #define MCP251863_LOW_POWER_MODE_EN 0x08
185 #define MCP251863_LOW_POWER_MODE_DIS 0x00
186 #define MCP251863_WAKEUP_INTERR_EN 0x40
187 
188 #define MCP251863_REG_CICON 0x000
189 #define MCP251863_REG_CINBTCFG 0x004
190 #define MCP251863_REG_CIDBTCFG 0x008
191 #define MCP251863_REG_CITDC 0x00C
192 
193 #define MCP251863_REG_CITBC 0x010
194 #define MCP251863_REG_CITSCON 0x014
195 #define MCP251863_REG_CIVEC 0x018
196 #define MCP251863_REG_CIINT 0x01C
197 #define MCP251863_REG_CIINTFLAG MCP251863_REG_CIINT
198 #define MCP251863_REG_CIINTENABLE ( MCP251863_REG_CIINT + 2 )
199 
200 #define MCP251863_REG_CIRXIF 0x020
201 #define MCP251863_REG_CITXIF 0x024
202 #define MCP251863_REG_CIRXOVIF 0x028
203 #define MCP251863_REG_CITXATIF 0x02C
204 
205 #define MCP251863_REG_CITXREQ 0x030
206 #define MCP251863_REG_CITREC 0x034
207 #define MCP251863_REG_CIBDIAG0 0x038
208 #define MCP251863_REG_CIBDIAG1 0x03C
209 
210 #define MCP251863_REG_CITEFCON 0x040
211 #define MCP251863_REG_CITEFSTA 0x044
212 #define MCP251863_REG_CITEFUA 0x048
213 #define MCP251863_REG_CIFIFOBA 0x04C
214 
215 #define MCP251863_REG_CIFIFOCON 0x050
216 #define MCP251863_REG_CIFIFOSTA 0x054
217 #define MCP251863_REG_CIFIFOUA 0x058
218  // mcp251863_reg
230 
250 #define MCP251863_FIFO_CH0 0
251 #define MCP251863_FIFO_CH1 1
252 #define MCP251863_FIFO_CH2 2
253 #define MCP251863_FIFO_CH3 3
254 #define MCP251863_FIFO_CH4 4
255 #define MCP251863_FIFO_CH5 5
256 #define MCP251863_FIFO_CH6 6
257 #define MCP251863_FIFO_CH7 7
258 
259 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
260  #define MCP251863_FIFO_CH8 8
261  #define MCP251863_FIFO_CH9 9
262  #define MCP251863_FIFO_CH10 10
263  #define MCP251863_FIFO_CH11 11
264  #define MCP251863_FIFO_CH12 12
265  #define MCP251863_FIFO_CH13 13
266  #define MCP251863_FIFO_CH14 14
267  #define MCP251863_FIFO_CH15 15
268 #endif
269 
270 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
271  #define MCP251863_FIFO_CH16 16
272  #define MCP251863_FIFO_CH17 17
273  #define MCP251863_FIFO_CH18 18
274  #define MCP251863_FIFO_CH19 19
275  #define MCP251863_FIFO_CH20 20
276  #define MCP251863_FIFO_CH21 21
277  #define MCP251863_FIFO_CH22 22
278  #define MCP251863_FIFO_CH23 23
279  #define MCP251863_FIFO_CH24 24
280  #define MCP251863_FIFO_CH25 25
281  #define MCP251863_FIFO_CH26 26
282  #define MCP251863_FIFO_CH27 27
283  #define MCP251863_FIFO_CH28 28
284  #define MCP251863_FIFO_CH29 29
285  #define MCP251863_FIFO_CH30 30
286  #define MCP251863_FIFO_CH31 31
287 #endif
288 
289 
290 #define MCP251863_FIFO_TOTAL_CHANNELS 32
291 
292 #ifdef CAN_TXQUEUE_IMPLEMENTED
293  #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1
294  #define CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0
295 #else
296  #define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH0
297 #endif
298 
303 #define MCP251863_FILT0 0
304 #define MCP251863_FILT1 1
305 #define MCP251863_FILT2 2
306 #define MCP251863_FILT3 3
307 #define MCP251863_FILT4 4
308 #define MCP251863_FILT5 5
309 #define MCP251863_FILT6 6
310 #define MCP251863_FILT7 7
311 
312 #ifdef MCP251863_FILT_08TO15_IMPLEMENTED
313  #define MCP251863_FILT8 8
314  #define MCP251863_FILT9 9
315  #define MCP251863_FILT10 10
316  #define MCP251863_FILT11 11
317  #define MCP251863_FILT12 12
318  #define MCP251863_FILT13 13
319  #define MCP251863_FILT14 14
320  #define MCP251863_FILT15 15
321 #endif
322 
323 #ifdef MCP251863_FILT_16TO31_IMPLEMENTED
324  #define MCP251863_FILT16 16
325  #define MCP251863_FILT17 17
326  #define MCP251863_FILT18 18
327  #define MCP251863_FILT19 19
328  #define MCP251863_FILT20 20
329  #define MCP251863_FILT21 21
330  #define MCP251863_FILT22 22
331  #define MCP251863_FILT23 23
332  #define MCP251863_FILT24 24
333  #define MCP251863_FILT25 25
334  #define MCP251863_FILT26 26
335  #define MCP251863_FILT27 27
336  #define MCP251863_FILT28 28
337  #define MCP251863_FILT29 29
338  #define MCP251863_FILT30 30
339  #define MCP251863_FILT31 31
340 #endif
341 
342 #define MCP251863_FILT_TOTAL 32
343 
348 #define MCP251863_NORMAL_MODE 0x00
349 #define MCP251863_SLEEP_MODE 0x01
350 #define MCP251863_INT_LOOP_MODE 0x02
351 #define MCP251863_LISTEN_ONLY_MODE 0x03
352 #define MCP251863_CONFIG_MODE 0x04
353 #define MCP251863_EXT_LOOP_MODE 0x05
354 #define MCP251863_CLASSIC_MODE 0x06
355 #define MCP251863_RESTRICT_MODE 0x07
356 #define MCP251863_INVALID_MODE 0xFF
357 
362 #define MCP251863_TXBWS_NO_DELAY 0
363 #define MCP251863_TXBWS_2 1
364 #define MCP251863_TXBWS_4 2
365 #define MCP251863_TXBWS_8 3
366 #define MCP251863_TXBWS_16 4
367 #define MCP251863_TXBWS_32 5
368 #define MCP251863_TXBWS_64 6
369 #define MCP251863_TXBWS_128 7
370 #define MCP251863_TXBWS_256 8
371 #define MCP251863_TXBWS_512 9
372 #define MCP251863_TXBWS_1024 10
373 #define MCP251863_TXBWS_2048 11
374 #define MCP251863_TXBWS_4096 12
375 
380 #define MCP251863_WFT00 0
381 #define MCP251863_WFT01 1
382 #define MCP251863_WFT10 2
383 #define MCP251863_WFT11 3
384 
389 #define MCP251863_DNET_FILT_DISABLE 0
390 #define MCP251863_DNET_FILT_SIZE_1_BIT 1
391 #define MCP251863_DNET_FILT_SIZE_2_BIT 2
392 #define MCP251863_DNET_FILT_SIZE_3_BIT 3
393 #define MCP251863_DNET_FILT_SIZE_4_BIT 4
394 #define MCP251863_DNET_FILT_SIZE_5_BIT 5
395 #define MCP251863_DNET_FILT_SIZE_6_BIT 6
396 #define MCP251863_DNET_FILT_SIZE_7_BIT 7
397 #define MCP251863_DNET_FILT_SIZE_8_BIT 8
398 #define MCP251863_DNET_FILT_SIZE_9_BIT 9
399 #define MCP251863_DNET_FILT_SIZE_10_BIT 10
400 #define MCP251863_DNET_FILT_SIZE_11_BIT 11
401 #define MCP251863_DNET_FILT_SIZE_12_BIT 12
402 #define MCP251863_DNET_FILT_SIZE_13_BIT 13
403 #define MCP251863_DNET_FILT_SIZE_14_BIT 14
404 #define MCP251863_DNET_FILT_SIZE_15_BIT 15
405 #define MCP251863_DNET_FILT_SIZE_16_BIT 16
406 #define MCP251863_DNET_FILT_SIZE_17_BIT 17
407 #define MCP251863_DNET_FILT_SIZE_18_BIT 18
408 
413 #define MCP251863_PLSIZE_8 0
414 #define MCP251863_PLSIZE_12 1
415 #define MCP251863_PLSIZE_16 2
416 #define MCP251863_PLSIZE_20 3
417 #define MCP251863_PLSIZE_24 4
418 #define MCP251863_PLSIZE_32 5
419 #define MCP251863_PLSIZE_48 6
420 #define MCP251863_PLSIZE_64 7
421 
426 #define MCP251863_DLC_0 0
427 #define MCP251863_DLC_1 1
428 #define MCP251863_DLC_2 2
429 #define MCP251863_DLC_3 3
430 #define MCP251863_DLC_4 4
431 #define MCP251863_DLC_5 5
432 #define MCP251863_DLC_6 6
433 #define MCP251863_DLC_7 7
434 #define MCP251863_DLC_8 8
435 #define MCP251863_DLC_12 9
436 #define MCP251863_DLC_16 10
437 #define MCP251863_DLC_20 11
438 #define MCP251863_DLC_24 12
439 #define MCP251863_DLC_32 13
440 #define MCP251863_DLC_48 14
441 #define MCP251863_DLC_64 15
442 
447 #define MCP251863_RX_FIFO_EMPTY 0
448 #define MCP251863_RX_FIFO_STATUS_MASK 0x0F
449 #define MCP251863_RX_FIFO_NOT_EMPTY 0x01
450 #define MCP251863_RX_FIFO_HALF_FULL 0x02
451 #define MCP251863_RX_FIFO_FULL 0x04
452 #define MCP251863_RX_FIFO_OVERFLOW 0x08
453 
458 #define MCP251863_TX_FIFO_FULL 0
459 #define MCP251863_TX_FIFO_STATUS_MASK 0x1F7
460 #define MCP251863_TX_FIFO_NOT_FULL 0x01
461 #define MCP251863_TX_FIFO_HALF_FULL 0x02
462 #define MCP251863_TX_FIFO_EMPTY 0x04
463 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10
464 #define MCP251863_TX_FIFO_ERROR 0x20
465 #define MCP251863_TX_FIFO_ARBITRATION_LOST 0x40
466 #define MCP251863_TX_FIFO_ABORTED 0x80
467 #define MCP251863_TX_FIFO_TRANSMITTING 0x100
468 
473 #define MCP251863_TEF_FIFO_EMPTY 0
474 #define MCP251863_TEF_FIFO_STATUS_MASK 0x0F
475 #define MCP251863_TEF_FIFO_NOT_EMPTY 0x01
476 #define MCP251863_TEF_FIFO_HALF_FULL 0x02
477 #define MCP251863_TEF_FIFO_FULL 0x04
478 #define MCP251863_TEF_FIFO_OVERFLOW 0x08
479 
484 #define MCP251863_TX_FIFO_NO_EVENT 0
485 #define MCP251863_TX_FIFO_ALL_EVENTS 0x17
486 #define MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01
487 #define MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02
488 #define MCP251863_TX_FIFO_EMPTY_EVENT 0x04
489 #define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10
490 
491 #define MCP251863_RX_FIFO_NO_EVENT 0
492 #define MCP251863_RX_FIFO_ALL_EVENTS 0x0F
493 #define MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01
494 #define MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02
495 #define MCP251863_RX_FIFO_FULL_EVENT 0x04
496 #define MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08
497 
498 #define MCP251863_TEF_FIFO_NO_EVENT 0
499 #define MCP251863_TEF_FIFO_ALL_EVENTS 0x0F
500 #define MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01
501 #define MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02
502 #define MCP251863_TEF_FIFO_FULL_EVENT 0x04
503 #define MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08
504 
505 #define MCP251863_NO_EVENT 0
506 #define MCP251863_ALL_EVENTS 0xFF1F
507 #define MCP251863_TX_EVENT 0x0001
508 #define MCP251863_RX_EVENT 0x0002
509 #define MCP251863_TIME_BASE_COUNTER_EVENT 0x0004
510 #define MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008
511 #define MCP251863_TEF_EVENT 0x0010
512 
513 #define MCP251863_RAM_ECC_EVENT 0x0100
514 #define MCP251863_SPI_CRC_EVENT 0x0200
515 #define MCP251863_TX_ATTEMPTS_EVENT 0x0400
516 #define MCP251863_RX_OVERFLOW_EVENT 0x0800
517 #define MCP251863_SYSTEM_ERROR_EVENT 0x1000
518 #define MCP251863_BUS_ERROR_EVENT 0x2000
519 #define MCP251863_BUS_WAKEUP_EVENT 0x4000
520 #define MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000
521 
522 #define MCP251863_500K_1M 0
523 #define MCP251863_500K_2M 1
524 #define MCP251863_500K_3M 2
525 #define MCP251863_500K_4M 3
526 #define MCP251863_500K_5M 4
527 #define MCP251863_500K_6M7 5
528 #define MCP251863_500K_8M 6
529 #define MCP251863_500K_10M 7
530 #define MCP251863_250K_500K 8
531 #define MCP251863_250K_833K 9
532 #define MCP251863_250K_1M 10
533 #define MCP251863_250K_1M5 11
534 #define MCP251863_250K_2M 12
535 #define MCP251863_250K_3M 13
536 #define MCP251863_250K_4M 14
537 #define MCP251863_1000K_4M 15
538 #define MCP251863_1000K_8M 16
539 #define MCP251863_125K_500K 17
540 
541 #define MCP251863_NBT_125K 0
542 #define MCP251863_NBT_250K 1
543 #define MCP251863_NBT_500K 2
544 #define MCP251863_NBT_1M 3
545 
546 #define MCP251863_DBT_500K 0
547 #define MCP251863_DBT_833K 1
548 #define MCP251863_DBT_1M 2
549 #define MCP251863_DBT_1M5 3
550 #define MCP251863_DBT_2M 4
551 #define MCP251863_DBT_3M 5
552 #define MCP251863_DBT_4M 6
553 #define MCP251863_DBT_5M 7
554 #define MCP251863_DBT_6M7 8
555 #define MCP251863_DBT_8M 9
556 #define MCP251863_DBT_10M 10
557 
558 #define MCP251863_SSP_MODE_OFF 0
559 #define MCP251863_SSP_MODE_MANUAL 1
560 #define MCP251863_SSP_MODE_AUTO 2
561 
562 #define MCP251863_ERROR_FREE_STATE 0
563 #define MCP251863_ERROR_ALL 0x3F
564 #define MCP251863_TX_RX_WARNING_STATE 0x01
565 #define MCP251863_RX_WARNING_STATE 0x02
566 #define MCP251863_TX_WARNING_STATE 0x04
567 #define MCP251863_RX_BUS_PASSIVE_STATE 0x08
568 #define MCP251863_TX_BUS_PASSIVE_STATE 0x10
569 #define MCP251863_TX_BUS_OFF_STATE 0x20
570 
571 #define MCP251863_TS_SOF 0x00
572 #define MCP251863_TS_EOF 0x01
573 #define MCP251863_TS_RES 0x02
574 
575 #define MCP2518_ECC_NO_EVENT 0x00
576 #define MCP2518_ECC_ALL_EVENTS 0x06
577 #define MCP2518_ECC_SEC_EVENT 0x02
578 #define MCP2518_ECC_DED_EVENT 0x04
579 
580 #define MCP251863_CRC_NO_EVENT 0x00
581 #define MCP251863_CRC_ALL_EVENTS 0x03
582 #define MCP251863_CRC_CRCERR_EVENT 0x01
583 #define MCP251863_CRC_FORMERR_EVENT 0x02
584 
589 #define MCP251863_PIN_0 0
590 #define MCP251863_PIN_1 1
591 
592 #define MCP251863_PINMODE_INT 0
593 #define MCP251863_PINMODE_GPIO 1
594 
595 #define MCP251863_PINOUT 0
596 #define MCP251863_PININ 1
597 
598 #define MCP251863_PINLOW 0
599 #define MCP251863_PINHIGH 1
600 
601 #define MCP251863_PUSHPULL 0
602 #define MCP251863_OPENDRAIN 1
603 
604 #define MCP251863_CLKO_CLOCK 0
605 #define MCP251863_CLKO_SOF 1
606 
611 #define MCP251863_TXREQ_CH0 0x00000001
612 #define MCP251863_TXREQ_CH1 0x00000002
613 #define MCP251863_TXREQ_CH2 0x00000004
614 #define MCP251863_TXREQ_CH3 0x00000008
615 #define MCP251863_TXREQ_CH4 0x00000010
616 #define MCP251863_TXREQ_CH5 0x00000020
617 #define MCP251863_TXREQ_CH6 0x00000040
618 #define MCP251863_TXREQ_CH7 0x00000080
619 
620 #define MCP251863_TXREQ_CH8 0x00000100
621 #define MCP251863_TXREQ_CH9 0x00000200
622 #define MCP251863_TXREQ_CH10 0x00000400
623 #define MCP251863_TXREQ_CH11 0x00000800
624 #define MCP251863_TXREQ_CH12 0x00001000
625 #define MCP251863_TXREQ_CH13 0x00002000
626 #define MCP251863_TXREQ_CH14 0x00004000
627 #define MCP251863_TXREQ_CH15 0x00008000
628 
629 #define MCP251863_TXREQ_CH16 0x00010000
630 #define MCP251863_TXREQ_CH17 0x00020000
631 #define MCP251863_TXREQ_CH18 0x00040000
632 #define MCP251863_TXREQ_CH19 0x00080000
633 #define MCP251863_TXREQ_CH20 0x00100000
634 #define MCP251863_TXREQ_CH21 0x00200000
635 #define MCP251863_TXREQ_CH22 0x00400000
636 #define MCP251863_TXREQ_CH23 0x00800000
637 
638 #define MCP251863_TXREQ_CH24 0x01000000
639 #define MCP251863_TXREQ_CH25 0x02000000
640 #define MCP251863_TXREQ_CH26 0x04000000
641 #define MCP251863_TXREQ_CH27 0x08000000
642 #define MCP251863_TXREQ_CH28 0x10000000
643 #define MCP251863_TXREQ_CH29 0x20000000
644 #define MCP251863_TXREQ_CH30 0x40000000
645 #define MCP251863_TXREQ_CH31 0x80000000
646 
651 #define MCP251863_ICODE_FIFO_CH0 0
652 #define MCP251863_ICODE_FIFO_CH1 1
653 #define MCP251863_ICODE_FIFO_CH2 2
654 #define MCP251863_ICODE_FIFO_CH3 3
655 #define MCP251863_ICODE_FIFO_CH4 4
656 #define MCP251863_ICODE_FIFO_CH5 5
657 #define MCP251863_ICODE_FIFO_CH6 6
658 #define MCP251863_ICODE_FIFO_CH7 7
659 
660 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
661  #define MCP251863_ICODE_FIFO_CH8 8
662  #define MCP251863_ICODE_FIFO_CH9 9
663  #define MCP251863_ICODE_FIFO_CH10 10
664  #define MCP251863_ICODE_FIFO_CH11 11
665  #define MCP251863_ICODE_FIFO_CH12 12
666  #define MCP251863_ICODE_FIFO_CH13 13
667  #define MCP251863_ICODE_FIFO_CH14 14
668  #define MCP251863_ICODE_FIFO_CH15 15
669 #endif
670 
671 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
672  #define MCP251863_ICODE_FIFO_CH16 16
673  #define MCP251863_ICODE_FIFO_CH17 17
674  #define MCP251863_ICODE_FIFO_CH18 18
675  #define MCP251863_ICODE_FIFO_CH19 19
676  #define MCP251863_ICODE_FIFO_CH20 20
677  #define MCP251863_ICODE_FIFO_CH21 21
678  #define MCP251863_ICODE_FIFO_CH22 22
679  #define MCP251863_ICODE_FIFO_CH23 23
680  #define MCP251863_ICODE_FIFO_CH24 24
681  #define MCP251863_ICODE_FIFO_CH25 25
682  #define MCP251863_ICODE_FIFO_CH26 26
683  #define MCP251863_ICODE_FIFO_CH27 27
684  #define MCP251863_ICODE_FIFO_CH28 28
685  #define MCP251863_ICODE_FIFO_CH29 29
686  #define MCP251863_ICODE_FIFO_CH30 30
687  #define MCP251863_ICODE_FIFO_CH31 31
688 #endif
689 
690 #define MCP251863_ICODE_TOTAL_CHANNELS 32
691 #define MCP251863_ICODE_NO_INT 64
692 #define MCP251863_ICODE_CERRIF 65
693 #define MCP251863_ICODE_WAKIF 66
694 #define MCP251863_ICODE_RXOVIF 67
695 #define MCP251863_ICODE_ADDRERR_SERRIF 68
696 #define MCP251863_ICODE_MABOV_SERRIF 69
697 #define MCP251863_ICODE_TBCIF 70
698 #define MCP251863_ICODE_MODIF 71
699 #define MCP251863_ICODE_IVMIF 72
700 #define MCP251863_ICODE_TEFIF 73
701 #define MCP251863_ICODE_TXATIF 74
702 #define MCP251863_ICODE_RESERVED 75
703 
708 #define MCP251863_RXCODE_FIFO_CH0 0
709 #define MCP251863_RXCODE_FIFO_CH1 1
710 #define MCP251863_RXCODE_FIFO_CH2 2
711 #define MCP251863_RXCODE_FIFO_CH3 3
712 #define MCP251863_RXCODE_FIFO_CH4 4
713 #define MCP251863_RXCODE_FIFO_CH5 5
714 #define MCP251863_RXCODE_FIFO_CH6 6
715 #define MCP251863_RXCODE_FIFO_CH7 7
716 
717 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
718  #define MCP251863_RXCODE_FIFO_CH8 8
719  #define MCP251863_RXCODE_FIFO_CH9 9
720  #define MCP251863_RXCODE_FIFO_CH10 10
721  #define MCP251863_RXCODE_FIFO_CH11 11
722  #define MCP251863_RXCODE_FIFO_CH12 12
723  #define MCP251863_RXCODE_FIFO_CH13 13
724  #define MCP251863_RXCODE_FIFO_CH14 14
725  #define MCP251863_RXCODE_FIFO_CH15 15
726 #endif
727 
728 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
729  #define MCP251863_RXCODE_FIFO_CH16 16
730  #define MCP251863_RXCODE_FIFO_CH17 17
731  #define MCP251863_RXCODE_FIFO_CH18 18
732  #define MCP251863_RXCODE_FIFO_CH19 19
733  #define MCP251863_RXCODE_FIFO_CH20 20
734  #define MCP251863_RXCODE_FIFO_CH21 21
735  #define MCP251863_RXCODE_FIFO_CH22 22
736  #define MCP251863_RXCODE_FIFO_CH23 23
737  #define MCP251863_RXCODE_FIFO_CH24 24
738  #define MCP251863_RXCODE_FIFO_CH25 25
739  #define MCP251863_RXCODE_FIFO_CH26 26
740  #define MCP251863_RXCODE_FIFO_CH27 27
741  #define MCP251863_RXCODE_FIFO_CH28 28
742  #define MCP251863_RXCODE_FIFO_CH29 29
743  #define MCP251863_RXCODE_FIFO_CH30 30
744  #define MCP251863_RXCODE_FIFO_CH31 31
745 #endif
746 
747 #define MCP251863_RXCODE_TOTAL_CHANNELS 32
748 #define MCP251863_RXCODE_NO_INT 64
749 #define MCP251863_RXCODE_RESERVED 65
750 
755 #define MCP251863_TXCODE_FIFO_CH0 0
756 #define MCP251863_TXCODE_FIFO_CH1 1
757 #define MCP251863_TXCODE_FIFO_CH2 2
758 #define MCP251863_TXCODE_FIFO_CH3 3
759 #define MCP251863_TXCODE_FIFO_CH4 4
760 #define MCP251863_TXCODE_FIFO_CH5 5
761 #define MCP251863_TXCODE_FIFO_CH6 6
762 #define MCP251863_TXCODE_FIFO_CH7 7
763 
764 #ifdef MCP251863_FIFO_08TO15_IMPLEMENTED
765  #define MCP251863_TXCODE_FIFO_CH8 8
766  #define MCP251863_TXCODE_FIFO_CH9 9
767  #define MCP251863_TXCODE_FIFO_CH10 10
768  #define MCP251863_TXCODE_FIFO_CH11 11
769  #define MCP251863_TXCODE_FIFO_CH12 12
770  #define MCP251863_TXCODE_FIFO_CH13 13
771  #define MCP251863_TXCODE_FIFO_CH14 14
772  #define MCP251863_TXCODE_FIFO_CH15 15
773 #endif
774 
775 #ifdef MCP251863_FIFO_16TO31_IMPLEMENTED
776  #define MCP251863_TXCODE_FIFO_CH16 16
777  #define MCP251863_TXCODE_FIFO_CH17 17
778  #define MCP251863_TXCODE_FIFO_CH18 18
779  #define MCP251863_TXCODE_FIFO_CH19 19
780  #define MCP251863_TXCODE_FIFO_CH20 20
781  #define MCP251863_TXCODE_FIFO_CH21 21
782  #define MCP251863_TXCODE_FIFO_CH22 22
783  #define MCP251863_TXCODE_FIFO_CH23 23
784  #define MCP251863_TXCODE_FIFO_CH24 24
785  #define MCP251863_TXCODE_FIFO_CH25 25
786  #define MCP251863_TXCODE_FIFO_CH26 26
787  #define MCP251863_TXCODE_FIFO_CH27 27
788  #define MCP251863_TXCODE_FIFO_CH28 28
789  #define MCP251863_TXCODE_FIFO_CH29 29
790  #define MCP251863_TXCODE_FIFO_CH30 30
791  #define MCP251863_TXCODE_FIFO_CH31 31
792 #endif
793 
794 #define MCP251863_TXCODE_TOTAL_CHANNELS 32
795 #define MCP251863_TXCODE_NO_INT 64
796 #define MCP251863_TXCODE_RESERVED 65
797 
802 #define MCP251863_SYSCLK_40M 0
803 #define MCP251863_SYSCLK_20M 1
804 #define MCP251863_SYSCLK_10M 2
805 
810 #define MCP251863_CLKO_DIV1 0
811 #define MCP251863_CLKO_DIV2 1
812 #define MCP251863_CLKO_DIV4 2
813 #define MCP251863_CLKO_DIV10 3
814 
815 #define N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )
816 #define N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )
817 #define N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )
818 
827 #define MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
828 #define MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
829  // mcp251863_set
831 
846 #define MCP251863_MAP_MIKROBUS( cfg, mikrobus ) \
847  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
848  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
849  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
850  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
851  cfg.stby = MIKROBUS( mikrobus, MIKROBUS_AN ); \
852  cfg.clk = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
853  cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
854  // mcp251863_map // mcp251863
857 
862 typedef struct
863 {
865  uint32_t iso_crc_enable;
873  uint32_t store_in_tef;
874  uint32_t txq_enable;
876 
878 
883 typedef struct
884 {
885  uint8_t iso_crc_enable;
886  uint8_t store_in_tef;
887  uint8_t tx_fifo_size;
889  uint8_t tx_priority;
890  uint8_t rx_fifo_size;
892  uint16_t standard_id;
893  uint32_t extended_id;
894  uint8_t fd_frame;
896  uint8_t ide;
898  uint8_t seq;
899 
901 
906 typedef uint8_t mcp251863_id_t;
907 
912 typedef uint32_t mcp251863_msg_time_stamp_t;
913 
918 typedef struct
919 {
920  uint32_t sid : 11;
921  uint32_t eid : 18;
922  uint32_t sid11 : 1;
923  uint32_t unimplemented1 : 2;
924 
926 
931 typedef struct
932 {
933  uint32_t dlc;
934  uint32_t ide;
935  uint32_t rtr;
936  uint32_t brs;
937  uint32_t fdf;
938  uint32_t esi;
939  uint32_t seq;
940  uint32_t unimplemented1;
941 
943 
948 typedef union
949 {
950  struct {
954  } bf;
955  uint32_t word[ 3 ];
956  uint8_t byte[ 12 ];
957 
959 
964 typedef struct
965 {
966  uint32_t dlc : 4;
967  uint32_t ide : 1;
968  uint32_t rtr : 1;
969  uint32_t brs : 1;
970  uint32_t fdf : 1;
971  uint32_t esi : 1;
972  uint32_t unimplemented1 : 2;
973  uint32_t filter_hit : 5;
974  uint32_t unimplemented2 : 16;
975 
977 
982 typedef union
983 {
984  struct {
988  } bf;
989  uint32_t word[ 3 ];
990  uint8_t byte[ 12 ];
991 
993 
998 typedef union
999 {
1000  struct {
1004  } bf;
1005  uint32_t word[ 3 ];
1006  uint8_t byte[ 12 ];
1007 
1009 
1014 typedef struct
1015 {
1016  uint32_t sid;
1017  uint32_t eid;
1018  uint32_t sid11;
1019  uint32_t exide;
1020  uint32_t unimplemented1;
1021 
1023 
1028 typedef union
1029 {
1031  uint32_t word;
1032  uint8_t byte[ 4 ];
1033 
1035 
1040 typedef struct
1041 {
1042  uint32_t msid;
1043  uint32_t meid;
1044  uint32_t msid11;
1045  uint32_t mide;
1046  uint32_t unimplemented1;
1047 
1049 
1054 typedef union
1055 {
1057  uint32_t word;
1058  uint8_t byte[ 4 ];
1059 
1061 
1062 typedef union
1063 {
1064  uint8_t byte[ 4 ];
1065  uint32_t word;
1066 
1067 } mcp251863_reg_t;
1068 
1073 typedef union
1074 {
1075  struct {
1076  uint32_t d_net_filter_count : 5;
1077  uint32_t iso_crc_enable : 1;
1079  uint32_t unimplemented1 : 1;
1081  uint32_t wake_up_filter_time : 2;
1082  uint32_t unimplemented2 : 1;
1084  uint32_t unimplemented3 : 3;
1086  uint32_t esi_in_gateway_mode : 1;
1088  uint32_t store_in_tef : 1;
1089  uint32_t txq_enable : 1;
1090  uint32_t op_mode : 3;
1091  uint32_t request_op_mode : 3;
1092  uint32_t abort_all_tx : 1;
1094  } bf;
1095  uint32_t word;
1096  uint8_t byte[ 4 ];
1097 
1098 } mcp251863_ctl_t;
1099 
1104 typedef union
1105 {
1106  struct {
1107  uint32_t tx_not_full_ie : 1;
1108  uint32_t unimplemented1 : 1;
1109  uint32_t tx_empty_ie : 1;
1110  uint32_t unimplemented2 : 1;
1111  uint32_t tx_attempt_ie : 1;
1112  uint32_t unimplemented3 : 2;
1113  uint32_t tx_enable : 1;
1114  uint32_t uinc : 1;
1115  uint32_t tx_request : 1;
1116  uint32_t freset : 1;
1117  uint32_t unimplemented4 : 5;
1118  uint32_t tx_priority : 5;
1119  uint32_t tx_attempts : 2;
1120  uint32_t unimplemented5 : 1;
1121  uint32_t fifo_size : 5;
1122  uint32_t pay_load_size : 3;
1123  } tx_bf;
1124  uint32_t word;
1125  uint8_t byte[ 4 ];
1126 
1128 
1133 typedef union
1134 {
1135  struct {
1136  uint32_t tefneie : 1;
1137  uint32_t tefhfie : 1;
1138  uint32_t teffulie : 1;
1139  uint32_t tefovie : 1;
1140  uint32_t unimplemented1 : 1;
1141  uint32_t time_stamp_enable : 1;
1142  uint32_t unimplemented2 : 2;
1143  uint32_t uinc : 1;
1144  uint32_t unimplemented3 : 1;
1145  uint32_t freset : 1;
1146  uint32_t unimplemented4 : 13;
1147  uint32_t fifo_size : 5;
1148  uint32_t unimplemented5 : 3;
1149  } bf;
1150  uint32_t word;
1151  uint8_t byte[ 4 ];
1152 
1154 
1159 typedef union
1160 {
1161  struct {
1162  uint32_t rx_not_empty_ie : 1;
1163  uint32_t rx_half_full_ie : 1;
1164  uint32_t rx_full_ie : 1;
1165  uint32_t rx_over_flow_ie : 1;
1166  uint32_t unimplemented1 : 1;
1167  uint32_t rx_time_stamp_enable : 1;
1168  uint32_t unimplemented2 : 1;
1169  uint32_t tx_enable : 1;
1170  uint32_t uinc : 1;
1171  uint32_t unimplemented3 : 1;
1172  uint32_t freset : 1;
1173  uint32_t unimplemented4 : 13;
1174  uint32_t fifo_size : 5;
1175  uint32_t pay_load_size : 3;
1176  } rx_bf;
1177 
1178  struct {
1179  uint32_t tx_not_full_ie : 1;
1180  uint32_t tx_half_full_ie : 1;
1181  uint32_t tx_empty_ie : 1;
1182  uint32_t unimplemented1 : 1;
1183  uint32_t tx_attempt_ie : 1;
1184  uint32_t unimplemented2 : 1;
1185  uint32_t rtr_enable : 1;
1186  uint32_t tx_enable : 1;
1187  uint32_t uinc : 1;
1188  uint32_t tx_request : 1;
1189  uint32_t freset : 1;
1190  uint32_t unimplemented3 : 5;
1191  uint32_t tx_priority : 5;
1192  uint32_t tx_attempts : 2;
1193  uint32_t unimplemented4 : 1;
1194  uint32_t fifo_size : 5;
1195  uint32_t pay_load_size : 3;
1196  } tx_bf;
1197  uint32_t word;
1198  uint8_t byte[ 4 ];
1199 
1201 
1206 typedef union
1207 {
1208  struct {
1209  uint32_t buffer_pointer : 5;
1210  uint32_t unimplemented1 : 2;
1211  uint32_t enable : 1;
1212  } bf;
1213  uint8_t byte;
1214 
1216 
1221 typedef union
1222 {
1223  struct {
1224  uint32_t pll_enable : 1;
1225  uint32_t unimplemented1 : 1;
1226  uint32_t osc_disable : 1;
1227  uint32_t unimplemented2 : 1;
1228  uint32_t sclk_divide : 1;
1229  uint32_t clk_out_divide : 2;
1230  uint32_t unimplemented3 : 1;
1231  uint32_t pll_ready : 1;
1232  uint32_t unimplemented4 : 1;
1233  uint32_t osc_ready : 1;
1234  uint32_t unimplemented5 : 1;
1235  uint32_t sclk_ready : 1;
1236  uint32_t unimplemented6 : 19;
1237  } bf;
1238  uint32_t word;
1239  uint8_t byte[ 4 ];
1240 
1242 
1247 typedef struct
1248 {
1249  uint32_t pll_enable;
1250  uint32_t osc_disable;
1251  uint32_t sclk_divide;
1252  uint32_t clk_out_divide;
1253 
1255 
1260 typedef union
1261 {
1262  struct {
1263  uint32_t tris0 : 1;
1264  uint32_t tris1 : 1;
1265  uint32_t unimplemented1 : 2;
1267  uint32_t auto_sleep_enable : 1;
1268  uint32_t xcr_stby_enable : 1;
1269  uint32_t unimplemented2 : 1;
1270  uint32_t lat0 : 1;
1271  uint32_t lat1 : 1;
1272  uint32_t unimplemented3 : 5;
1273  uint32_t hvdetsel : 1;
1274  uint32_t gpio0 : 1;
1275  uint32_t gpio1 : 1;
1276  uint32_t unimplemented4 : 6;
1277  uint32_t pin_mode0 : 1;
1278  uint32_t pin_mode1 : 1;
1279  uint32_t unimplemented5 : 2;
1280  uint32_t tx_can_open_drain : 1;
1281  uint32_t sof_output_enable : 1;
1282  uint32_t int_pin_open_drain : 1;
1283  uint32_t unimplemented6 : 1;
1284  } bf;
1285  uint32_t word;
1286  uint8_t byte[ 4 ];
1287 
1289 
1294 typedef union
1295 {
1296  struct {/* can_fd_ubp */
1297  uint32_t ecc_en : 1;
1298  uint32_t secie : 1;
1299  uint32_t dedie : 1;
1300  uint32_t unimplemented1 : 5;
1301  uint32_t parity : 7;
1302  uint32_t unimplemented2 : 17;
1303  } bf;
1304  uint32_t word;
1305  uint8_t byte[ 4 ];
1306 
1308 
1313 typedef struct
1314 {
1315  uint32_t d_net_filter_count : 5;
1316  uint32_t iso_crc_enable : 1;
1319  uint32_t wake_up_filter_time : 2;
1322  uint32_t esi_in_gateway_mode : 1;
1324  uint32_t store_in_tef : 1;
1325  uint32_t txq_enable : 1;
1327 
1329 
1334 typedef struct
1335 {
1336  uint32_t rtr_enable;
1337  uint32_t tx_priority;
1338  uint32_t tx_attempts;
1339  uint32_t fifo_size;
1340  uint32_t pay_load_size;
1341 
1343 
1348 typedef struct
1349 {
1350  uint32_t tx_priority : 5;
1351  uint32_t tx_attempts : 2;
1352  uint32_t fifo_size : 5;
1353  uint32_t pay_load_size : 3;
1354 
1356 
1361 typedef struct
1362 {
1364  uint32_t fifo_size;
1365  uint32_t pay_load_size;
1366 
1368 
1369 
1374 typedef union
1375 {
1376  struct {
1377  uint32_t user_address : 12;
1378  uint32_t unimplemented1 : 20;
1379  } bf;
1380  uint32_t word;
1381  uint8_t byte[ 4 ];
1382 
1384 
1389 typedef struct
1390 {
1392  uint32_t fifo_size;
1393 
1395 
1400 typedef union
1401 {
1402  struct {
1403  uint32_t swj : 7;
1404  uint32_t unimplemented1 : 1;
1405  uint32_t tseg2 : 7;
1406  uint32_t unimplemented2 : 1;
1407  uint32_t tseg1 : 8;
1408  uint32_t brp : 8;
1409  } bf;
1410  uint32_t word;
1411  uint8_t byte[ 4 ];
1412 
1414 
1419 typedef union
1420 {
1421  struct {
1422  uint32_t swj : 4;
1423  uint32_t unimplemented1 : 4;
1424  uint32_t tseg2 : 4;
1425  uint32_t unimplemented2 : 4;
1426  uint32_t tseg1 : 5;
1427  uint32_t unimplemented3 : 3;
1428  uint32_t brp : 8;
1429  } bf;
1430  uint32_t word;
1431  uint8_t byte[ 4 ];
1432 
1434 
1439 typedef union
1440 {
1441  struct {
1442  uint32_t tdc_value : 6;
1443  uint32_t unimplemented1 : 2;
1444  uint32_t tdc_offset : 7;
1445  uint32_t unimplemented2 : 1;
1446  uint32_t tdc_mode : 2;
1447  uint32_t unimplemented3 : 6;
1448  uint32_t sid11_enable : 1;
1449  uint32_t edge_filter_enable : 1;
1450  uint32_t unimplemented4 : 6;
1451  } bf;
1452  uint32_t word;
1453  uint8_t byte[ 4 ];
1454 
1456 
1461 typedef union
1462 {
1463  struct {
1464  uint32_t tbc_prescaler : 10;
1465  uint32_t unimplemented1 : 6;
1466  uint32_t tbc_enable : 1;
1467  uint32_t time_stamp_eof : 1;
1468  uint32_t unimplemented2 : 14;
1469  } bf;
1470  uint32_t word;
1471  uint8_t byte[ 4 ];
1472 
1474 
1479 typedef struct
1480 {
1481  uint32_t txie : 1;
1482  uint32_t rxie : 1;
1483  uint32_t tbcie : 1;
1484  uint32_t modie : 1;
1485  uint32_t tefie : 1;
1486  uint32_t unimplemented2 : 3;
1487 
1488  uint32_t eccie : 1;
1489  uint32_t spicrcie : 1;
1490  uint32_t txatie : 1;
1491  uint32_t rxovie : 1;
1492  uint32_t serrie : 1;
1493  uint32_t cerrie : 1;
1494  uint32_t wakie : 1;
1495  uint32_t ivmie : 1;
1496 
1498 
1503 typedef union
1504 {
1506  uint16_t word;
1507  uint8_t byte[ 2 ];
1508 
1510 
1515 typedef union
1516 {
1517  struct {
1518  uint32_t icode : 7;
1519  uint32_t unimplemented1 : 1;
1520  uint32_t filter_hit : 5;
1521  uint32_t unimplemented2 : 3;
1522  uint32_t tx_code : 7;
1523  uint32_t unimplemented3 : 1;
1524  uint32_t rx_code : 7;
1525  uint32_t unimplemented4 : 1;
1526  } bf;
1527  uint32_t word;
1528  uint8_t byte[ 4 ];
1529 
1531 
1536 typedef struct
1537 {
1538  uint32_t TXIF : 1;
1539  uint32_t RXIF : 1;
1540  uint32_t TBCIF : 1;
1541  uint32_t MODIF : 1;
1542  uint32_t TEFIF : 1;
1543  uint32_t unimplemented1 : 3;
1544 
1545  uint32_t ECCIF : 1;
1546  uint32_t SPICRCIF : 1;
1547  uint32_t TXATIF : 1;
1548  uint32_t RXOVIF : 1;
1549  uint32_t SERRIF : 1;
1550  uint32_t CERRIF : 1;
1551  uint32_t WAKIF : 1;
1552  uint32_t IVMIF : 1;
1553 
1555 
1560 typedef union
1561 {
1563  uint16_t word;
1564  uint8_t byte[ 2 ];
1565 
1567 
1572 typedef union
1573 {
1574  struct {
1577  } bf;
1578  uint32_t word;
1579  uint8_t byte[ 4 ];
1580 
1581 } mcp251863_int_t;
1582 
1587 typedef union
1588 {
1589  struct {
1590  uint32_t rx_error_count : 8;
1591  uint32_t tx_error_count : 8;
1592  uint32_t error_state_warning : 1;
1598  uint32_t unimplemented1 : 10;
1599  } bf;
1600  uint32_t word;
1601  uint8_t byte[ 4 ];
1602 
1604 
1609 typedef union
1610 {
1611  struct {
1612  uint32_t tef_not_empty_if : 1;
1613  uint32_t tef_half_full_if : 1;
1614  uint32_t tef_full_if : 1;
1615  uint32_t tef_ov_if : 1;
1616  uint32_t unimplemented1 : 28;
1617  } bf;
1618  uint32_t word;
1619  uint8_t byte[ 4 ];
1620 
1621 } mcp251863_tef_t;
1622 
1627 typedef union
1628 {
1629  struct {
1630  uint32_t tx_not_full_if : 1;
1631  uint32_t unimplemented1 : 1;
1632  uint32_t tx_empty_if : 1;
1633  uint32_t unimplemented2 : 1;
1634  uint32_t tx_attempt_if : 1;
1635  uint32_t tx_error : 1;
1636  uint32_t tx_lost_arbitration : 1;
1637  uint32_t tx_aborted : 1;
1638  uint32_t fifo_index : 5;
1639  uint32_t unimplemented3 : 19;
1640  } tx_bf;
1641  uint32_t word;
1642  uint8_t byte[ 4 ];
1643 
1645 
1650 typedef union
1651 {
1652  struct {
1653  uint32_t rx_not_empty_if : 1;
1654  uint32_t rx_half_full_if : 1;
1655  uint32_t rx_full_if : 1;
1656  uint32_t rx_over_flow_if : 1;
1657  uint32_t unimplemented1 : 4;
1658  uint32_t fifo_index : 5;
1659  uint32_t unimplemented2 : 19;
1660  } rx_bf;
1661 
1662  struct {
1663  uint32_t tx_not_full_if : 1;
1664  uint32_t tx_half_full_if : 1;
1665  uint32_t tx_empty_if : 1;
1666  uint32_t unimplemented1 : 1;
1667  uint32_t tx_attempt_if : 1;
1668  uint32_t tx_error : 1;
1669  uint32_t tx_lost_arbitration : 1;
1670  uint32_t tx_aborted : 1;
1671  uint32_t fifo_index : 5;
1672  uint32_t unimplemented2 : 19;
1673  } tx_bf;
1674  uint32_t word;
1675  uint8_t byte[ 4 ];
1676 
1678 
1683 typedef union
1684 {
1685  struct {
1686  uint32_t crc : 16;
1687  uint32_t crcerrif : 1;
1688  uint32_t ferrif : 1;
1689  uint32_t unimplemented1 : 6;
1690  uint32_t crcerrie : 1;
1691  uint32_t ferrie : 1;
1692  uint32_t unimplemented2 : 6;
1693  } bf;
1694  uint32_t word;
1695  uint8_t byte[ 4 ];
1696 
1697 } mcp251863_crc_t;
1698 
1703 typedef union
1704 {
1705  struct {
1706  uint32_t unimplemented1 : 1;
1707  uint32_t secif : 1;
1708  uint32_t dedif : 1;
1709  uint32_t unimplemented2 : 13;
1710  uint32_t error_address : 12;
1711  uint32_t unimplemented3 : 4;
1712  } bf;
1713  uint32_t word;
1714  uint8_t byte[ 4 ];
1715 
1717 
1722 typedef struct
1723 {
1724  uint32_t pll_ready : 1;
1725  uint32_t osc_ready : 1;
1726  uint32_t sclk_ready : 1;
1727 
1729 
1734 typedef struct
1735 {
1736  uint32_t n_bit0_err : 1;
1737  uint32_t n_bit1_err : 1;
1738  uint32_t n_ack_err : 1;
1739  uint32_t n_form_err : 1;
1740  uint32_t n_stuff_err : 1;
1741  uint32_t n_crc_err : 1;
1742  uint32_t unimplemented1 : 1;
1743  uint32_t txbo_err : 1;
1744  uint32_t d_bit0_err : 1;
1745  uint32_t d_bit1_err : 1;
1746  uint32_t unimplemented2 : 1;
1747  uint32_t d_form_err : 1;
1748  uint32_t d_stuff_err : 1;
1749  uint32_t d_crc_err : 1;
1750  uint32_t esi : 1;
1751  uint32_t dlc_mismatch : 1;
1752 
1754 
1759 typedef struct
1760 {
1761  uint8_t n_rec;
1762  uint8_t n_tec;
1763  uint8_t d_rec;
1764  uint8_t d_tec;
1765 
1767 
1772 typedef union
1773 {
1774  struct {
1778  } bf;
1779  uint32_t word[ 2 ];
1780  uint8_t byte[ 8 ];
1781 
1783 
1788 typedef union
1789 {
1790  struct {
1791  uint32_t n_rx_error_count : 8;
1792  uint32_t n_tx_error_count : 8;
1793  uint32_t d_rx_error_count : 8;
1794  uint32_t d_tx_error_count : 8;
1795  } bf;
1796  uint32_t word;
1797  uint8_t byte[ 4 ];
1798 
1800 
1805 typedef union
1806 {
1807  struct {
1808  uint32_t error_free_msg_count : 16;
1809  uint32_t n_bit0_error : 1;
1810  uint32_t n_bit1_error : 1;
1811  uint32_t n_ack_error : 1;
1812  uint32_t n_form_error : 1;
1813  uint32_t n_stuff_error : 1;
1814  uint32_t n_crc_error : 1;
1815  uint32_t unimplemented1 : 1;
1816  uint32_t txbo_error : 1;
1817  uint32_t d_bit0_error : 1;
1818  uint32_t d_bit1_error : 1;
1819  uint32_t d_ack_error : 1;
1820  uint32_t d_form_error : 1;
1821  uint32_t d_stuff_error : 1;
1822  uint32_t d_crc_error : 1;
1823  uint32_t esi : 1;
1824  uint32_t unimplemented2 : 1;
1825  } bf;
1826  uint32_t word;
1827  uint8_t byte[ 4 ];
1828 
1830 
1835 typedef struct
1836 {
1837  uint16_t address;
1838  uint8_t *rxd;
1839  uint16_t n_bytes;
1840  uint8_t *txd;
1841  uint32_t txd_num_bytes;
1842 
1844 
1849 typedef struct
1850 {
1852  uint8_t tx_flags;
1853  uint8_t rx_flags;
1854  uint8_t error_flags;
1855  uint8_t tec;
1856  uint8_t rec;
1857  uint8_t op_mode;
1858  uint32_t tx_id;
1859 
1868 
1870 
1875 typedef struct
1876 {
1877  // Output pins
1878  digital_out_t stby;
1880  // Input pins
1881  digital_in_t clk;
1882  digital_in_t int_pin;
1884  // Modules
1885  spi_master_t spi;
1887  pin_name_t chip_select;
1891 
1892 } mcp251863_t;
1893 
1898 typedef struct
1899 {
1900  // Communication gpio pins
1901  pin_name_t miso;
1902  pin_name_t mosi;
1903  pin_name_t sck;
1904  pin_name_t cs;
1906  // Additional gpio pins
1907  pin_name_t stby;
1908  pin_name_t clk;
1909  pin_name_t int_pin;
1911  // static variable
1912  uint32_t spi_speed;
1913  spi_master_mode_t spi_mode;
1914  spi_master_chip_select_polarity_t cs_polarity;
1916 } mcp251863_cfg_t;
1917 
1922 typedef enum
1923 {
1925  MCP251863_ERROR = -1
1926 
1928 
1945 
1960 
1975 
1990 err_t mcp251863_generic_write ( mcp251863_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
1991 
2006 err_t mcp251863_generic_read ( mcp251863_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
2007 
2020 err_t mcp251863_transmit_message ( mcp251863_t *ctx, uint8_t *data_in, uint16_t data_len );
2021 
2034 err_t mcp251863_receive_message ( mcp251863_t *ctx, uint8_t *data_out, uint16_t *data_len );
2035 
2047 
2060 err_t mcp251863_read_byte ( mcp251863_t *ctx, uint16_t address, uint8_t *data_out );
2061 
2074 err_t mcp251863_write_byte ( mcp251863_t *ctx, uint16_t address, uint8_t data_in );
2075 
2088 err_t mcp251863_read_word ( mcp251863_t *ctx, uint16_t address, uint32_t *data_out );
2089 
2102 err_t mcp251863_write_word ( mcp251863_t *ctx, uint16_t address, uint32_t data_in );
2103 
2116 err_t mcp251863_read_half_word ( mcp251863_t *ctx, uint16_t address, uint16_t *data_out );
2117 
2130 err_t mcp251863_write_half_word ( mcp251863_t *ctx, uint16_t address, uint16_t data_in );
2131 
2147 err_t mcp251863_write_byte_safe ( mcp251863_t *ctx, uint16_t address, uint8_t data_in );
2148 
2164 err_t mcp251863_write_word_safe ( mcp251863_t *ctx, uint16_t address, uint32_t data_in );
2165 
2179 err_t mcp251863_read_byte_array ( mcp251863_t *ctx, uint16_t address, uint8_t *data_out, uint16_t n_bytes );
2180 
2193 err_t mcp251863_read_byte_array_with_crc ( mcp251863_t *ctx, bool from_ram, bool *crc_is_correct );
2194 
2208 err_t mcp251863_write_byte_array ( mcp251863_t *ctx, uint16_t address, uint8_t *data_in, uint16_t n_bytes );
2209 
2221 err_t mcp251863_write_byte_array_with_crc ( mcp251863_t *ctx, bool from_ram );
2222 
2236 err_t mcp251863_read_word_array ( mcp251863_t *ctx, uint16_t address, uint32_t *data_out, uint16_t n_words );
2237 
2251 err_t mcp251863_write_word_array ( mcp251863_t *ctx, uint16_t address, uint32_t *data_in, uint16_t n_words );
2252 
2265 
2273 
2286 err_t mcp251863_operation_mode_select ( mcp251863_t *ctx, uint8_t op_mode );
2287 
2296 
2310 
2318 
2331 
2339 
2353 err_t mcp251863_transmit_channel_load ( mcp251863_t *ctx, uint8_t channel, mcp251863_tx_msg_obj_t *tx_obj, bool flush );
2354 
2366 err_t mcp251863_transmit_channel_flush ( mcp251863_t *ctx, uint8_t channel );
2367 
2380 err_t mcp251863_transmit_channel_status_get ( mcp251863_t *ctx, uint8_t channel, uint16_t *status );
2381 
2393 int8_t mcp251863_transmit_channel_reset ( mcp251863_t *ctx, uint8_t channel );
2394 
2407 err_t mcp251863_transmit_channel_update ( mcp251863_t *ctx, uint8_t channel, bool flush );
2408 
2420 err_t mcp251863_transmit_request_set ( mcp251863_t *ctx, uint32_t tx_req );
2421 
2433 err_t mcp251863_transmit_request_get ( mcp251863_t *ctx, uint32_t* tx_req );
2434 
2446 err_t mcp251863_transmit_channel_abort ( mcp251863_t *ctx, uint8_t channel );
2447 
2459 
2472 
2486 
2500 
2514 err_t mcp251863_filter_to_fifo_link ( mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable );
2515 
2527 err_t mcp251863_filter_enable ( mcp251863_t *ctx, uint8_t filter );
2528 
2541 err_t mcp251863_filter_disable ( mcp251863_t *ctx, uint8_t filter );
2542 
2556 
2569 err_t mcp251863_receive_channel_configure ( mcp251863_t *ctx, uint8_t channel,
2570  mcp251863_rx_fifo_cfg_t *config );
2571 
2579 
2592 err_t mcp251863_receive_channel_status_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *status );
2593 
2609 err_t mcp251863_receive_message_get ( mcp251863_t *ctx, uint8_t channel, mcp251863_rx_msg_obj_t *rx_obj );
2610 
2622 err_t mcp251863_receive_channel_reset ( mcp251863_t *ctx, uint8_t channel );
2623 
2635 err_t mcp251863_receive_channel_update ( mcp251863_t *ctx, uint8_t channel );
2636 
2648 err_t mcp251863_tef_status_get ( mcp251863_t *ctx, uint8_t *status );
2649 
2664 
2676 
2688 
2701 
2711 
2723 err_t mcp251863_module_event_get ( mcp251863_t *ctx, uint16_t *flags );
2724 
2737 err_t mcp251863_module_event_enable ( mcp251863_t *ctx, uint16_t flags );
2738 
2751 err_t mcp251863_module_event_disable ( mcp251863_t *ctx, uint16_t flags );
2752 
2766 err_t mcp251863_module_event_clear ( mcp251863_t *ctx, uint16_t flags );
2767 
2779 err_t mcp251863_module_event_rx_code_get ( mcp251863_t *ctx, uint8_t *rx_code );
2780 
2792 err_t mcp251863_module_event_tx_code_get ( mcp251863_t *ctx, uint8_t *tx_code );
2793 
2805 err_t mcp251863_module_event_filter_hit_get ( mcp251863_t *ctx, uint8_t* filter_hit );
2806 
2818 err_t mcp251863_module_event_icode_get ( mcp251863_t *ctx, uint8_t *icode );
2819 
2832 err_t mcp251863_transmit_channel_event_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *flags );
2833 
2845 err_t mcp251863_transmit_event_get ( mcp251863_t *ctx, uint32_t *txif );
2846 
2858 err_t mcp251863_transmit_event_attempt_get ( mcp251863_t *ctx, uint32_t *txatif );
2859 
2872 err_t mcp251863_transmit_channel_index_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *idx );
2873 
2887 err_t mcp251863_transmit_channel_event_enable( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2888 
2902 err_t mcp251863_transmit_channel_event_disable ( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2903 
2917 
2930 err_t mcp251863_receive_channel_event_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *flags );
2931 
2943 err_t mcp251863_receive_event_get ( mcp251863_t *ctx, uint32_t *rxif );
2944 
2956 err_t mcp251863_receive_event_overflow_get ( mcp251863_t *ctx, uint32_t *rxovif );
2957 
2967 int8_t mcp251863_receive_channel_index_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *idx );
2968 
2982 err_t mcp251863_receive_channel_event_enable ( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2983 
2997 err_t mcp251863_receive_channel_event_disable ( mcp251863_t *ctx, uint8_t channel, uint8_t flags );
2998 
3012 
3025 err_t mcp251863_tef_event_get ( mcp251863_t *ctx, uint8_t* flags );
3026 
3039 err_t mcp251863_tef_event_enable ( mcp251863_t *ctx, uint8_t flags );
3040 
3053 err_t mcp251863_tef_event_disable ( mcp251863_t *ctx, uint8_t flags );
3054 
3068 
3081 
3093 err_t mcp251863_error_count_receive_get ( mcp251863_t *ctx, uint8_t *rec );
3094 
3106 err_t mcp251863_error_state_get ( mcp251863_t *ctx, uint8_t *flags );
3107 
3121 err_t mcp251863_error_count_state_get ( mcp251863_t *ctx, uint8_t *tec, uint8_t *rec, uint8_t *flags );
3122 
3136 
3148 
3161 
3174 
3187 err_t mcp251863_ecc_event_get ( mcp251863_t *ctx, uint8_t *flags );
3188 
3200 err_t mcp251863_ecc_parity_set ( mcp251863_t *ctx, uint8_t parity );
3201 
3213 err_t mcp251863_ecc_parity_get ( mcp251863_t *ctx, uint8_t *parity );
3214 
3226 err_t mcp251863_ecc_error_address_get ( mcp251863_t *ctx, uint16_t *address );
3227 
3240 err_t mcp251863_ecc_event_enable ( mcp251863_t *ctx, uint8_t flags );
3241 
3254 err_t mcp251863_ecc_event_disable ( mcp251863_t *ctx, uint8_t flags );
3255 
3268 err_t mcp251863_ecc_event_clear ( mcp251863_t *ctx, uint8_t flags );
3269 
3282 err_t mcp251863_crc_event_enable ( mcp251863_t *ctx, uint8_t flags );
3283 
3296 err_t mcp251863_crc_event_disable ( mcp251863_t *ctx, uint8_t flags );
3297 
3310 err_t mcp251863_crc_event_clear ( mcp251863_t *ctx, uint8_t flags );
3311 
3323 err_t mcp251863_crc_event_get ( mcp251863_t *ctx, uint8_t *flags );
3324 
3336 err_t mcp251863_crc_value_get ( mcp251863_t *ctx, uint16_t *crc );
3337 
3349 err_t mcp251863_ram_init ( mcp251863_t *ctx, uint8_t rx_data );
3350 
3363 
3376 
3388 err_t mcp251863_time_stamp_get ( mcp251863_t *ctx, uint32_t *time_stamp );
3389 
3401 err_t mcp251863_time_stamp_set ( mcp251863_t *ctx, uint32_t ts );
3402 
3416 
3428 err_t mcp251863_time_stamp_prescaler_set ( mcp251863_t *ctx, uint16_t time_stamp );
3429 
3443 
3459 
3467 
3480 
3493 err_t mcp251863_bit_time_configure ( mcp251863_t *ctx, uint8_t bit_time, uint8_t clk );
3494 
3507 
3520 
3533 
3546 
3559 
3572 
3586 err_t mcp251863_gpio_mode_configure ( mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1 );
3587 
3601 err_t mcp251863_gpio_direction_configure ( mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1 );
3602 
3615 
3628 
3642 
3656 
3670 err_t mcp251863_gpio_pin_set ( mcp251863_t *ctx, uint8_t pos, uint8_t latch );
3671 
3684 err_t mcp251863_gpio_pin_read ( mcp251863_t *ctx, uint8_t pos, uint8_t *state );
3685 
3699 
3706 uint32_t mcp251863_dlc_to_data_bytes ( uint8_t dlc );
3707 
3720 err_t mcp251863_fifo_index_get ( mcp251863_t *ctx, uint8_t channel, uint8_t *data_out );
3721 
3731 uint16_t mcp251863_calculate_crc16 ( uint8_t *data_pointer, uint16_t size );
3732 
3739 uint8_t mcp251863_data_bytes_to_dlc ( uint8_t num );
3740 
3741 #ifdef __cplusplus
3742 }
3743 #endif
3744 #endif // MCP251863_H
3745  // mcp251863
3747 
3748 // ------------------------------------------------------------------------ END
mcp251863_cfg_t::spi_speed
uint32_t spi_speed
Definition: mcp251863.h:1912
mcp251863_nbt_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1404
mcp251863_tx_que_ctl_t::freset
uint32_t freset
Definition: mcp251863.h:1116
mcp251863_tef_ctl_t
MCP251863 Click Transmit Event FIFO Control Register.
Definition: mcp251863.h:1134
mcp251863_mask_obj_id_t::meid
uint32_t meid
Definition: mcp251863.h:1043
mcp251863_read_word
err_t mcp251863_read_word(mcp251863_t *ctx, uint16_t address, uint32_t *data_out)
SPI Read Word.
mcp251863_fifo_stat_t::rx_over_flow_if
uint32_t rx_over_flow_if
Definition: mcp251863.h:1656
mcp251863_write_half_word
err_t mcp251863_write_half_word(mcp251863_t *ctx, uint16_t address, uint16_t data_in)
SPI Write Half Word.
mcp251863_bus_error_count_t::n_rec
uint8_t n_rec
Definition: mcp251863.h:1761
mcp251863_transmit_channel_event_attempt_clear
err_t mcp251863_transmit_channel_event_attempt_clear(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Event Clear.
mcp251863_transmit_request_get
err_t mcp251863_transmit_request_get(mcp251863_t *ctx, uint32_t *tx_req)
Get TXREQ register.
mcp251863_int_vec_t
MCP251863 Click Interrupt Vector Register.
Definition: mcp251863.h:1516
mcp251863_ctl_t::esi_in_gateway_mode
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1086
mcp251863_rx_msg_obj_t::ctrl
mcp251863_rx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:986
mcp251863_fifo_stat_t::tx_not_full_if
uint32_t tx_not_full_if
Definition: mcp251863.h:1663
mcp251863_rx_msg_obj_t::time_stamp
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:987
mcp251863_osc_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1230
mcp251863_tef_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1146
mcp251863_io_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1272
mcp251863_tx_msg_obj_ctl_t::fdf
uint32_t fdf
Definition: mcp251863.h:937
mcp251863_tx_que_ctl_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1119
mcp251863_cfg_t::sck
pin_name_t sck
Definition: mcp251863.h:1903
mcp251863_bit_time_configure_data_10_mhz
err_t mcp251863_bit_time_configure_data_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 10MHz system clock.
mcp251863_ecc_sta_t::error_address
uint32_t error_address
Definition: mcp251863.h:1710
mcp251863_bus_diag1_t::d_form_error
uint32_t d_form_error
Definition: mcp251863.h:1820
mcp251863_int_en_t::ivmie
uint32_t ivmie
Definition: mcp251863.h:1495
mcp251863_nbt_cfg_t::swj
uint32_t swj
Definition: mcp251863.h:1403
mcp251863_fifo_ctl_t
MCP251863 Click FIFO Control Register.
Definition: mcp251863.h:1160
mcp251863_int_en_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1486
mcp251863_cfg_t
MCP251863 Click configuration object.
Definition: mcp251863.h:1899
mcp251863_ctl_t::wake_up_filter_time
uint32_t wake_up_filter_time
Definition: mcp251863.h:1081
mcp251863_ecc_event_enable
err_t mcp251863_ecc_event_enable(mcp251863_t *ctx, uint8_t flags)
ECC Event Enable.
mcp251863_ecc_ctl_t::dedie
uint32_t dedie
Definition: mcp251863.h:1299
mcp251863_dbt_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1423
mcp251863_bus_diag1_t::n_ack_error
uint32_t n_ack_error
Definition: mcp251863.h:1811
mcp251863_bus_diag_flags_t::n_stuff_err
uint32_t n_stuff_err
Definition: mcp251863.h:1740
mcp251863_ecc_enable
err_t mcp251863_ecc_enable(mcp251863_t *ctx)
Enable ECC.
mcp251863_tef_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1142
mcp251863_ecc_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1302
mcp251863_dbt_cfg_t::brp
uint32_t brp
Definition: mcp251863.h:1428
mcp251863_rx_fifo_cfg_t
MCP251863 Click CAN Receive Channel Configure.
Definition: mcp251863.h:1362
mcp251863_gpio_transmit_pin_open_drain_configure
err_t mcp251863_gpio_transmit_pin_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain TXCAN.
mcp251863_oscillator_status_get
err_t mcp251863_oscillator_status_get(mcp251863_t *ctx, mcp251863_osc_sta_t *status)
Get Oscillator Status.
mcp251863_bit_time_configure_data_40_mhz
err_t mcp251863_bit_time_configure_data_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Data bit time for 40MHz system clock.
mcp251863_receive_channel_update
err_t mcp251863_receive_channel_update(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Update.
mcp251863_transmit_channel_abort
err_t mcp251863_transmit_channel_abort(mcp251863_t *ctx, uint8_t channel)
Abort transmission of single FIFO.
mcp251863_fifo_ctl_t::tx_enable
uint32_t tx_enable
Definition: mcp251863.h:1169
mcp251863_tx_msg_obj_t::id
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:951
mcp251863_tef_ctl_t::tefhfie
uint32_t tefhfie
Definition: mcp251863.h:1137
mcp251863_transmit_channel_event_get
err_t mcp251863_transmit_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Transmit FIFO Event Get.
mcp251863_bus_diag_flags_t::d_crc_err
uint32_t d_crc_err
Definition: mcp251863.h:1749
mcp251863_device_net_filter_count_set
err_t mcp251863_device_net_filter_count_set(mcp251863_t *ctx, uint8_t dnfc)
Set Device Net Filter Count.
mcp251863_trec_t::tx_error_state_warning
uint32_t tx_error_state_warning
Definition: mcp251863.h:1594
mcp251863_int_flags_stat_t::RXOVIF
uint32_t RXOVIF
Definition: mcp251863.h:1548
mcp251863_trec_t
MCP251863 Click Transmit/Receive Error Count Register.
Definition: mcp251863.h:1588
mcp251863_can_cfg_t::wake_up_filter_enable
uint32_t wake_up_filter_enable
Definition: mcp251863.h:867
mcp251863_oscillator_enable
err_t mcp251863_oscillator_enable(mcp251863_t *ctx)
Enable oscillator to wake-up from sleep.
mcp251863_bus_diag1_t::esi
uint32_t esi
Definition: mcp251863.h:1823
mcp251863_transmit_channel_flush
err_t mcp251863_transmit_channel_flush(mcp251863_t *ctx, uint8_t channel)
TX Channel Flush.
mcp251863_mask_obj_t
MCP251863 Click Mask Object Register.
Definition: mcp251863.h:1055
mcp251863_dbt_cfg_t::swj
uint32_t swj
Definition: mcp251863.h:1422
mcp251863_oscillator_control_object_reset
void mcp251863_oscillator_control_object_reset(mcp251863_div_ctl_t *ctrl)
Reset Oscillator Control.
mcp251863_div_ctl_t
MCP251863 Click Oscillator Control.
Definition: mcp251863.h:1248
mcp251863_trec_t::tx_error_state_passive
uint32_t tx_error_state_passive
Definition: mcp251863.h:1596
mcp251863_tx_msg_obj_ctl_t::seq
uint32_t seq
Definition: mcp251863.h:939
T_MCP251863_cfg_t::system_error_to_listen_only
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1323
mcp251863_bus_diag_t::error_count
mcp251863_bus_error_count_t error_count
Definition: mcp251863.h:1775
mcp251863_fifo_ctl_t::tx_empty_ie
uint32_t tx_empty_ie
Definition: mcp251863.h:1181
mcp251863_ctl_t::system_error_to_listen_only
uint32_t system_error_to_listen_only
Definition: mcp251863.h:1087
mcp251863_ecc_sta_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1709
mcp251863_osc_sta_t::sclk_ready
uint32_t sclk_ready
Definition: mcp251863.h:1726
mcp251863_calculate_crc16
uint16_t mcp251863_calculate_crc16(uint8_t *data_pointer, uint16_t size)
Calculate CRC16.
mcp251863_module_event_icode_get
err_t mcp251863_module_event_icode_get(mcp251863_t *ctx, uint8_t *icode)
Get ICODE.
mcp251863_fifo_ctl_t::rx_half_full_ie
uint32_t rx_half_full_ie
Definition: mcp251863.h:1163
mcp251863_tx_fifo_cfg_t
MCP251863 Click CAN Transmit Channel Configure.
Definition: mcp251863.h:1335
mcp251863_crc_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1692
mcp251863_div_ctl_t::clk_out_divide
uint32_t clk_out_divide
Definition: mcp251863.h:1252
mcp251863_io_ctl_t::sof_output_enable
uint32_t sof_output_enable
Definition: mcp251863.h:1281
mcp251863_rx_msg_obj_ctl_t::fdf
uint32_t fdf
Definition: mcp251863.h:970
mcp251863_ts_cfg_t
MCP251863 Click Time Stamp Configuration Register.
Definition: mcp251863.h:1462
mcp251863_filt_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1210
mcp251863_ecc_error_address_get
err_t mcp251863_ecc_error_address_get(mcp251863_t *ctx, uint16_t *address)
Get ECC Error Address.
mcp251863_nbt_cfg_t::tseg2
uint32_t tseg2
Definition: mcp251863.h:1405
mcp251863_tx_que_stat_t::fifo_index
uint32_t fifo_index
Definition: mcp251863.h:1638
mcp251863_rx_msg_obj_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:974
mcp251863_osc_ctl_t::pll_enable
uint32_t pll_enable
Definition: mcp251863.h:1224
mcp251863_int_vec_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1519
mcp251863_ecc_ctl_t::ecc_en
uint32_t ecc_en
Definition: mcp251863.h:1297
mcp251863_ctl_t::restrict_re_tx_attempts
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1085
mcp251863_module_event_tx_code_get
err_t mcp251863_module_event_tx_code_get(mcp251863_t *ctx, uint8_t *tx_code)
Get TX Code.
mcp251863_bus_diag_flags_t::n_bit0_err
uint32_t n_bit0_err
Definition: mcp251863.h:1736
mcp251863_ctl_t::wake_up_filter_enable
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1080
mcp251863_int_t::word
uint32_t word
Definition: mcp251863.h:1578
mcp251863_data_t::tx_flags
uint8_t tx_flags
Definition: mcp251863.h:1852
mcp251863_fifo_user_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1378
mcp251863_dbt_cfg_t
MCP251863 Click Data Bit Time Configuration Register.
Definition: mcp251863.h:1420
mcp251863_config_t::rx_pay_load_size
uint8_t rx_pay_load_size
Definition: mcp251863.h:891
mcp251863_div_ctl_t::osc_disable
uint32_t osc_disable
Definition: mcp251863.h:1250
mcp251863_func_data_t::address
uint16_t address
Definition: mcp251863.h:1837
mcp251863_tef_status_get
err_t mcp251863_tef_status_get(mcp251863_t *ctx, uint8_t *status)
Transmit Event FIFO Status Get.
mcp251863_tef_ctl_t::freset
uint32_t freset
Definition: mcp251863.h:1145
mcp251863_transmit_request_set
err_t mcp251863_transmit_request_set(mcp251863_t *ctx, uint32_t tx_req)
Request transmissions using TXREQ register.
mcp251863_t::stby
digital_out_t stby
Definition: mcp251863.h:1878
mcp251863_fifo_user_cfg_t
MCP251863 Click FIFO User Address Register.
Definition: mcp251863.h:1375
mcp251863_time_stamp_enable
err_t mcp251863_time_stamp_enable(mcp251863_t *ctx)
Time Stamp Enable.
mcp251863_transmit_channel_event_enable
err_t mcp251863_transmit_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Enable.
mcp251863_mask_obj_id_t
MCP251863 Click CAN Mask Object ID.
Definition: mcp251863.h:1041
mcp251863_io_ctl_t
MCP251863 Click I/O Control Register.
Definition: mcp251863.h:1261
spi_specifics.h
This file contains SPI specific macros, functions, etc.
mcp251863_tef_ctl_t::word
uint32_t word
Definition: mcp251863.h:1150
mcp251863_can_cfg_t::esi_in_gateway_mode
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:871
mcp251863_tef_msg_obj_t::ctrl
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:1002
mcp251863_read_half_word
err_t mcp251863_read_half_word(mcp251863_t *ctx, uint16_t address, uint16_t *data_out)
SPI Read Half Word.
mcp251863_bit_time_configure_nominal_10_mhz
err_t mcp251863_bit_time_configure_nominal_10_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 10MHz system clock.
mcp251863_ecc_event_disable
err_t mcp251863_ecc_event_disable(mcp251863_t *ctx, uint8_t flags)
ECC Event Disable.
mcp251863_gpio_clock_output_configure
err_t mcp251863_gpio_clock_output_configure(mcp251863_t *ctx, int8_t mode)
Configure CLKO Pin.
mcp251863_rx_msg_obj_ctl_t::filter_hit
uint32_t filter_hit
Definition: mcp251863.h:973
mcp251863_tx_que_ctl_t
MCP251863 Click Transmit Queue Control Register.
Definition: mcp251863.h:1105
mcp251863_ecc_ctl_t::word
uint32_t word
Definition: mcp251863.h:1304
mcp251863_data_t::rec
uint8_t rec
Definition: mcp251863.h:1856
mcp251863_int_flags_stat_t::CERRIF
uint32_t CERRIF
Definition: mcp251863.h:1550
mcp251863_bus_diag_flags_t::txbo_err
uint32_t txbo_err
Definition: mcp251863.h:1743
mcp251863_io_ctl_t::lat0
uint32_t lat0
Definition: mcp251863.h:1270
mcp251863_ctl_t::tx_band_width_sharing
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1093
mcp251863_tef_msg_obj_t::time_stamp
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:1003
mcp251863_fifo_ctl_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1174
mcp251863_osc_ctl_t::word
uint32_t word
Definition: mcp251863.h:1238
MCP251863_OK
@ MCP251863_OK
Definition: mcp251863.h:1924
mcp251863_tx_que_ctl_t::uinc
uint32_t uinc
Definition: mcp251863.h:1114
mcp251863_transmit_band_width_sharing_set
err_t mcp251863_transmit_band_width_sharing_set(mcp251863_t *ctx, uint8_t tx_bws)
Set Transmit Bandwidth Sharing Delay.
mcp251863_int_en_t::rxie
uint32_t rxie
Definition: mcp251863.h:1482
mcp251863_tx_que_ctl_t::tx_empty_ie
uint32_t tx_empty_ie
Definition: mcp251863.h:1109
mcp251863_write_byte_safe
err_t mcp251863_write_byte_safe(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI SFR Write Byte Safe.
mcp251863_int_cfg_t
MCP251863 Click Interrupt Configuration.
Definition: mcp251863.h:1504
mcp251863_rx_msg_obj_ctl_t::brs
uint32_t brs
Definition: mcp251863.h:969
mcp251863_bus_diag0_t::word
uint32_t word
Definition: mcp251863.h:1796
mcp251863_ts_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1465
mcp251863_transmit_channel_update
err_t mcp251863_transmit_channel_update(mcp251863_t *ctx, uint8_t channel, bool flush)
Transmit FIFO Update.
mcp251863_rx_msg_obj_ctl_t::esi
uint32_t esi
Definition: mcp251863.h:971
mcp251863_config_t::ide
uint8_t ide
Definition: mcp251863.h:896
mcp251863_filter_object_configure
err_t mcp251863_filter_object_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_filt_obj_id_t *id)
Filter Object Configuration.
mcp251863_tef_t
MCP251863 Click Transmit Event FIFO Status Register.
Definition: mcp251863.h:1610
mcp251863_trec_t::rx_error_count
uint32_t rx_error_count
Definition: mcp251863.h:1590
mcp251863_int_flags_stat_t::TBCIF
uint32_t TBCIF
Definition: mcp251863.h:1540
mcp251863_t::spi
spi_master_t spi
Definition: mcp251863.h:1885
mcp251863_ecc_sta_t
MCP251863 Click ECC Status Register.
Definition: mcp251863.h:1704
mcp251863_time_stamp_disable
err_t mcp251863_time_stamp_disable(mcp251863_t *ctx)
Time Stamp Disable.
mcp251863_fifo_ctl_t::tx_attempt_ie
uint32_t tx_attempt_ie
Definition: mcp251863.h:1183
mcp251863_error_count_transmit_get
err_t mcp251863_error_count_transmit_get(mcp251863_t *ctx, uint8_t *tec)
Transmit Error Count Get.
mcp251863_dbt_cfg_t::tseg2
uint32_t tseg2
Definition: mcp251863.h:1424
mcp251863_osc_ctl_t
MCP251863 Click Oscillator Control Register.
Definition: mcp251863.h:1222
mcp251863_crc_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1689
mcp251863_filt_ctl_t
MCP251863 Click Filter Control Register.
Definition: mcp251863.h:1207
mcp251863_osc_ctl_t::osc_disable
uint32_t osc_disable
Definition: mcp251863.h:1226
mcp251863_write_word
err_t mcp251863_write_word(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI Write Word.
mcp251863_tx_que_ctl_t::tx_not_full_ie
uint32_t tx_not_full_ie
Definition: mcp251863.h:1107
mcp251863_osc_ctl_t::sclk_divide
uint32_t sclk_divide
Definition: mcp251863.h:1228
mcp251863_osc_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1227
mcp251863_tx_que_cfg_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1351
mcp251863_tef_ctl_t::tefneie
uint32_t tefneie
Definition: mcp251863.h:1136
mcp251863_tx_msg_obj_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:940
mcp251863_bus_diag1_t::n_form_error
uint32_t n_form_error
Definition: mcp251863.h:1812
mcp251863_bus_diag_flags_t::esi
uint32_t esi
Definition: mcp251863.h:1750
mcp251863_trec_t::rx_error_state_warning
uint32_t rx_error_state_warning
Definition: mcp251863.h:1593
mcp251863_data_t::rx_config
mcp251863_rx_fifo_cfg_t rx_config
Definition: mcp251863.h:1862
mcp251863_tx_que_ctl_t::word
uint32_t word
Definition: mcp251863.h:1124
mcp251863_dbt_cfg_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1427
mcp251863_time_stamp_set
err_t mcp251863_time_stamp_set(mcp251863_t *ctx, uint32_t ts)
Time Stamp Set.
mcp251863_crc_t::word
uint32_t word
Definition: mcp251863.h:1694
mcp251863_ts_cfg_t::word
uint32_t word
Definition: mcp251863.h:1470
mcp251863_bus_diag1_t::d_bit1_error
uint32_t d_bit1_error
Definition: mcp251863.h:1818
mcp251863_msg_time_stamp_t
uint32_t mcp251863_msg_time_stamp_t
MCP251863 Click CAN Message Time Stamp.
Definition: mcp251863.h:912
mcp251863_transmit_channel_index_get
err_t mcp251863_transmit_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Transmit FIFO Index Get.
mcp251863_data_t::m_obj
mcp251863_mask_obj_t m_obj
Definition: mcp251863.h:1866
mcp251863_transmit_event_get
err_t mcp251863_transmit_event_get(mcp251863_t *ctx, uint32_t *txif)
Get pending interrupts of all transmit FIFOs.
mcp251863_ctl_t::d_net_filter_count
uint32_t d_net_filter_count
Definition: mcp251863.h:1076
T_MCP251863_cfg_t::restrict_re_tx_attempts
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:1321
mcp251863_tdc_cfg_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1443
mcp251863_data_bytes_to_dlc
uint8_t mcp251863_data_bytes_to_dlc(uint8_t num)
Data bytes to DLC conversion.
mcp251863_configure_object_reset
void mcp251863_configure_object_reset(mcp251863_can_cfg_t *config)
Reset Configure object to reset values.
mcp251863_data_t::bus_diagnostics
mcp251863_bus_diag_t bus_diagnostics
Definition: mcp251863.h:1867
mcp251863_generic_write
err_t mcp251863_generic_write(mcp251863_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len)
MCP251863 data writing function.
mcp251863_reg_t
Definition: mcp251863.h:1063
mcp251863_osc_ctl_t::pll_ready
uint32_t pll_ready
Definition: mcp251863.h:1231
mcp251863_fifo_stat_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1659
mcp251863_write_byte_array
err_t mcp251863_write_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_in, uint16_t n_bytes)
SPI Write Byte Array.
mcp251863_bit_time_configure_data_20_mhz
err_t mcp251863_bit_time_configure_data_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.
mcp251863_filt_obj_id_t::sid
uint32_t sid
Definition: mcp251863.h:1016
mcp251863_fifo_ctl_t::tx_not_full_ie
uint32_t tx_not_full_ie
Definition: mcp251863.h:1179
mcp251863_osc_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1232
mcp251863_io_ctl_t::clear_auto_sleep_on_match
uint32_t clear_auto_sleep_on_match
Definition: mcp251863.h:1266
mcp251863_t::func_data
mcp251863_func_data_t func_data
Definition: mcp251863.h:1890
mcp251863_bus_diag_flags_t::n_ack_err
uint32_t n_ack_err
Definition: mcp251863.h:1738
mcp251863_bus_diag1_t::n_crc_error
uint32_t n_crc_error
Definition: mcp251863.h:1814
mcp251863_fifo_ctl_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1192
mcp251863_ctl_t::iso_crc_enable
uint32_t iso_crc_enable
Definition: mcp251863.h:1077
mcp251863_bus_diag0_t::n_tx_error_count
uint32_t n_tx_error_count
Definition: mcp251863.h:1792
mcp251863_int_flag_t
MCP251863 Click Interrupt Flag Register.
Definition: mcp251863.h:1561
mcp251863_func_data_t::rxd
uint8_t * rxd
Definition: mcp251863.h:1838
mcp251863_tx_msg_obj_ctl_t::esi
uint32_t esi
Definition: mcp251863.h:938
mcp251863_bus_diag_flags_t::n_form_err
uint32_t n_form_err
Definition: mcp251863.h:1739
mcp251863_fifo_ctl_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1191
mcp251863_int_flags_stat_t::IVMIF
uint32_t IVMIF
Definition: mcp251863.h:1552
mcp251863_tx_msg_obj_t::time_stamp
mcp251863_msg_time_stamp_t time_stamp
Definition: mcp251863.h:953
mcp251863_bus_diag_flags_t::dlc_mismatch
uint32_t dlc_mismatch
Definition: mcp251863.h:1751
mcp251863_tef_cfg_t::time_stamp_enable
uint32_t time_stamp_enable
Definition: mcp251863.h:1391
mcp251863_mask_obj_t::bf
mcp251863_mask_obj_id_t bf
Definition: mcp251863.h:1056
mcp251863_msg_obj_id_t::sid11
uint32_t sid11
Definition: mcp251863.h:922
mcp251863_mask_obj_id_t::msid
uint32_t msid
Definition: mcp251863.h:1042
mcp251863_bus_diag_flags_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1742
mcp251863_mask_obj_id_t::msid11
uint32_t msid11
Definition: mcp251863.h:1044
mcp251863_tx_que_ctl_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1122
MCP251863_ERROR
@ MCP251863_ERROR
Definition: mcp251863.h:1925
mcp251863_ctl_t::request_op_mode
uint32_t request_op_mode
Definition: mcp251863.h:1091
mcp251863_dbt_cfg_t::tseg1
uint32_t tseg1
Definition: mcp251863.h:1426
mcp251863_transmit_channel_event_disable
err_t mcp251863_transmit_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Transmit FIFO Event Disable.
mcp251863_fifo_ctl_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1175
mcp251863_fifo_ctl_t::uinc
uint32_t uinc
Definition: mcp251863.h:1170
mcp251863_tx_que_cfg_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1353
mcp251863_int_vec_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1523
mcp251863_bus_diag_flags_t::d_bit1_err
uint32_t d_bit1_err
Definition: mcp251863.h:1745
mcp251863_tdc_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1445
mcp251863_receive_channel_index_get
int8_t mcp251863_receive_channel_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *idx)
Receive FIFO Index Get.
mcp251863_int_en_t::txie
uint32_t txie
Definition: mcp251863.h:1481
mcp251863_io_ctl_t::lat1
uint32_t lat1
Definition: mcp251863.h:1271
mcp251863_osc_ctl_t::osc_ready
uint32_t osc_ready
Definition: mcp251863.h:1233
mcp251863_int_flag_t::word
uint16_t word
Definition: mcp251863.h:1563
mcp251863_ctl_t::bit_rate_switch_disable
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1083
mcp251863_filt_ctl_t::buffer_pointer
uint32_t buffer_pointer
Definition: mcp251863.h:1209
mcp251863_bus_diag_flags_t::d_bit0_err
uint32_t d_bit0_err
Definition: mcp251863.h:1744
mcp251863_receive_channel_reset
err_t mcp251863_receive_channel_reset(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Reset.
mcp251863_tx_fifo_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1339
mcp251863_configure
err_t mcp251863_configure(mcp251863_t *ctx, mcp251863_can_cfg_t *config)
CAN Control register configuration.
mcp251863_int_en_t::tbcie
uint32_t tbcie
Definition: mcp251863.h:1483
mcp251863_reset
err_t mcp251863_reset(mcp251863_t *ctx)
Reset function.
mcp251863_int_flags_stat_t::SPICRCIF
uint32_t SPICRCIF
Definition: mcp251863.h:1546
mcp251863_div_ctl_t::pll_enable
uint32_t pll_enable
Definition: mcp251863.h:1249
mcp251863_filt_obj_id_t::exide
uint32_t exide
Definition: mcp251863.h:1019
mcp251863_tef_event_overflow_clear
err_t mcp251863_tef_event_overflow_clear(mcp251863_t *ctx)
Transmit Event FIFO Event Clear.
mcp251863_ecc_sta_t::word
uint32_t word
Definition: mcp251863.h:1713
mcp251863_read_byte_array_with_crc
err_t mcp251863_read_byte_array_with_crc(mcp251863_t *ctx, bool from_ram, bool *crc_is_correct)
SPI Read Byte Array with CRC.
mcp251863_bus_diagnostics_get
err_t mcp251863_bus_diagnostics_get(mcp251863_t *ctx, mcp251863_bus_diag_t *bus_diag)
Get Bus Diagnostic Registers: all data_ at once, since we want to keep them in synch.
mcp251863_cfg_t::cs
pin_name_t cs
Definition: mcp251863.h:1904
mcp251863_ts_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1468
mcp251863_fifo_user_cfg_t::word
uint32_t word
Definition: mcp251863.h:1380
mcp251863_nbt_cfg_t::tseg1
uint32_t tseg1
Definition: mcp251863.h:1407
mcp251863_config_t::iso_crc_enable
uint8_t iso_crc_enable
Definition: mcp251863.h:885
mcp251863_io_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1269
mcp251863_tef_t::tef_not_empty_if
uint32_t tef_not_empty_if
Definition: mcp251863.h:1612
mcp251863_int_vec_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1525
mcp251863_bus_diag1_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1824
mcp251863_tef_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1144
mcp251863_transmit_message
err_t mcp251863_transmit_message(mcp251863_t *ctx, uint8_t *data_in, uint16_t data_len)
Message Transmit function.
mcp251863_tx_fifo_cfg_t::rtr_enable
uint32_t rtr_enable
Definition: mcp251863.h:1336
mcp251863_tef_configure
err_t mcp251863_tef_configure(mcp251863_t *ctx, mcp251863_tef_cfg_t *config)
Configure Transmit Event FIFO.
mcp251863_int_en_t::spicrcie
uint32_t spicrcie
Definition: mcp251863.h:1489
mcp251863_fifo_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1166
mcp251863_filt_ctl_t::enable
uint32_t enable
Definition: mcp251863.h:1211
mcp251863_filt_obj_id_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1020
mcp251863_tef_msg_obj_t
MCP251863 Click CAN TEF Message Object.
Definition: mcp251863.h:999
mcp251863_filter_mask_configure
err_t mcp251863_filter_mask_configure(mcp251863_t *ctx, uint8_t filter, mcp251863_mask_obj_id_t *mask)
Filter Mask Configuration.
mcp251863_tdc_cfg_t::tdc_offset
uint32_t tdc_offset
Definition: mcp251863.h:1444
mcp251863_int_en_t::eccie
uint32_t eccie
Definition: mcp251863.h:1488
mcp251863_tx_que_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1110
mcp251863_config_t::remote_frame_req
uint8_t remote_frame_req
Definition: mcp251863.h:897
mcp251863_osc_sta_t::osc_ready
uint32_t osc_ready
Definition: mcp251863.h:1725
mcp251863_bus_diag1_t::txbo_error
uint32_t txbo_error
Definition: mcp251863.h:1816
mcp251863_div_ctl_t::sclk_divide
uint32_t sclk_divide
Definition: mcp251863.h:1251
mcp251863_fifo_stat_t::tx_attempt_if
uint32_t tx_attempt_if
Definition: mcp251863.h:1667
mcp251863_osc_ctl_t::clk_out_divide
uint32_t clk_out_divide
Definition: mcp251863.h:1229
mcp251863_reg_t::word
uint32_t word
Definition: mcp251863.h:1065
mcp251863_gpio_mode_configure
err_t mcp251863_gpio_mode_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Mode.
mcp251863_fifo_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1173
mcp251863_io_ctl_t::pin_mode1
uint32_t pin_mode1
Definition: mcp251863.h:1278
mcp251863_t::int_pin
digital_in_t int_pin
Definition: mcp251863.h:1882
mcp251863_msg_obj_id_t::eid
uint32_t eid
Definition: mcp251863.h:921
mcp251863_gpio_pin_read
err_t mcp251863_gpio_pin_read(mcp251863_t *ctx, uint8_t pos, uint8_t *state)
Input Pin Read.
mcp251863_can_cfg_t::wake_up_filter_time
uint32_t wake_up_filter_time
Definition: mcp251863.h:868
mcp251863_filt_obj_id_t::eid
uint32_t eid
Definition: mcp251863.h:1017
mcp251863_tx_que_stat_t
MCP251863 Click Transmit Queue Status Register.
Definition: mcp251863.h:1628
mcp251863_transmit_queue_configure_object_reset
void mcp251863_transmit_queue_configure_object_reset(mcp251863_tx_que_cfg_t *config)
Reset Transmit Queue Configure object to reset values.
mcp251863_msg_obj_id_t
MCP251863 Click CAN Message Object ID.
Definition: mcp251863.h:919
mcp251863_tdc_cfg_t::sid11_enable
uint32_t sid11_enable
Definition: mcp251863.h:1448
mcp251863_io_ctl_t::gpio0
uint32_t gpio0
Definition: mcp251863.h:1274
mcp251863_dlc_to_data_bytes
uint32_t mcp251863_dlc_to_data_bytes(uint8_t dlc)
DLC to number of actual data_bytes conversion.
T_MCP251863_cfg_t::esi_in_gateway_mode
uint32_t esi_in_gateway_mode
Definition: mcp251863.h:1322
mcp251863_fifo_stat_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1657
mcp251863_msg_obj_id_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:923
mcp251863_rx_fifo_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1364
mcp251863_can_cfg_t
MCP251863 Click CAN Configure.
Definition: mcp251863.h:863
mcp251863_receive_channel_event_enable
err_t mcp251863_receive_channel_event_enable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Enable.
mcp251863_can_cfg_t::system_error_to_listen_only
uint32_t system_error_to_listen_only
Definition: mcp251863.h:872
mcp251863_receive_message_get
err_t mcp251863_receive_message_get(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_msg_obj_t *rx_obj)
Get Received Message.
mcp251863_io_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1276
mcp251863_tx_que_ctl_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1121
mcp251863_tef_reset
err_t mcp251863_tef_reset(mcp251863_t *ctx)
Transmit Event FIFO Reset.
mcp251863_transmit_abort_all
err_t mcp251863_transmit_abort_all(mcp251863_t *ctx)
Abort All transmissions.
mcp251863_int_vec_t::icode
uint32_t icode
Definition: mcp251863.h:1518
mcp251863_time_stamp_get
err_t mcp251863_time_stamp_get(mcp251863_t *ctx, uint32_t *time_stamp)
Time Stamp Get.
mcp251863_data_t::config
mcp251863_can_cfg_t config
Definition: mcp251863.h:1860
mcp251863_filt_obj_t::word
uint32_t word
Definition: mcp251863.h:1031
T_MCP251863_cfg_t::wake_up_filter_enable
uint32_t wake_up_filter_enable
Definition: mcp251863.h:1318
mcp251863_int_flags_stat_t
MCP251863 Click Interrupt Flags.
Definition: mcp251863.h:1537
mcp251863_bus_diag_flags_t::d_form_err
uint32_t d_form_err
Definition: mcp251863.h:1747
mcp251863_int_en_t
MCP251863 Click Interrupt Enables.
Definition: mcp251863.h:1480
mcp251863_tx_msg_obj_ctl_t
MCP251863 Click CAN TX Message Object Control.
Definition: mcp251863.h:932
mcp251863_trec_t::word
uint32_t word
Definition: mcp251863.h:1600
mcp251863_read_word_array
err_t mcp251863_read_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_out, uint16_t n_words)
SPI Read Word Array.
mcp251863_osc_sta_t
MCP251863 Click Oscillator Status.
Definition: mcp251863.h:1723
mcp251863_data_t::rx_obj
mcp251863_rx_msg_obj_t rx_obj
Definition: mcp251863.h:1864
T_MCP251863_cfg_t::txq_enable
uint32_t txq_enable
Definition: mcp251863.h:1325
mcp251863_tx_que_cfg_t
MCP251863 Click CAN Transmit Queue Configure.
Definition: mcp251863.h:1349
mcp251863_int_en_t::tefie
uint32_t tefie
Definition: mcp251863.h:1485
mcp251863_data_t::tx_obj
mcp251863_tx_msg_obj_t tx_obj
Definition: mcp251863.h:1863
mcp251863_receive_channel_configure_object_reset
void mcp251863_receive_channel_configure_object_reset(mcp251863_rx_fifo_cfg_t *config)
Reset Receive Channel Configure object to reset value.
mcp251863_tx_que_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1112
mcp251863_tx_msg_obj_ctl_t::brs
uint32_t brs
Definition: mcp251863.h:936
mcp251863_transmit_channel_status_get
err_t mcp251863_transmit_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint16_t *status)
Transmit Channel Status Get.
mcp251863_int_flags_stat_t::RXIF
uint32_t RXIF
Definition: mcp251863.h:1539
mcp251863_fifo_index_get
err_t mcp251863_fifo_index_get(mcp251863_t *ctx, uint8_t channel, uint8_t *data_out)
FIFO Index Get.
mcp251863_cfg_t::stby
pin_name_t stby
Definition: mcp251863.h:1907
mcp251863_int_vec_t::filter_hit
uint32_t filter_hit
Definition: mcp251863.h:1520
mcp251863_config_t
MCP251863 Click CAN Message Configuration.
Definition: mcp251863.h:884
mcp251863_tx_msg_obj_ctl_t::ide
uint32_t ide
Definition: mcp251863.h:934
mcp251863_transmit_channel_configure_object_reset
void mcp251863_transmit_channel_configure_object_reset(mcp251863_tx_fifo_cfg_t *config)
Reset Transmit Channel Configure object to reset values.
mcp251863_func_data_t::txd_num_bytes
uint32_t txd_num_bytes
Definition: mcp251863.h:1841
mcp251863_gpio_direction_configure
err_t mcp251863_gpio_direction_configure(mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
Initialize GPIO Direction.
mcp251863_tef_ctl_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1147
mcp251863_cfg_setup
void mcp251863_cfg_setup(mcp251863_cfg_t *cfg)
MCP251863 configuration object setup function.
mcp251863_filter_enable
err_t mcp251863_filter_enable(mcp251863_t *ctx, uint8_t filter)
Filter Enable.
mcp251863_ecc_parity_set
err_t mcp251863_ecc_parity_set(mcp251863_t *ctx, uint8_t parity)
Set ECC Parity.
mcp251863_can_cfg_t::iso_crc_enable
uint32_t iso_crc_enable
Definition: mcp251863.h:865
mcp251863_mask_obj_id_t::mide
uint32_t mide
Definition: mcp251863.h:1045
mcp251863_trec_t::tx_error_count
uint32_t tx_error_count
Definition: mcp251863.h:1591
mcp251863_int_en_t::rxovie
uint32_t rxovie
Definition: mcp251863.h:1491
mcp251863_tx_que_stat_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1631
mcp251863_default_cfg
err_t mcp251863_default_cfg(mcp251863_t *ctx)
MCP251863 default configuration function.
mcp251863_tdc_cfg_t
MCP251863 Click Transmitter Delay Compensation Register.
Definition: mcp251863.h:1440
mcp251863_filt_obj_id_t
MCP251863 Click CAN Filter Object ID.
Definition: mcp251863.h:1015
mcp251863_tx_que_stat_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1639
mcp251863_int_en_t::wakie
uint32_t wakie
Definition: mcp251863.h:1494
mcp251863_config_t::store_in_tef
uint8_t store_in_tef
Definition: mcp251863.h:886
mcp251863_int_flags_stat_t::ECCIF
uint32_t ECCIF
Definition: mcp251863.h:1545
mcp251863_tef_t::tef_ov_if
uint32_t tef_ov_if
Definition: mcp251863.h:1615
mcp251863_can_cfg_t::txq_enable
uint32_t txq_enable
Definition: mcp251863.h:874
mcp251863_dbt_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1425
mcp251863_tef_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1616
mcp251863_bus_diag1_t::d_crc_error
uint32_t d_crc_error
Definition: mcp251863.h:1822
mcp251863_ecc_sta_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1711
mcp251863_fifo_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1171
mcp251863_receive_message
err_t mcp251863_receive_message(mcp251863_t *ctx, uint8_t *data_out, uint16_t *data_len)
Message Receive function.
mcp251863_int_t::if_stat
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1575
mcp251863_fifo_stat_t::tx_half_full_if
uint32_t tx_half_full_if
Definition: mcp251863.h:1664
mcp251863_config_t::rx_fifo_size
uint8_t rx_fifo_size
Definition: mcp251863.h:890
mcp251863_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1082
mcp251863_nbt_cfg_t
MCP251863 Click Nominal Bit Time Configuration Register.
Definition: mcp251863.h:1401
mcp251863_fifo_ctl_t::rx_full_ie
uint32_t rx_full_ie
Definition: mcp251863.h:1164
mcp251863_operation_mode_get
err_t mcp251863_operation_mode_get(mcp251863_t *ctx)
Get Operation Mode.
T_MCP251863_cfg_t
MCP251863 Click CAN Configure.
Definition: mcp251863.h:1314
mcp251863_bus_error_count_t::n_tec
uint8_t n_tec
Definition: mcp251863.h:1762
mcp251863_return_value_t
mcp251863_return_value_t
MCP251863 Click return value data.
Definition: mcp251863.h:1923
mcp251863_tx_que_stat_t::word
uint32_t word
Definition: mcp251863.h:1641
mcp251863_io_ctl_t::hvdetsel
uint32_t hvdetsel
Definition: mcp251863.h:1273
mcp251863_config_t::extended_id
uint32_t extended_id
Definition: mcp251863.h:893
mcp251863_tx_que_stat_t::tx_attempt_if
uint32_t tx_attempt_if
Definition: mcp251863.h:1634
mcp251863_bus_diag_flags_t::n_bit1_err
uint32_t n_bit1_err
Definition: mcp251863.h:1737
mcp251863_tef_msg_obj_t::id
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:1001
mcp251863_transmit_channel_configure
err_t mcp251863_transmit_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_fifo_cfg_t *config)
Configure Transmit FIFO.
mcp251863_tx_que_ctl_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1117
mcp251863_nbt_cfg_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1406
mcp251863_int_t
MCP251863 Click Interrupt Register.
Definition: mcp251863.h:1573
mcp251863_io_ctl_t::int_pin_open_drain
uint32_t int_pin_open_drain
Definition: mcp251863.h:1282
mcp251863_ram_init
err_t mcp251863_ram_init(mcp251863_t *ctx, uint8_t rx_data)
Initialize RAM.
mcp251863_ecc_sta_t::secif
uint32_t secif
Definition: mcp251863.h:1707
mcp251863_trec_t::tx_error_state_bus_off
uint32_t tx_error_state_bus_off
Definition: mcp251863.h:1597
mcp251863_transmit_channel_reset
int8_t mcp251863_transmit_channel_reset(mcp251863_t *ctx, uint8_t channel)
Transmit FIFO Reset.
mcp251863_ts_cfg_t::tbc_prescaler
uint32_t tbc_prescaler
Definition: mcp251863.h:1464
mcp251863_int_vec_t::tx_code
uint32_t tx_code
Definition: mcp251863.h:1522
mcp251863_id_t
uint8_t mcp251863_id_t
MCP251863 Click Module ID.
Definition: mcp251863.h:906
mcp251863_ecc_sta_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1706
mcp251863_fifo_stat_t::rx_not_empty_if
uint32_t rx_not_empty_if
Definition: mcp251863.h:1653
mcp251863_int_vec_t::rx_code
uint32_t rx_code
Definition: mcp251863.h:1524
mcp251863_crc_event_get
err_t mcp251863_crc_event_get(mcp251863_t *ctx, uint8_t *flags)
CRC Event Get.
mcp251863_func_data_t::txd
uint8_t * txd
Definition: mcp251863.h:1840
mcp251863_crc_event_clear
err_t mcp251863_crc_event_clear(mcp251863_t *ctx, uint8_t flags)
CRC Event Clear.
mcp251863_data_t::f_obj
mcp251863_filt_obj_t f_obj
Definition: mcp251863.h:1865
mcp251863_t::chip_select
pin_name_t chip_select
Definition: mcp251863.h:1887
mcp251863_tdc_cfg_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1447
mcp251863_int_vec_t::word
uint32_t word
Definition: mcp251863.h:1527
mcp251863_ctl_t::word
uint32_t word
Definition: mcp251863.h:1095
mcp251863_cfg_t::int_pin
pin_name_t int_pin
Definition: mcp251863.h:1909
mcp251863_tx_que_stat_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1633
mcp251863_fifo_stat_t::tx_error
uint32_t tx_error
Definition: mcp251863.h:1668
mcp251863_tef_t::tef_half_full_if
uint32_t tef_half_full_if
Definition: mcp251863.h:1613
mcp251863_bus_diag1_t::d_stuff_error
uint32_t d_stuff_error
Definition: mcp251863.h:1821
mcp251863_int_flags_stat_t::WAKIF
uint32_t WAKIF
Definition: mcp251863.h:1551
mcp251863_write_word_array
err_t mcp251863_write_word_array(mcp251863_t *ctx, uint16_t address, uint32_t *data_in, uint16_t n_words)
SPI Write Word Array.
mcp251863_config_t::seq
uint8_t seq
Definition: mcp251863.h:898
mcp251863_time_stamp_mode_configure
err_t mcp251863_time_stamp_mode_configure(mcp251863_t *ctx, uint8_t mode)
Time Stamp Mode Configure.
mcp251863_tef_configure_object_reset
void mcp251863_tef_configure_object_reset(mcp251863_tef_cfg_t *config)
Reset TefConfigure object to reset value.
mcp251863_func_data_t
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1836
mcp251863_bus_diag1_t::error_free_msg_count
uint32_t error_free_msg_count
Definition: mcp251863.h:1808
mcp251863_fifo_stat_t
MCP251863 Click FIFO Status Register.
Definition: mcp251863.h:1651
mcp251863_filt_obj_id_t::sid11
uint32_t sid11
Definition: mcp251863.h:1018
mcp251863_tdc_cfg_t::edge_filter_enable
uint32_t edge_filter_enable
Definition: mcp251863.h:1449
mcp251863_tx_que_ctl_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1118
mcp251863_crc_event_disable
err_t mcp251863_crc_event_disable(mcp251863_t *ctx, uint8_t flags)
CRC Event Disnable.
mcp251863_data_t::rx_flags
uint8_t rx_flags
Definition: mcp251863.h:1853
mcp251863_osc_ctl_t::sclk_ready
uint32_t sclk_ready
Definition: mcp251863.h:1235
mcp251863_fifo_ctl_t::rx_time_stamp_enable
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1167
mcp251863_int_flags_stat_t::SERRIF
uint32_t SERRIF
Definition: mcp251863.h:1549
mcp251863_bus_diag1_t::word
uint32_t word
Definition: mcp251863.h:1826
mcp251863_transmit_event_attempt_get
err_t mcp251863_transmit_event_attempt_get(mcp251863_t *ctx, uint32_t *txatif)
Get pending TXATIF of all transmit FIFOs.
mcp251863_fifo_stat_t::tx_aborted
uint32_t tx_aborted
Definition: mcp251863.h:1670
mcp251863_ctl_t::txq_enable
uint32_t txq_enable
Definition: mcp251863.h:1089
mcp251863_ecc_ctl_t::parity
uint32_t parity
Definition: mcp251863.h:1301
mcp251863_int_vec_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1521
mcp251863_data_t
MCP251863 Click CAN message configuration.
Definition: mcp251863.h:1850
mcp251863_tx_que_cfg_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1350
mcp251863_crc_t::crcerrif
uint32_t crcerrif
Definition: mcp251863.h:1687
mcp251863_bus_diagnostics_clear
err_t mcp251863_bus_diagnostics_clear(mcp251863_t *ctx)
Clear Bus Diagnostic Registers.
mcp251863_rx_msg_obj_ctl_t::rtr
uint32_t rtr
Definition: mcp251863.h:968
T_MCP251863_cfg_t::store_in_tef
uint32_t store_in_tef
Definition: mcp251863.h:1324
mcp251863_ctl_t::store_in_tef
uint32_t store_in_tef
Definition: mcp251863.h:1088
mcp251863_tef_ctl_t::time_stamp_enable
uint32_t time_stamp_enable
Definition: mcp251863.h:1141
mcp251863_fifo_ctl_t::rx_not_empty_ie
uint32_t rx_not_empty_ie
Definition: mcp251863.h:1162
mcp251863_bit_time_configure_nominal_40_mhz
err_t mcp251863_bit_time_configure_nominal_40_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 40MHz system clock.
mcp251863_config_t::switch_bit_rate
uint8_t switch_bit_rate
Definition: mcp251863.h:895
mcp251863_osc_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1225
mcp251863_ctl_t::op_mode
uint32_t op_mode
Definition: mcp251863.h:1090
mcp251863_ctl_t::abort_all_tx
uint32_t abort_all_tx
Definition: mcp251863.h:1092
mcp251863_io_ctl_t::tris1
uint32_t tris1
Definition: mcp251863.h:1264
mcp251863_tdc_cfg_t::tdc_value
uint32_t tdc_value
Definition: mcp251863.h:1442
mcp251863_operation_mode_select
err_t mcp251863_operation_mode_select(mcp251863_t *ctx, uint8_t op_mode)
Select Operation Mode.
mcp251863_tef_cfg_t
MCP251863 Click CAN Transmit Event FIFO Configure.
Definition: mcp251863.h:1390
mcp251863_receive_channel_event_get
err_t mcp251863_receive_channel_event_get(mcp251863_t *ctx, uint8_t channel, uint8_t *flags)
Receive FIFO Event Get.
mcp251863_rx_msg_obj_ctl_t::dlc
uint32_t dlc
Definition: mcp251863.h:966
mcp251863_fifo_stat_t::tx_empty_if
uint32_t tx_empty_if
Definition: mcp251863.h:1665
mcp251863_data_t::tec
uint8_t tec
Definition: mcp251863.h:1855
mcp251863_tef_t::tef_full_if
uint32_t tef_full_if
Definition: mcp251863.h:1614
mcp251863_gpio_standby_control_disable
err_t mcp251863_gpio_standby_control_disable(mcp251863_t *ctx)
Disable Transceiver Standby Control.
mcp251863_int_en_t::cerrie
uint32_t cerrie
Definition: mcp251863.h:1493
mcp251863_dbt_cfg_t::word
uint32_t word
Definition: mcp251863.h:1430
mcp251863_int_t::ie
mcp251863_int_en_t ie
Definition: mcp251863.h:1576
mcp251863_osc_ctl_t::unimplemented6
uint32_t unimplemented6
Definition: mcp251863.h:1236
mcp251863_tx_que_ctl_t::tx_enable
uint32_t tx_enable
Definition: mcp251863.h:1113
mcp251863_io_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1279
mcp251863_tef_event_get
err_t mcp251863_tef_event_get(mcp251863_t *ctx, uint8_t *flags)
Transmit Event FIFO Event Get.
mcp251863_tx_que_stat_t::tx_empty_if
uint32_t tx_empty_if
Definition: mcp251863.h:1632
mcp251863_int_flags_stat_t::TEFIF
uint32_t TEFIF
Definition: mcp251863.h:1542
mcp251863_bus_diag0_t::n_rx_error_count
uint32_t n_rx_error_count
Definition: mcp251863.h:1791
mcp251863_tef_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1140
mcp251863_time_stamp_prescaler_set
err_t mcp251863_time_stamp_prescaler_set(mcp251863_t *ctx, uint16_t time_stamp)
Time Stamp Prescaler Set.
mcp251863_tdc_cfg_t::word
uint32_t word
Definition: mcp251863.h:1452
mcp251863_module_event_get
err_t mcp251863_module_event_get(mcp251863_t *ctx, uint16_t *flags)
Module Event Get.
mcp251863_rx_fifo_cfg_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1365
mcp251863_cfg_t::mosi
pin_name_t mosi
Definition: mcp251863.h:1902
mcp251863_tef_event_enable
err_t mcp251863_tef_event_enable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Enable.
mcp251863_data_t::selected_bit_time
uint8_t selected_bit_time
Definition: mcp251863.h:1851
mcp251863_mask_obj_id_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1046
mcp251863_bus_diag_flags_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1746
mcp251863_tdc_cfg_t::tdc_mode
uint32_t tdc_mode
Definition: mcp251863.h:1446
mcp251863_tef_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1392
mcp251863_fifo_ctl_t::unimplemented2
uint32_t unimplemented2
Definition: mcp251863.h:1168
mcp251863_io_ctl_t::gpio1
uint32_t gpio1
Definition: mcp251863.h:1275
mcp251863_int_flags_stat_t::TXATIF
uint32_t TXATIF
Definition: mcp251863.h:1547
mcp251863_fifo_stat_t::fifo_index
uint32_t fifo_index
Definition: mcp251863.h:1658
mcp251863_int_flags_stat_t::TXIF
uint32_t TXIF
Definition: mcp251863.h:1538
mcp251863_fifo_ctl_t::word
uint32_t word
Definition: mcp251863.h:1197
mcp251863_generic_read
err_t mcp251863_generic_read(mcp251863_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len)
MCP251863 data reading function.
mcp251863_ctl_t
MCP251863 Click CAN Control Register.
Definition: mcp251863.h:1074
mcp251863_ts_cfg_t::time_stamp_eof
uint32_t time_stamp_eof
Definition: mcp251863.h:1467
mcp251863_fifo_ctl_t::tx_request
uint32_t tx_request
Definition: mcp251863.h:1188
mcp251863_msg_obj_id_t::sid
uint32_t sid
Definition: mcp251863.h:920
mcp251863_io_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1265
mcp251863_tx_que_stat_t::tx_lost_arbitration
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1636
mcp251863_ecc_event_get
err_t mcp251863_ecc_event_get(mcp251863_t *ctx, uint8_t *flags)
ECC Event Get.
mcp251863_io_ctl_t::tris0
uint32_t tris0
Definition: mcp251863.h:1263
mcp251863_fifo_stat_t::word
uint32_t word
Definition: mcp251863.h:1674
mcp251863_fifo_stat_t::tx_lost_arbitration
uint32_t tx_lost_arbitration
Definition: mcp251863.h:1669
mcp251863_filt_ctl_t::byte
uint8_t byte
Definition: mcp251863.h:1213
mcp251863_filter_disable
err_t mcp251863_filter_disable(mcp251863_t *ctx, uint8_t filter)
Filter Disable.
mcp251863_bus_error_count_t::d_tec
uint8_t d_tec
Definition: mcp251863.h:1764
mcp251863_tx_que_stat_t::tx_not_full_if
uint32_t tx_not_full_if
Definition: mcp251863.h:1630
mcp251863_int_en_t::modie
uint32_t modie
Definition: mcp251863.h:1484
mcp251863_bus_error_count_t::d_rec
uint8_t d_rec
Definition: mcp251863.h:1763
mcp251863_can_cfg_t::d_net_filter_count
uint32_t d_net_filter_count
Definition: mcp251863.h:864
mcp251863_tx_msg_obj_ctl_t::rtr
uint32_t rtr
Definition: mcp251863.h:935
mcp251863_receive_channel_event_disable
err_t mcp251863_receive_channel_event_disable(mcp251863_t *ctx, uint8_t channel, uint8_t flags)
Receive FIFO Event Disable.
mcp251863_bus_diag_flags_t::n_crc_err
uint32_t n_crc_err
Definition: mcp251863.h:1741
mcp251863_int_flags_stat_t::MODIF
uint32_t MODIF
Definition: mcp251863.h:1541
T_MCP251863_cfg_t::d_net_filter_count
uint32_t d_net_filter_count
Definition: mcp251863.h:1315
mcp251863_rx_msg_obj_ctl_t
MCP251863 Click CAN RX Message Object Control.
Definition: mcp251863.h:965
mcp251863_int_cfg_t::word
uint16_t word
Definition: mcp251863.h:1506
mcp251863_io_ctl_t::xcr_stby_enable
uint32_t xcr_stby_enable
Definition: mcp251863.h:1268
mcp251863_ctl_t::unimplemented3
uint32_t unimplemented3
Definition: mcp251863.h:1084
mcp251863_module_event_disable
err_t mcp251863_module_event_disable(mcp251863_t *ctx, uint16_t flags)
Module Event Disable.
mcp251863_tx_que_stat_t::tx_aborted
uint32_t tx_aborted
Definition: mcp251863.h:1637
mcp251863_receive_event_get
err_t mcp251863_receive_event_get(mcp251863_t *ctx, uint32_t *rxif)
Get pending interrupts of all receive FIFOs.
T_MCP251863_cfg_t::wake_up_filter_time
uint32_t wake_up_filter_time
Definition: mcp251863.h:1319
mcp251863_rx_msg_obj_t::id
mcp251863_msg_obj_id_t id
Definition: mcp251863.h:985
mcp251863_fifo_user_cfg_t::user_address
uint32_t user_address
Definition: mcp251863.h:1377
mcp251863_module_event_rx_code_get
err_t mcp251863_module_event_rx_code_get(mcp251863_t *ctx, uint8_t *rx_code)
Get RX Code.
mcp251863_tx_msg_obj_ctl_t::dlc
uint32_t dlc
Definition: mcp251863.h:933
mcp251863_ecc_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1300
mcp251863_filt_obj_t::bf
mcp251863_filt_obj_id_t bf
Definition: mcp251863.h:1030
mcp251863_bus_diag1_t::n_bit1_error
uint32_t n_bit1_error
Definition: mcp251863.h:1810
mcp251863_can_cfg_t::protocol_expection_event_disable
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:866
mcp251863_crc_t::crc
uint32_t crc
Definition: mcp251863.h:1686
mcp251863_fifo_ctl_t::rx_over_flow_ie
uint32_t rx_over_flow_ie
Definition: mcp251863.h:1165
mcp251863_ctl_t::protocol_exception_event_disable
uint32_t protocol_exception_event_disable
Definition: mcp251863.h:1078
mcp251863_fifo_stat_t::rx_full_if
uint32_t rx_full_if
Definition: mcp251863.h:1655
mcp251863_rx_msg_obj_ctl_t::ide
uint32_t ide
Definition: mcp251863.h:967
mcp251863_crc_value_get
err_t mcp251863_crc_value_get(mcp251863_t *ctx, uint16_t *crc)
Get CRC Value from device.
mcp251863_cfg_t::clk
pin_name_t clk
Definition: mcp251863.h:1908
mcp251863_crc_t::ferrie
uint32_t ferrie
Definition: mcp251863.h:1691
mcp251863_tx_fifo_cfg_t::pay_load_size
uint32_t pay_load_size
Definition: mcp251863.h:1340
mcp251863_int_cfg_t::ie
mcp251863_int_en_t ie
Definition: mcp251863.h:1505
mcp251863_ts_cfg_t::tbc_enable
uint32_t tbc_enable
Definition: mcp251863.h:1466
mcp251863_data_t::tx_config
mcp251863_tx_fifo_cfg_t tx_config
Definition: mcp251863.h:1861
mcp251863_can_cfg_t::restrict_re_tx_attempts
uint32_t restrict_re_tx_attempts
Definition: mcp251863.h:870
mcp251863_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: mcp251863.h:1913
mcp251863_io_ctl_t::word
uint32_t word
Definition: mcp251863.h:1285
mcp251863_t
MCP251863 Click context object.
Definition: mcp251863.h:1876
mcp251863_gpio_pin_set
err_t mcp251863_gpio_pin_set(mcp251863_t *ctx, uint8_t pos, uint8_t latch)
GPIO Output Pin Set.
mcp251863_receive_channel_event_overflow_clear
err_t mcp251863_receive_channel_event_overflow_clear(mcp251863_t *ctx, uint8_t channel)
Receive FIFO Event Clear.
mcp251863_ecc_ctl_t
MCP251863 Click ECC Control Register.
Definition: mcp251863.h:1295
mcp251863_bus_diag_flags_t
MCP251863 Click CAN Bus Diagnostic flags.
Definition: mcp251863.h:1735
mcp251863_tef_event_disable
err_t mcp251863_tef_event_disable(mcp251863_t *ctx, uint8_t flags)
Transmit Event FIFO Event Disable.
mcp251863_tef_ctl_t::teffulie
uint32_t teffulie
Definition: mcp251863.h:1138
mcp251863_config_t::tx_fifo_size
uint8_t tx_fifo_size
Definition: mcp251863.h:887
mcp251863_bus_diag1_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1815
mcp251863_module_event_enable
err_t mcp251863_module_event_enable(mcp251863_t *ctx, uint16_t flags)
Module Event Enable.
mcp251863_tx_que_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1120
mcp251863_receive_channel_configure
err_t mcp251863_receive_channel_configure(mcp251863_t *ctx, uint8_t channel, mcp251863_rx_fifo_cfg_t *config)
Configure Receive FIFO.
mcp251863_fifo_stat_t::rx_half_full_if
uint32_t rx_half_full_if
Definition: mcp251863.h:1654
mcp251863_int_en_t::txatie
uint32_t txatie
Definition: mcp251863.h:1490
mcp251863_write_word_safe
err_t mcp251863_write_word_safe(mcp251863_t *ctx, uint16_t address, uint32_t data_in)
SPI RAM Write Word Safe.
mcp251863_osc_sta_t::pll_ready
uint32_t pll_ready
Definition: mcp251863.h:1724
mcp251863_fifo_ctl_t::tx_half_full_ie
uint32_t tx_half_full_ie
Definition: mcp251863.h:1180
mcp251863_init
err_t mcp251863_init(mcp251863_t *ctx, mcp251863_cfg_t *cfg)
MCP251863 initialization function.
mcp251863_tx_fifo_cfg_t::tx_attempts
uint32_t tx_attempts
Definition: mcp251863.h:1338
mcp251863_error_count_state_get
err_t mcp251863_error_count_state_get(mcp251863_t *ctx, uint8_t *tec, uint8_t *rec, uint8_t *flags)
Error Counts and Error State Get.
mcp251863_tef_message_get
err_t mcp251863_tef_message_get(mcp251863_t *ctx, mcp251863_tef_msg_obj_t *tef_obj)
Get Transmit Event FIFO Message.
mcp251863_data_t::op_mode
uint8_t op_mode
Definition: mcp251863.h:1857
mcp251863_write_byte_array_with_crc
err_t mcp251863_write_byte_array_with_crc(mcp251863_t *ctx, bool from_ram)
SPI Write Byte Array with CRC.
mcp251863_ecc_event_clear
err_t mcp251863_ecc_event_clear(mcp251863_t *ctx, uint8_t flags)
ECC Event Clear.
mcp251863_bus_diag_t
MCP251863 Click CAN BUS DIAGNOSTICS.
Definition: mcp251863.h:1773
mcp251863_tx_que_ctl_t::tx_attempt_ie
uint32_t tx_attempt_ie
Definition: mcp251863.h:1111
mcp251863_config_t::fd_frame
uint8_t fd_frame
Definition: mcp251863.h:894
T_MCP251863_cfg_t::bit_rate_switch_disable
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:1320
mcp251863_tx_msg_obj_t
MCP251863 Click CAN TX Message Object.
Definition: mcp251863.h:949
mcp251863_tx_que_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1108
mcp251863_nbt_cfg_t::word
uint32_t word
Definition: mcp251863.h:1410
mcp251863_rx_msg_obj_t
MCP251863 Click CAN RX Message Object.
Definition: mcp251863.h:983
mcp251863_trec_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1598
mcp251863_nbt_cfg_t::brp
uint32_t brp
Definition: mcp251863.h:1408
mcp251863_int_flags_stat_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1543
mcp251863_filt_obj_t
MCP251863 Click Filter Object Register.
Definition: mcp251863.h:1029
mcp251863_read_byte
err_t mcp251863_read_byte(mcp251863_t *ctx, uint16_t address, uint8_t *data_out)
SPI Read Byte function.
mcp251863_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:1079
mcp251863_tef_update
err_t mcp251863_tef_update(mcp251863_t *ctx)
Transmit Event FIFO Update.
mcp251863_fifo_ctl_t::freset
uint32_t freset
Definition: mcp251863.h:1172
mcp251863_mask_obj_t::word
uint32_t word
Definition: mcp251863.h:1057
mcp251863_receive_event_overflow_get
err_t mcp251863_receive_event_overflow_get(mcp251863_t *ctx, uint32_t *rxovif)
Get pending RXOVIF of all receive FIFOs.
mcp251863_crc_event_enable
err_t mcp251863_crc_event_enable(mcp251863_t *ctx, uint8_t flags)
CRC Event Enable.
mcp251863_tx_msg_obj_t::ctrl
mcp251863_tx_msg_obj_ctl_t ctrl
Definition: mcp251863.h:952
mcp251863_bus_diag_flags_t::d_stuff_err
uint32_t d_stuff_err
Definition: mcp251863.h:1748
mcp251863_trec_t::rx_error_state_passive
uint32_t rx_error_state_passive
Definition: mcp251863.h:1595
mcp251863_int_en_t::serrie
uint32_t serrie
Definition: mcp251863.h:1492
mcp251863_receive_channel_status_get
err_t mcp251863_receive_channel_status_get(mcp251863_t *ctx, uint8_t channel, uint8_t *status)
Receive Channel Status Get.
mcp251863_crc_t
MCP251863 Click CRC Regsiter.
Definition: mcp251863.h:1684
mcp251863_io_ctl_t::tx_can_open_drain
uint32_t tx_can_open_drain
Definition: mcp251863.h:1280
mcp251863_can_cfg_t::store_in_tef
uint32_t store_in_tef
Definition: mcp251863.h:873
mcp251863_ecc_disable
err_t mcp251863_ecc_disable(mcp251863_t *ctx)
Disable ECC.
mcp251863_bus_error_count_t
MCP251863 Click CAN Bus Diagnostic Error Counts.
Definition: mcp251863.h:1760
mcp251863_config_t::tx_pay_load_size
uint8_t tx_pay_load_size
Definition: mcp251863.h:888
mcp251863_module_event_filter_hit_get
err_t mcp251863_module_event_filter_hit_get(mcp251863_t *ctx, uint8_t *filter_hit)
Get Filter Hit.
mcp251863_ecc_sta_t::dedif
uint32_t dedif
Definition: mcp251863.h:1708
mcp251863_bus_diag_t::flag
mcp251863_bus_diag_flags_t flag
Definition: mcp251863.h:1777
mcp251863_tx_fifo_cfg_t::tx_priority
uint32_t tx_priority
Definition: mcp251863.h:1337
mcp251863_error_state_get
err_t mcp251863_error_state_get(mcp251863_t *ctx, uint8_t *flags)
Error State Get.
mcp251863_t::glb_data
mcp251863_data_t glb_data
Definition: mcp251863.h:1889
mcp251863_bus_diag1_t::n_bit0_error
uint32_t n_bit0_error
Definition: mcp251863.h:1809
mcp251863_bus_diag0_t::d_rx_error_count
uint32_t d_rx_error_count
Definition: mcp251863.h:1793
mcp251863_func_data_t::n_bytes
uint16_t n_bytes
Definition: mcp251863.h:1839
mcp251863_data_t::error_flags
uint8_t error_flags
Definition: mcp251863.h:1854
mcp251863_ecc_parity_get
err_t mcp251863_ecc_parity_get(mcp251863_t *ctx, uint8_t *parity)
Get ECC Parity.
mcp251863_io_ctl_t::pin_mode0
uint32_t pin_mode0
Definition: mcp251863.h:1277
T_MCP251863_cfg_t::tx_band_width_sharing
uint32_t tx_band_width_sharing
Definition: mcp251863.h:1326
mcp251863_int_flag_t::if_stat
mcp251863_int_flags_stat_t if_stat
Definition: mcp251863.h:1562
mcp251863_bus_diag1_t::d_ack_error
uint32_t d_ack_error
Definition: mcp251863.h:1819
mcp251863_transmit_queue_configure
err_t mcp251863_transmit_queue_configure(mcp251863_t *ctx, mcp251863_tx_que_cfg_t *config)
Configure Transmit Queue.
mcp251863_io_ctl_t::unimplemented6
uint32_t unimplemented6
Definition: mcp251863.h:1283
mcp251863_fifo_ctl_t::rtr_enable
uint32_t rtr_enable
Definition: mcp251863.h:1185
mcp251863_config_t::standard_id
uint16_t standard_id
Definition: mcp251863.h:892
mcp251863_bus_diag0_t
MCP251863 Click Diagnostic register 0.
Definition: mcp251863.h:1789
T_MCP251863_cfg_t::iso_crc_enable
uint32_t iso_crc_enable
Definition: mcp251863.h:1316
mcp251863_osc_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1234
mcp251863_filter_to_fifo_link
err_t mcp251863_filter_to_fifo_link(mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable)
Link Filter to FIFO.
mcp251863_t::clk
digital_in_t clk
Definition: mcp251863.h:1881
mcp251863_trec_t::error_state_warning
uint32_t error_state_warning
Definition: mcp251863.h:1592
mcp251863_tef_ctl_t::unimplemented5
uint32_t unimplemented5
Definition: mcp251863.h:1148
mcp251863_oscillator_control_set
err_t mcp251863_oscillator_control_set(mcp251863_t *ctx, mcp251863_div_ctl_t ctrl)
Set Oscillator Control.
mcp251863_tef_t::word
uint32_t word
Definition: mcp251863.h:1618
mcp251863_bus_diag_t::error_free_msg_count
uint16_t error_free_msg_count
Definition: mcp251863.h:1776
mcp251863_tdc_cfg_t::unimplemented4
uint32_t unimplemented4
Definition: mcp251863.h:1450
mcp251863_bus_diag1_t::d_bit0_error
uint32_t d_bit0_error
Definition: mcp251863.h:1817
T_MCP251863_cfg_t::protocol_expection_event_disable
uint32_t protocol_expection_event_disable
Definition: mcp251863.h:1317
mcp251863_can_cfg_t::tx_band_width_sharing
uint32_t tx_band_width_sharing
Definition: mcp251863.h:875
mcp251863_cfg_t::miso
pin_name_t miso
Definition: mcp251863.h:1901
mcp251863_tx_que_ctl_t::tx_request
uint32_t tx_request
Definition: mcp251863.h:1115
mcp251863_bus_diag1_t
MCP251863 Click Diagnostic register 1.
Definition: mcp251863.h:1806
mcp251863_gpio_standby_control_enable
err_t mcp251863_gpio_standby_control_enable(mcp251863_t *ctx)
Enable Transceiver Standby Control.
mcp251863_rx_msg_obj_ctl_t::unimplemented1
uint32_t unimplemented1
Definition: mcp251863.h:972
mcp251863_read_byte_array
err_t mcp251863_read_byte_array(mcp251863_t *ctx, uint16_t address, uint8_t *data_out, uint16_t n_bytes)
SPI Read Byte Array.
mcp251863_bit_time_configure
err_t mcp251863_bit_time_configure(mcp251863_t *ctx, uint8_t bit_time, uint8_t clk)
Configure Bit Time registers (based on CAN clock speed).
mcp251863_tef_ctl_t::tefovie
uint32_t tefovie
Definition: mcp251863.h:1139
mcp251863_can_cfg_t::bit_rate_switch_disable
uint32_t bit_rate_switch_disable
Definition: mcp251863.h:869
mcp251863_tx_que_stat_t::tx_error
uint32_t tx_error
Definition: mcp251863.h:1635
mcp251863_bus_diag1_t::n_stuff_error
uint32_t n_stuff_error
Definition: mcp251863.h:1813
mcp251863_bus_diag0_t::d_tx_error_count
uint32_t d_tx_error_count
Definition: mcp251863.h:1794
mcp251863_module_event_clear
err_t mcp251863_module_event_clear(mcp251863_t *ctx, uint16_t flags)
Module Event Clear.
mcp251863_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: mcp251863.h:1914
mcp251863_ecc_ctl_t::secie
uint32_t secie
Definition: mcp251863.h:1298
mcp251863_rx_fifo_cfg_t::rx_time_stamp_enable
uint32_t rx_time_stamp_enable
Definition: mcp251863.h:1363
mcp251863_data_t::tx_id
uint32_t tx_id
Definition: mcp251863.h:1858
mcp251863_error_count_receive_get
err_t mcp251863_error_count_receive_get(mcp251863_t *ctx, uint8_t *rec)
Receive Error Count Get.
mcp251863_write_byte
err_t mcp251863_write_byte(mcp251863_t *ctx, uint16_t address, uint8_t data_in)
SPI Write Byte.
mcp251863_io_ctl_t::auto_sleep_enable
uint32_t auto_sleep_enable
Definition: mcp251863.h:1267
mcp251863_gpio_interrupt_pins_open_drain_configure
err_t mcp251863_gpio_interrupt_pins_open_drain_configure(mcp251863_t *ctx, uint8_t mode)
Configure Open Drain Interrupts.
mcp251863_crc_t::crcerrie
uint32_t crcerrie
Definition: mcp251863.h:1690
mcp251863_tx_que_cfg_t::fifo_size
uint32_t fifo_size
Definition: mcp251863.h:1352
mcp251863_config_t::tx_priority
uint8_t tx_priority
Definition: mcp251863.h:889
mcp251863_tef_ctl_t::uinc
uint32_t uinc
Definition: mcp251863.h:1143
mcp251863_transmit_channel_load
err_t mcp251863_transmit_channel_load(mcp251863_t *ctx, uint8_t channel, mcp251863_tx_msg_obj_t *tx_obj, bool flush)
TX Channel Load.
mcp251863_crc_t::ferrif
uint32_t ferrif
Definition: mcp251863.h:1688
mcp251863_bit_time_configure_nominal_20_mhz
err_t mcp251863_bit_time_configure_nominal_20_mhz(mcp251863_t *ctx, uint8_t bit_time)
Configure Nominal bit time for 20MHz system clock.