ntag5link  2.0.0.0
ntag5link.h
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3 ** Contact: https://www.mikroe.com/contact
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5 ** Permission is hereby granted, free of charge, to any person obtaining a copy
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22 
28 #ifndef NTAG5LINK_H
29 #define NTAG5LINK_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
39 #ifdef PREINIT_SUPPORTED
40 #include "preinit.h"
41 #endif
42 
43 #ifdef MikroCCoreVersion
44  #if MikroCCoreVersion >= 1
45  #include "delays.h"
46  #endif
47 #endif
48 
49 #include "drv_digital_out.h"
50 #include "drv_digital_in.h"
51 #include "drv_i2c_master.h"
52 
73 #define NTAG5LINK_CONFIG_SIGNATURE 0x1000
74 #define NTAG5LINK_CONFIG_HEADER 0x1008
75 #define NTAG5LINK_CONFIG_ID 0x1009
76 #define NTAG5LINK_CONFIG_NFC_GCH 0x100C
77 #define NTAG5LINK_CONFIG_NFC_CCH 0x100D
78 #define NTAG5LINK_CONFIG_NFC_AUTH_LIMIT 0x100E
79 #define NTAG5LINK_CONFIG_NFC_KH0 0x1010
80 #define NTAG5LINK_CONFIG_NFC_KP0 0x1011
81 #define NTAG5LINK_CONFIG_NFC_KH1 0x1012
82 #define NTAG5LINK_CONFIG_NFC_KP1 0x1013
83 #define NTAG5LINK_CONFIG_NFC_KH2 0x1014
84 #define NTAG5LINK_CONFIG_NFC_KP2 0x1015
85 #define NTAG5LINK_CONFIG_NFC_KH3 0x1016
86 #define NTAG5LINK_CONFIG_NFC_KP3 0x1017
87 #define NTAG5LINK_CONFIG_KEY_0 0x1020
88 #define NTAG5LINK_CONFIG_KEY_1 0x1024
89 #define NTAG5LINK_CONFIG_KEY_2 0x1028
90 #define NTAG5LINK_CONFIG_KEY_3 0x102C
91 #define NTAG5LINK_CONFIG_I2C_KH 0x1030
92 #define NTAG5LINK_CONFIG_I2C_PP_AND_PPC 0x1031
93 #define NTAG5LINK_CONFIG_I2C_AUTH_LIMIT 0x1032
94 #define NTAG5LINK_CONFIG_I2C_PWD_0 0x1033
95 #define NTAG5LINK_CONFIG_I2C_PWD_1 0x1034
96 #define NTAG5LINK_CONFIG_I2C_PWD_2 0x1035
97 #define NTAG5LINK_CONFIG_I2C_PWD_3 0x1036
98 #define NTAG5LINK_CONFIG_CONFIG 0x1037
99 #define NTAG5LINK_CONFIG_SYNC_DATA_BLOCK 0x1038
100 #define NTAG5LINK_CONFIG_PWM_GPIO_CONFIG 0x1039
101 #define NTAG5LINK_CONFIG_PWM0_ON_OFF 0x103A
102 #define NTAG5LINK_CONFIG_PWM1_ON_OFF 0x103B
103 #define NTAG5LINK_CONFIG_WDT_CFG_AND_SRAM_COPY 0x103C
104 #define NTAG5LINK_CONFIG_EH_AND_ED_CONFIG 0x103D
105 #define NTAG5LINK_CONFIG_I2C_SLAVE_MASTER_CFG 0x103E
106 #define NTAG5LINK_CONFIG_SEC_SRAM_AND_PP_AREA_1 0x103F
107 #define NTAG5LINK_CONFIG_SRAM_DEFAULT 0x1045
108 #define NTAG5LINK_CONFIG_AFI 0x1055
109 #define NTAG5LINK_CONFIG_DSFID 0x1056
110 #define NTAG5LINK_CONFIG_EAS_ID 0x1057
111 #define NTAG5LINK_CONFIG_NFC_PP_AREA_0_AND_PPC 0x1058
112 #define NTAG5LINK_CONFIG_NFC_LOCK_BLOCK 0x106A
113 #define NTAG5LINK_CONFIG_I2C_LOCK_BLOCK 0x108A
114 #define NTAG5LINK_CONFIG_NFC_SECTION_LOCK 0x1092
115 #define NTAG5LINK_CONFIG_I2C_SECTION_LOCK 0x1094
116 #define NTAG5LINK_CONFIG_I2C_PWD_0_AUTH 0x1096
117 #define NTAG5LINK_CONFIG_I2C_PWD_1_AUTH 0x1097
118 #define NTAG5LINK_CONFIG_I2C_PWD_2_AUTH 0x1098
119 #define NTAG5LINK_CONFIG_I2C_PWD_3_AUTH 0x1099
120 
125 #define NTAG5LINK_SESSION_REG_STATUS 0x10A0
126 #define NTAG5LINK_SESSION_REG_CONFIG 0x10A1
127 #define NTAG5LINK_SESSION_REG_SYNC_DATA_BLOCK 0x10A2
128 #define NTAG5LINK_SESSION_REG_PWM_GPIO_CONFIG 0x10A3
129 #define NTAG5LINK_SESSION_REG_PWM0_ON_OFF 0x10A4
130 #define NTAG5LINK_SESSION_REG_PWM1_ON_OFF 0x10A5
131 #define NTAG5LINK_SESSION_REG_WDT_CONFIG 0x10A6
132 #define NTAG5LINK_SESSION_REG_EH_CONFIG 0x10A7
133 #define NTAG5LINK_SESSION_REG_ED_CONFIG 0x10A8
134 #define NTAG5LINK_SESSION_REG_I2C_SLAVE_CONFIG 0x10A9
135 #define NTAG5LINK_SESSION_REG_RESET_GEN 0x10AA
136 #define NTAG5LINK_SESSION_REG_ED_INTR_CLEAR 0x10AB
137 #define NTAG5LINK_SESSION_REG_I2C_MASTER_CONFIG 0x10AC
138 #define NTAG5LINK_SESSION_REG_I2C_MASTER_STATUS 0x10AD
139 #define NTAG5LINK_SESSION_REG_BYTE_0 0x00
140 #define NTAG5LINK_SESSION_REG_BYTE_1 0x01
141 #define NTAG5LINK_SESSION_REG_BYTE_2 0x02
142 #define NTAG5LINK_SESSION_REG_BYTE_3 0x03
143  // ntag5link_reg
145 
160 #define NTAG5LINK_USER_MEMORY_ADDRESS_MIN 0x0000
161 #define NTAG5LINK_USER_MEMORY_ADDRESS_MAX 0x01FF
162 #define NTAG5LINK_CONFIG_MEMORY_ADDRESS_MIN 0x1000
163 #define NTAG5LINK_CONFIG_MEMORY_ADDRESS_MAX 0x109F
164 #define NTAG5LINK_SESSION_REG_ADDRESS_MIN 0x10A0
165 #define NTAG5LINK_SESSION_REG_ADDRESS_MAX 0x10AF
166 #define NTAG5LINK_MEMORY_BLOCK_SIZE 4
167 
172 #define NTAG5LINK_CONFIG_0_SRAM_COPY_ENABLE 0x80
173 #define NTAG5LINK_CONFIG_0_EH_LOW_FIELD_STR 0x08
174 #define NTAG5LINK_CONFIG_0_EH_HIGH_FIELD_STR 0x0C
175 #define NTAG5LINK_CONFIG_0_LOCK_SESSION_REG 0x02
176 #define NTAG5LINK_CONFIG_0_AUTO_STANDBY_MODE_EN 0x01
177 #define NTAG5LINK_CONFIG_1_EH_ARBITER_MODE_EN 0x80
178 #define NTAG5LINK_CONFIG_1_USE_CASE_I2C_SLAVE 0x00
179 #define NTAG5LINK_CONFIG_1_USE_CASE_I2C_MASTER 0x10
180 #define NTAG5LINK_CONFIG_1_USE_CASE_GPIO_PWM 0x20
181 #define NTAG5LINK_CONFIG_1_USE_CASE_3_STATE 0x30
182 #define NTAG5LINK_CONFIG_1_ARBITER_NORMAL_MODE 0x00
183 #define NTAG5LINK_CONFIG_1_ARBITER_SRAM_MIRROR 0x04
184 #define NTAG5LINK_CONFIG_1_ARBITER_SRAM_PT 0x08
185 #define NTAG5LINK_CONFIG_1_ARBITER_SRAM_PHDC 0x0C
186 #define NTAG5LINK_CONFIG_1_SRAM_ENABLE 0x02
187 #define NTAG5LINK_CONFIG_1_PT_TRANSFER_I2C_NFC 0x00
188 #define NTAG5LINK_CONFIG_1_PT_TRANSFER_NFC_I2C 0x01
189 #define NTAG5LINK_CONFIG_2_GPIO1_IN_DISABLE 0x00
190 #define NTAG5LINK_CONFIG_2_GPIO1_IN_PULL_UP 0x40
191 #define NTAG5LINK_CONFIG_2_GPIO1_IN_ENABLE 0x80
192 #define NTAG5LINK_CONFIG_2_GPIO1_IN_PULL_DOWN 0xC0
193 #define NTAG5LINK_CONFIG_2_GPIO0_IN_DISABLE 0x00
194 #define NTAG5LINK_CONFIG_2_GPIO0_IN_PULL_UP 0x10
195 #define NTAG5LINK_CONFIG_2_GPIO0_IN_ENABLE 0x20
196 #define NTAG5LINK_CONFIG_2_GPIO0_IN_PULL_DOWN 0x30
197 #define NTAG5LINK_CONFIG_2_EXT_CMD_SUPPORT 0x08
198 #define NTAG5LINK_CONFIG_2_LOCK_BLK_CMD_SUPPORT 0x04
199 #define NTAG5LINK_CONFIG_2_GPIO1_HIGH_SLEW_RATE 0x02
200 #define NTAG5LINK_CONFIG_2_GPIO0_HIGH_SLEW_RATE 0x01
201 
206 #define NTAG5LINK_CAPABILITY_CONTAINER_ADDRESS 0x0000
207 #define NTAG5LINK_CAPABILITY_CONTAINER 0xE1, 0x40, 0x80, 0x01
208 #define NTAG5LINK_NDEF_MESSAGE_START_ADDRESS 0x0001
209 #define NTAG5LINK_TYPE_NDEF_MESSAGE 0x03
210 #define NTAG5LINK_NDEF_RECORD_HEADER 0xD1
211 #define NTAG5LINK_NDEF_TYPE_LENGTH 0x01
212 #define NTAG5LINK_NDEF_URI_TYPE 'U'
213 #define NTAG5LINK_NDEF_MESSAGE_END_MARK 0xFE
214 
219 #define NTAG5LINK_URI_PREFIX_0 0x00
220 #define NTAG5LINK_URI_PREFIX_1 0x01
221 #define NTAG5LINK_URI_PREFIX_2 0x02
222 #define NTAG5LINK_URI_PREFIX_3 0x03
223 #define NTAG5LINK_URI_PREFIX_4 0x04
224 #define NTAG5LINK_URI_PREFIX_5 0x05
225 #define NTAG5LINK_URI_PREFIX_6 0x06
226 #define NTAG5LINK_URI_PREFIX_7 0x07
227 #define NTAG5LINK_URI_PREFIX_8 0x08
228 #define NTAG5LINK_URI_PREFIX_9 0x09
229 #define NTAG5LINK_URI_PREFIX_10 0x0A
230 #define NTAG5LINK_URI_PREFIX_11 0x0B
231 #define NTAG5LINK_URI_PREFIX_12 0x0C
232 #define NTAG5LINK_URI_PREFIX_13 0x0D
233 #define NTAG5LINK_URI_PREFIX_14 0x0E
234 #define NTAG5LINK_URI_PREFIX_15 0x0F
235 #define NTAG5LINK_URI_PREFIX_16 0x10
236 #define NTAG5LINK_URI_PREFIX_17 0x11
237 #define NTAG5LINK_URI_PREFIX_18 0x12
238 #define NTAG5LINK_URI_PREFIX_19 0x13
239 #define NTAG5LINK_URI_PREFIX_20 0x14
240 #define NTAG5LINK_URI_PREFIX_21 0x15
241 #define NTAG5LINK_URI_PREFIX_22 0x16
242 #define NTAG5LINK_URI_PREFIX_23 0x17
243 #define NTAG5LINK_URI_PREFIX_24 0x18
244 #define NTAG5LINK_URI_PREFIX_25 0x19
245 #define NTAG5LINK_URI_PREFIX_26 0x1A
246 #define NTAG5LINK_URI_PREFIX_27 0x1B
247 #define NTAG5LINK_URI_PREFIX_28 0x1C
248 #define NTAG5LINK_URI_PREFIX_29 0x1D
249 #define NTAG5LINK_URI_PREFIX_30 0x1E
250 #define NTAG5LINK_URI_PREFIX_31 0x1F
251 #define NTAG5LINK_URI_PREFIX_32 0x20
252 #define NTAG5LINK_URI_PREFIX_33 0x21
253 #define NTAG5LINK_URI_PREFIX_34 0x22
254 #define NTAG5LINK_URI_PREFIX_35 0x23
261 #define NTAG5LINK_DEVICE_ADDRESS 0x54
262  // ntag5link_set
264 
279 #define NTAG5LINK_MAP_MIKROBUS( cfg, mikrobus ) \
280  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
281  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
282  cfg.hpd = MIKROBUS( mikrobus, MIKROBUS_RST ); \
283  cfg.ed = MIKROBUS( mikrobus, MIKROBUS_INT )
284  // ntag5link_map // ntag5link
287 
288 
293 typedef union
294 {
295  uint8_t value_bytes[ 4 ];
296  uint32_t value;
298 
303 typedef struct
304 {
305  // Output pins
306  digital_out_t hpd;
308  // Input pins
309  digital_in_t ed;
311  // Modules
312  i2c_master_t i2c;
314  // I2C slave address
315  uint8_t slave_address;
317 } ntag5link_t;
318 
323 typedef struct
324 {
325  pin_name_t scl;
326  pin_name_t sda;
328  pin_name_t hpd;
329  pin_name_t ed;
331  uint32_t i2c_speed;
332  uint8_t i2c_address;
335 
340 typedef enum
341 {
343  NTAG5LINK_ERROR = -1
344 
346 
363 
379 
394 
408 err_t ntag5link_write_memory_block ( ntag5link_t *ctx, uint16_t block_addr, ntag5link_block_t *block );
409 
423 err_t ntag5link_read_memory_block ( ntag5link_t *ctx, uint16_t block_addr, ntag5link_block_t *block );
424 
440 err_t ntag5link_write_multiple_memory_block ( ntag5link_t *ctx, uint16_t block_addr,
441  ntag5link_block_t *block, uint8_t num_blocks );
442 
458 err_t ntag5link_read_multiple_memory_block ( ntag5link_t *ctx, uint16_t block_addr,
459  ntag5link_block_t *block, uint8_t num_blocks );
460 
475 err_t ntag5link_write_session_register ( ntag5link_t *ctx, uint16_t block_addr, uint8_t byte_num,
476  uint8_t mask, uint8_t data_in );
477 
491 err_t ntag5link_read_session_register ( ntag5link_t *ctx, uint16_t block_addr, uint8_t byte_num, uint8_t *data_out );
492 
508 err_t ntag5link_write_ndef_uri_record ( ntag5link_t *ctx, uint8_t uri_prefix, uint8_t *uri_data, uint8_t data_len );
509 
521 
536 err_t ntag5link_write_message_to_memory ( ntag5link_t *ctx, uint16_t block_addr, uint8_t *message, uint16_t message_len );
537 
552 err_t ntag5link_read_message_from_memory ( ntag5link_t *ctx, uint16_t block_addr, uint8_t *message, uint16_t message_len );
553 
563 
573 
583 
584 #ifdef __cplusplus
585 }
586 #endif
587 #endif // NTAG5LINK_H
588  // ntag5link
590 
591 // ------------------------------------------------------------------------ END