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35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_spi_master.h"
60 #define MRAM3_CMD_NOP 0x00
61 #define MRAM3_CMD_WRITE_ENABLE 0x06
62 #define MRAM3_CMD_WRITE_DISABLE 0x04
63 #define MRAM3_CMD_ENABLE_DPI 0x37
64 #define MRAM3_CMD_ENABLE_QPI 0x38
65 #define MRAM3_CMD_ENABLE_SPI 0xFF
66 #define MRAM3_CMD_ENTER_DEEP_POWER_DOWN 0xB9
67 #define MRAM3_CMD_ENTER_HIBERNATE 0xBA
68 #define MRAM3_CMD_SOFT_RESET_ENABLE 0x66
69 #define MRAM3_CMD_SOFT_RESET 0x99
70 #define MRAM3_CMD_EXIT_DEEP_POWER_DOWN 0xAB
76 #define MRAM3_CMD_READ_STATUS 0x05
77 #define MRAM3_CMD_READ_CONFIG_1 0x35
78 #define MRAM3_CMD_READ_CONFIG_2 0x3F
79 #define MRAM3_CMD_READ_CONFIG_3 0x44
80 #define MRAM3_CMD_READ_CONFIG_4 0x45
81 #define MRAM3_CMD_READ_CONFIG_ALL 0x46
82 #define MRAM3_CMD_READ_DEVICE_ID 0x9F
83 #define MRAM3_CMD_READ_UNIQUE_ID 0x4C
84 #define MRAM3_CMD_READ_SERIAL_NUMBER 0xC3
85 #define MRAM3_CMD_READ_AUG_ARRAY_PROTECT 0x14
86 #define MRAM3_CMD_READ_ADDRESS_BASED 0x65
92 #define MRAM3_CMD_WRITE_STATUS 0x01
93 #define MRAM3_CMD_WRITE_CONFIG_ALL 0x87
94 #define MRAM3_CMD_WRITE_SERIAL_NUMBER 0xC2
95 #define MRAM3_CMD_WRITE_AUG_ARRAY_PROTECT 0x1A
96 #define MRAM3_CMD_WRITE_ADDRESS_BASED 0x71
102 #define MRAM3_CMD_READ_MEMORY_SDR 0x03
103 #define MRAM3_CMD_FAST_READ_MEMORY_SDR 0x0B
104 #define MRAM3_CMD_FAST_READ_MEMORY_DDR 0x0D
105 #define MRAM3_CMD_READ_DUAL_OUT_MEMORY_SDR 0x3B
106 #define MRAM3_CMD_READ_QUAD_OUT_MEMORY_SDR 0x6B
107 #define MRAM3_CMD_READ_DUAL_IO_MEMORY_SDR 0xBB
108 #define MRAM3_CMD_READ_DUAL_IO_MEMORY_DDR 0xBD
109 #define MRAM3_CMD_READ_QUAD_IO_MEMORY_SDR 0xEB
110 #define MRAM3_CMD_READ_QUAD_IO_MEMORY_DDR 0xED
116 #define MRAM3_CMD_WRITE_MEMORY_SDR 0x02
117 #define MRAM3_CMD_FAST_WRITE_MEMORY_SDR 0xDA
118 #define MRAM3_CMD_FAST_WRITE_MEMORY_DDR 0xDE
119 #define MRAM3_CMD_WRITE_DUAL_IN_MEMORY_SDR 0xA2
120 #define MRAM3_CMD_WRITE_QUAD_IN_MEMORY_SDR 0x32
121 #define MRAM3_CMD_WRITE_QUAD_IN_MEMORY_DDR 0x31
122 #define MRAM3_CMD_WRITE_DUAL_IO_MEMORY_SDR 0xA1
123 #define MRAM3_CMD_WRITE_QUAD_IO_MEMORY_SDR 0xD2
124 #define MRAM3_CMD_WRITE_QUAD_IO_MEMORY_DDR 0xD1
130 #define MRAM3_CMD_READ_AUG_STORAGE_SDR 0x4B
131 #define MRAM3_CMD_WRITE_AUG_STORAGE_SDR 0x42
149 #define MRAM3_STATUS_WPEN 0x80
150 #define MRAM3_STATUS_SNPEN 0x40
151 #define MRAM3_STATUS_TBSEL_BOTTOM 0x20
152 #define MRAM3_STATUS_TBSEL_TOP 0x00
153 #define MRAM3_STATUS_BPSEL_NONE 0x00
154 #define MRAM3_STATUS_BPSEL_UPPER_1_64 0x04
155 #define MRAM3_STATUS_BPSEL_UPPER_1_32 0x08
156 #define MRAM3_STATUS_BPSEL_UPPER_1_16 0x0C
157 #define MRAM3_STATUS_BPSEL_UPPER_1_8 0x10
158 #define MRAM3_STATUS_BPSEL_UPPER_QUARTER 0x14
159 #define MRAM3_STATUS_BPSEL_UPPER_HALF 0x18
160 #define MRAM3_STATUS_BPSEL_ALL 0x1C
161 #define MRAM3_STATUS_WREN 0x02
167 #define MRAM3_CONFIG1_MAPLK_LOCK 0x04
168 #define MRAM3_CONFIG1_MAPLK_UNLOCK 0x00
169 #define MRAM3_CONFIG1_ASPLK_LOCK 0x01
170 #define MRAM3_CONFIG1_ASPLK_UNLOCK 0x00
171 #define MRAM3_CONFIG2_QUAD_SPI 0x40
172 #define MRAM3_CONFIG2_DUAL_SPI 0x10
173 #define MRAM3_CONFIG2_MLATS_0_CYCLES 0x00
174 #define MRAM3_CONFIG2_MLATS_1_CYCLE 0x01
175 #define MRAM3_CONFIG2_MLATS_2_CYCLES 0x02
176 #define MRAM3_CONFIG2_MLATS_3_CYCLES 0x03
177 #define MRAM3_CONFIG2_MLATS_4_CYCLES 0x04
178 #define MRAM3_CONFIG2_MLATS_5_CYCLES 0x05
179 #define MRAM3_CONFIG2_MLATS_6_CYCLES 0x06
180 #define MRAM3_CONFIG2_MLATS_7_CYCLES 0x07
181 #define MRAM3_CONFIG2_MLATS_8_CYCLES 0x08
182 #define MRAM3_CONFIG2_MLATS_9_CYCLES 0x09
183 #define MRAM3_CONFIG2_MLATS_10_CYCLES 0x0A
184 #define MRAM3_CONFIG2_MLATS_11_CYCLES 0x0B
185 #define MRAM3_CONFIG2_MLATS_12_CYCLES 0x0C
186 #define MRAM3_CONFIG2_MLATS_13_CYCLES 0x0D
187 #define MRAM3_CONFIG2_MLATS_14_CYCLES 0x0E
188 #define MRAM3_CONFIG2_MLATS_15_CYCLES 0x0F
189 #define MRAM3_CONFIG3_ODSEL_35OHM 0x00
190 #define MRAM3_CONFIG3_ODSEL_75OHM 0x20
191 #define MRAM3_CONFIG3_ODSEL_60OHM 0x40
192 #define MRAM3_CONFIG3_ODSEL_45OHM 0x60
193 #define MRAM3_CONFIG3_ODSEL_40OHM 0xA0
194 #define MRAM3_CONFIG3_ODSEL_20OHM 0xC0
195 #define MRAM3_CONFIG3_ODSEL_15OHM 0xE0
196 #define MRAM3_CONFIG3_WRAPS_ENABLE 0x10
197 #define MRAM3_CONFIG3_WRPLS_16BYTE 0x00
198 #define MRAM3_CONFIG3_WRPLS_32BYTE 0x01
199 #define MRAM3_CONFIG3_WRPLS_64BYTE 0x02
200 #define MRAM3_CONFIG3_WRPLS_128BYTE 0x03
201 #define MRAM3_CONFIG3_WRPLS_256BYTE 0x04
202 #define MRAM3_CONFIG4_WRENS_NORMAL 0x04
203 #define MRAM3_CONFIG4_WRENS_SRAM 0x05
204 #define MRAM3_CONFIG4_WRENS_BACK_TO_BACK 0x06
210 #define MRAM3_MIN_ADDRESS 0x000000
211 #define MRAM3_MAX_ADDRESS 0x01FFFFul
217 #define MRAM3_DEVICE_ID 0xE6010102ul
227 #define MRAM3_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
228 #define MRAM3_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
246 #define MRAM3_MAP_MIKROBUS( cfg, mikrobus ) \
247 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
248 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
249 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
250 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
251 cfg.io3 = MIKROBUS( mikrobus, MIKROBUS_RST ); \
252 cfg.wp = MIKROBUS( mikrobus, MIKROBUS_PWM );
err_t mram3_init(mram3_t *ctx, mram3_cfg_t *cfg)
MRAM 3 initialization function.
@ MRAM3_OK
Definition: mram3.h:303
pin_name_t sck
Definition: mram3.h:283
err_t mram3_write_cmd(mram3_t *ctx, uint8_t cmd)
MRAM 3 write cmd function.
pin_name_t mosi
Definition: mram3.h:282
pin_name_t miso
Definition: mram3.h:281
err_t mram3_memory_write(mram3_t *ctx, uint32_t address, uint8_t *data_in, uint32_t len)
MRAM 3 memory write function.
digital_out_t wp
Definition: mram3.h:265
err_t mram3_write_status(mram3_t *ctx, uint8_t status)
MRAM 3 write status function.
spi_master_mode_t spi_mode
Definition: mram3.h:292
This file contains SPI specific macros, functions, etc.
err_t mram3_write_enable(mram3_t *ctx)
MRAM 3 write enable function.
spi_master_t spi
Definition: mram3.h:268
err_t mram3_check_communication(mram3_t *ctx)
MRAM 3 check communication function.
MRAM 3 Click configuration object.
Definition: mram3.h:279
pin_name_t io3
Definition: mram3.h:287
pin_name_t cs
Definition: mram3.h:284
err_t mram3_aug_memory_write(mram3_t *ctx, uint8_t address, uint8_t *data_in, uint8_t len)
MRAM 3 aug memory write function.
err_t mram3_memory_read(mram3_t *ctx, uint32_t address, uint8_t *data_out, uint32_t len)
MRAM 3 memory read function.
err_t mram3_default_cfg(mram3_t *ctx)
MRAM 3 default configuration function.
err_t mram3_read_status(mram3_t *ctx, uint8_t *status)
MRAM 3 read status function.
err_t mram3_read_cmd_address_data(mram3_t *ctx, uint8_t cmd, uint32_t address, uint8_t *data_out, uint32_t len)
MRAM 3 read cmd address data function.
err_t mram3_read_cmd_data(mram3_t *ctx, uint8_t cmd, uint8_t *data_out, uint8_t len)
MRAM 3 read cmd data function.
void mram3_cfg_setup(mram3_cfg_t *cfg)
MRAM 3 configuration object setup function.
mram3_return_value_t
MRAM 3 Click return value data.
Definition: mram3.h:302
MRAM 3 Click context object.
Definition: mram3.h:262
err_t mram3_write_cmd_data(mram3_t *ctx, uint8_t cmd, uint8_t *data_in, uint8_t len)
MRAM 3 write cmd data function.
spi_master_chip_select_polarity_t cs_polarity
Definition: mram3.h:293
uint32_t spi_speed
Definition: mram3.h:291
pin_name_t chip_select
Definition: mram3.h:270
err_t mram3_aug_memory_read(mram3_t *ctx, uint8_t address, uint8_t *data_out, uint8_t len)
MRAM 3 aug memory read function.
pin_name_t wp
Definition: mram3.h:288
err_t mram3_soft_reset(mram3_t *ctx)
MRAM 3 soft reset function.
err_t mram3_write_protect(mram3_t *ctx)
MRAM 3 write protect function.
err_t mram3_write_cmd_address_data(mram3_t *ctx, uint8_t cmd, uint32_t address, uint8_t *data_in, uint32_t len)
MRAM 3 write cmd address data function.
digital_out_t io3
Definition: mram3.h:264
@ MRAM3_ERROR
Definition: mram3.h:304