uwb2  2.1.0.0
uwb2.h
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2 ** Copyright (C) 2020 MikroElektronika d.o.o.
3 ** Contact: https://www.mikroe.com/contact
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5 ** Permission is hereby granted, free of charge, to any person obtaining a copy
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22 
28 #ifndef UWB2_H
29 #define UWB2_H
30 
31 #ifdef __cplusplus
32 extern "C"{
33 #endif
34 
35 #include "drv_digital_out.h"
36 #include "drv_digital_in.h"
37 #include "drv_spi_master.h"
38 #include "spi_specifics.h"
39 
60 #define UWB2_CMD_TXRXOFF 0x00
61 #define UWB2_CMD_TX 0x01
62 #define UWB2_CMD_RX 0x02
63 #define UWB2_CMD_DTX 0x03
64 #define UWB2_CMD_DRX 0x04
65 #define UWB2_CMD_DTX_TS 0x05
66 #define UWB2_CMD_DRX_TS 0x06
67 #define UWB2_CMD_DTX_RS 0x07
68 #define UWB2_CMD_DRX_RS 0x08
69 #define UWB2_CMD_DTX_REF 0x09
70 #define UWB2_CMD_DRX_REF 0x0A
71 #define UWB2_CMD_CCA_TX 0x0B
72 #define UWB2_CMD_TX_W4R 0x0C
73 #define UWB2_CMD_DTX_W4R 0x0D
74 #define UWB2_CMD_DTX_TS_W4R 0x0E
75 #define UWB2_CMD_DTX_RS_W4R 0x0F
76 #define UWB2_CMD_DTX_REF_W4R 0x10
77 #define UWB2_CMD_CCA_TX_W4R 0x11
78 #define UWB2_CMD_CLR_IRQS 0x12
79 #define UWB2_CMD_DB_TOGGLE 0x13
80 
87 #define UWB2_REG_DEV_ID 0x0000u
88 #define UWB2_REG_EUI_64 0x0004u
89 #define UWB2_REG_PANADR 0x000Cu
90 #define UWB2_REG_SYS_CFG 0x0010u
91 #define UWB2_REG_FF_CFG 0x0014u
92 #define UWB2_REG_SPI_RD_CRC 0x0018u
93 #define UWB2_REG_SYS_TIME 0x001Cu
94 #define UWB2_REG_TX_FCTRL_LO 0x0024u
95 #define UWB2_REG_TX_FCTRL_HI 0x0028u
96 #define UWB2_REG_DX_TIME 0x002Cu
97 #define UWB2_REG_DREF_TIME 0x0030u
98 #define UWB2_REG_RX_FWTO 0x0034u
99 #define UWB2_REG_SYS_CTRL 0x0038u
100 #define UWB2_REG_SYS_ENABLE_LO 0x003Cu
101 #define UWB2_REG_SYS_ENABLE_HI 0x0040u
102 #define UWB2_REG_SYS_STATUS_LO 0x0044u
103 #define UWB2_REG_SYS_STATUS_HI 0x0048u
104 #define UWB2_REG_RX_FINFO 0x004Cu
105 #define UWB2_REG_RX_TIME 0x0064u
106 #define UWB2_REG_TX_TIME 0x0074u
107 #define UWB2_REG_TX_RAWST 0x0100u
108 #define UWB2_REG_TX_ANTD 0x0104u
109 #define UWB2_REG_ACK_RESP_T 0x0108u
110 #define UWB2_REG_TX_POWER 0x010Cu
111 #define UWB2_REG_CHAN_CTRL 0x0114u
112 #define UWB2_REG_LE_PEND_01 0x0118u
113 #define UWB2_REG_LE_PEND_23 0x011Cu
114 #define UWB2_REG_SPI_COLLISION 0x0120u
115 #define UWB2_REG_RDB_STATUS 0x0124u
116 #define UWB2_REG_RDB_DIAG 0x0128u
117 #define UWB2_REG_AES_CFG 0x0130u
118 #define UWB2_REG_AES_IV0 0x0134u
119 #define UWB2_REG_AES_IV1 0x0138u
120 #define UWB2_REG_AES_IV2 0x013Cu
121 #define UWB2_REG_AES_IV3 0x0140u
122 #define UWB2_REG_DMA_CFG 0x0144u
123 #define UWB2_REG_AES_START 0x014Cu
124 #define UWB2_REG_AES_STS 0x0150u
125 #define UWB2_REG_AES_KEY 0x0154u
126 #define UWB2_REG_STS_CFG 0x0200u
127 #define UWB2_REG_STS_CTRL 0x0204u
128 #define UWB2_REG_STS_STS 0x0208u
129 #define UWB2_REG_STS_KEY 0x020Cu
130 #define UWB2_REG_STS_IV 0x021Cu
131 #define UWB2_REG_DGC_CFG 0x0318u
132 #define UWB2_REG_DGC_CFG_0 0x031Cu
133 #define UWB2_REG_DGC_CFG_1 0x0320u
134 #define UWB2_REG_DGC_LUT_0 0x0338u
135 #define UWB2_REG_DGC_LUT_1 0x033Cu
136 #define UWB2_REG_DGC_LUT_2 0x0340u
137 #define UWB2_REG_DGC_LUT_3 0x0344u
138 #define UWB2_REG_DGC_LUT_4 0x0348u
139 #define UWB2_REG_DGC_LUT_5 0x034Cu
140 #define UWB2_REG_DGC_LUT_6 0x0350u
141 #define UWB2_REG_DGC_DBG 0x0360u
142 #define UWB2_REG_EC_CTRL 0x0400u
143 #define UWB2_REG_RX_CAL 0x040Cu
144 #define UWB2_REG_RX_CAL_RESI 0x0414u
145 #define UWB2_REG_RX_CAL_RESQ 0x041Cu
146 #define UWB2_REG_RX_CAL_STS 0x0420u
147 #define UWB2_REG_GPIO_MODE 0x0500u
148 #define UWB2_REG_GPIO_PULL_EN 0x0504u
149 #define UWB2_REG_GPIO_DIR 0x0508u
150 #define UWB2_REG_GPIO_OUT 0x050Cu
151 #define UWB2_REG_GPIO_IRQE 0x0510u
152 #define UWB2_REG_GPIO_ISTS 0x0514u
153 #define UWB2_REG_GPIO_ISEN 0x0518u
154 #define UWB2_REG_GPIO_IMODE 0x051Cu
155 #define UWB2_REG_GPIO_IBES 0x0520u
156 #define UWB2_REG_GPIO_ICLR 0x0524u
157 #define UWB2_REG_GPIO_IDBE 0x0528u
158 #define UWB2_REG_GPIO_RAW 0x052Cu
159 #define UWB2_REG_DTUNE_0 0x0600u
160 #define UWB2_REG_RX_SFD_TOC 0x0602u
161 #define UWB2_REG_PRE_TOC 0x0604u
162 #define UWB2_REG_DTUNE_3 0x060Cu
163 #define UWB2_REG_DTUNE_4 0x0610u
164 #define UWB2_REG_DTUNE_5 0x0614u
165 #define UWB2_REG_DRX_CAR_INT 0x0629u
166 #define UWB2_REG_RF_ENABLE 0x0700u
167 #define UWB2_REG_RF_CTRL_MASK 0x0704u
168 #define UWB2_REG_RF_SWITCH 0x0714u
169 #define UWB2_REG_RF_TX_CTRL_1 0x071Au
170 #define UWB2_REG_RF_TX_CTRL_2 0x071Cu
171 #define UWB2_REG_TX_TEST 0x0728u
172 #define UWB2_REG_SAR_TEST 0x0734u
173 #define UWB2_REG_LDO_TUNE_LO 0x0740u
174 #define UWB2_REG_LDO_TUNE_HI 0x0744u
175 #define UWB2_REG_LDO_CTRL 0x0748u
176 #define UWB2_REG_LDO_RLOAD 0x0751u
177 #define UWB2_REG_SAR_CTRL 0x0800u
178 #define UWB2_REG_SAR_STATUS 0x0804u
179 #define UWB2_REG_SAR_READING 0x0808u
180 #define UWB2_REG_SAR_WAKE_RD 0x080Cu
181 #define UWB2_REG_PGC_CTRL 0x0810u
182 #define UWB2_REG_PGC_STATUS 0x0814u
183 #define UWB2_REG_PG_TEST 0x0818u
184 #define UWB2_REG_PG_CAL_TARGET 0x081Cu
185 #define UWB2_REG_PLL_CFG 0x0900u
186 #define UWB2_REG_PLL_CC 0x0904u
187 #define UWB2_REG_PLL_CAL 0x0908u
188 #define UWB2_REG_XTAL 0x0914u
189 #define UWB2_REG_AON_DIG_CFG 0x0A00u
190 #define UWB2_REG_AON_CTRL 0x0A04u
191 #define UWB2_REG_AON_RDATA 0x0A08u
192 #define UWB2_REG_AON_ADDR 0x0A0Cu
193 #define UWB2_REG_AON_WDATA 0x0A10u
194 #define UWB2_REG_AON_CFG 0x0A14u
195 #define UWB2_REG_OTP_WDATA 0x0B00u
196 #define UWB2_REG_OTP_ADDR 0x0B04u
197 #define UWB2_REG_OTP_CFG 0x0B08u
198 #define UWB2_REG_OTP_STAT 0x0B0Cu
199 #define UWB2_REG_OTP_RDATA 0x0B10u
200 #define UWB2_REG_OTP_SRDATA 0x0B14u
201 #define UWB2_REG_IP_TS 0x0C00u
202 #define UWB2_REG_STS_TS 0x0C08u
203 #define UWB2_REG_STS1_TS 0x0C10u
204 #define UWB2_REG_TDOA 0x0C18u
205 #define UWB2_REG_PDOA 0x0C1Eu
206 #define UWB2_REG_CIA_DIAG_0 0x0C20u
207 #define UWB2_REG_IP_DIAG_0 0x0C28u
208 #define UWB2_REG_IP_DIAG_1 0x0C2Cu
209 #define UWB2_REG_IP_DIAG_2 0x0C30u
210 #define UWB2_REG_IP_DIAG_3 0x0C34u
211 #define UWB2_REG_IP_DIAG_4 0x0C38u
212 #define UWB2_REG_IP_DIAG_8 0x0C48u
213 #define UWB2_REG_IP_DIAG_12 0x0C58u
214 #define UWB2_REG_STS_DIAG_0 0x0C5Cu
215 #define UWB2_REG_STS_DIAG_1 0x0C60u
216 #define UWB2_REG_STS_DIAG_2 0x0C64u
217 #define UWB2_REG_STS_DIAG_3 0x0C68u
218 #define UWB2_REG_STS_DIAG_4 0x0D00u
219 #define UWB2_REG_STS_DIAG_8 0x0D10u
220 #define UWB2_REG_STS_DIAG_12 0x0D20u
221 #define UWB2_REG_STS1_DIAG_0 0x0D38u
222 #define UWB2_REG_STS1_DIAG_1 0x0D3Cu
223 #define UWB2_REG_STS1_DIAG_2 0x0D40u
224 #define UWB2_REG_STS1_DIAG_3 0x0D44u
225 #define UWB2_REG_STS1_DIAG_4 0x0D48u
226 #define UWB2_REG_STS1_DIAG_8 0x0D58u
227 #define UWB2_REG_STS1_DIAG_12 0x0D68u
228 #define UWB2_REG_CIA_CONF 0x0E00u
229 #define UWB2_REG_FP_CONF 0x0E04u
230 #define UWB2_REG_IP_CONF 0x0E0Cu
231 #define UWB2_REG_STS_CONF_0 0x0E12u
232 #define UWB2_REG_STS_CONF_1 0x0E16u
233 #define UWB2_REG_CIA_ADJUST 0x0E1Au
234 #define UWB2_REG_EVC_CTRL 0x0F00u
235 #define UWB2_REG_EVC_PHE 0x0F04u
236 #define UWB2_REG_EVC_RSE 0x0F06u
237 #define UWB2_REG_EVC_FCG 0x0F08u
238 #define UWB2_REG_EVC_FCE 0x0F0Au
239 #define UWB2_REG_EVC_FFR 0x0F0Cu
240 #define UWB2_REG_EVC_OVR 0x0F0Eu
241 #define UWB2_REG_EVC_STO 0x0F10u
242 #define UWB2_REG_EVC_PTO 0x0F12u
243 #define UWB2_REG_EVC_FWTO 0x0F14u
244 #define UWB2_REG_EVC_TXFS 0x0F16u
245 #define UWB2_REG_EVC_HPW 0x0F18u
246 #define UWB2_REG_EVC_SWCE 0x0F1Au
247 #define UWB2_REG_EVC_RES1 0x0F1Cu
248 #define UWB2_REG_DIAG_TMC 0x0F24u
249 #define UWB2_REG_EVC_CPQE 0x0F28u
250 #define UWB2_REG_EVC_VWARN 0x0F2Au
251 #define UWB2_REG_SPI_MODE 0x0F2Cu
252 #define UWB2_REG_SYS_STATE 0x0F30u
253 #define UWB2_REG_FCMD_STAT 0x0F3Cu
254 #define UWB2_REG_CTR_DBG 0x0F48u
255 #define UWB2_REG_SPICRCINIT 0x0F4Cu
256 #define UWB2_REG_SOFT_RST 0x1100u
257 #define UWB2_REG_CLK_CTRL 0x1104u
258 #define UWB2_REG_SEQ_CTRL 0x1108u
259 #define UWB2_REG_TXFSEQ 0x1112u
260 #define UWB2_REG_LED_CTRL 0x1116u
261 #define UWB2_REG_RX_SNIFF 0x111Au
262 #define UWB2_REG_BIAS_CTRL 0x111Fu
263 #define UWB2_REG_RX_BUFFER_0 0x1200u
264 #define UWB2_REG_RX_BUFFER_1 0x1300u
265 #define UWB2_REG_TX_BUFFER 0x1400u
266 #define UWB2_REG_ACC_MEM 0x1500u
267 #define UWB2_REG_SCRATCH_RAM 0x1600u
268 #define UWB2_REG_AES_KEY_1 0x1700u
269 #define UWB2_REG_AES_KEY_2 0x1710u
270 #define UWB2_REG_AES_KEY_3 0x1720u
271 #define UWB2_REG_AES_KEY_4 0x1730u
272 #define UWB2_REG_AES_KEY_5 0x1740u
273 #define UWB2_REG_AES_KEY_6 0x1750u
274 #define UWB2_REG_AES_KEY_7 0x1760u
275 #define UWB2_REG_AES_KEY_8 0x1770u
276 #define UWB2_REG_SET1_SET2 0x1800u
277 #define UWB2_REG_INDIRECT_PTR_A 0x1D00u
278 #define UWB2_REG_INDIRECT_PTR_B 0x1E00u
279 #define UWB2_REG_FINT_STAT 0x1F00u
280 #define UWB2_REG_PTR_ADDR_A 0x1F04u
281 #define UWB2_REG_PTR_OFFSET_A 0x1F08u
282 #define UWB2_REG_PTR_ADDR_B 0x1F0Cu
283 #define UWB2_REG_PTR_OFFSET_B 0x1F10u
284 
289 #define UWB2_OTP_ADR_EUID_LO 0x0000u
290 #define UWB2_OTP_ADR_EUID_HI 0x0001u
291 #define UWB2_OTP_ADR_AEUID_LO 0x0002u
292 #define UWB2_OTP_ADR_AEUID_HI 0x0003u
293 #define UWB2_OTP_ADR_LDOTUNE_LO 0x0004u
294 #define UWB2_OTP_ADR_LDOTUNE_HI 0x0005u
295 #define UWB2_OTP_ADR_PART_ID 0x0006u
296 #define UWB2_OTP_ADR_LOT_ID 0x0007u
297 #define UWB2_OTP_ADR_VBAT 0x0008u
298 #define UWB2_OTP_ADR_TEMP 0x0009u
299 #define UWB2_OTP_ADR_BIASTUNE 0x000Au
300 #define UWB2_OTP_ADR_ANTENNA_DELAY 0x000Bu
301 #define UWB2_OTP_ADR_AOA_ISO 0x000Cu
302 #define UWB2_OTP_ADR_WS_LOT_ID_LO 0x000Du
303 #define UWB2_OTP_ADR_WS_LOT_ID_HI 0x000Eu
304 #define UWB2_OTP_ADR_WS_LOC 0x000Fu
305 #define UWB2_OTP_ADR_XTAL_TRIM 0x001Eu
306 #define UWB2_OTP_ADR_OTP_REVISION 0x001Fu
307 #define UWB2_OTP_ADR_DGC_TUNE 0x0020u
308 #define UWB2_OTP_ADR_PLL_LOCK_CODE 0x0035u
309 #define UWB2_OTP_ADR_AES_KEY_START 0x0078u
310 #define UWB2_OTP_ADR_AES_KEY_END 0x007Fu
311  // uwb2_reg
313 
328 #define UWB2_SYS_CFG_FAST_AAT_MASK 0x00040000ul
329 #define UWB2_SYS_CFG_PDOA_MODE_MASK 0x00030000ul
330 #define UWB2_SYS_CFG_CP_SDC_SPC_MASK 0x0000B000ul
331 #define UWB2_SYS_CFG_AUTO_ACK_MASK 0x00000800ul
332 #define UWB2_SYS_CFG_RXAUTR_MASK 0x00000400ul
333 #define UWB2_SYS_CFG_RXWTOE_MASK 0x00000200ul
334 #define UWB2_SYS_CFG_CIA_STS_MASK 0x00000100ul
335 #define UWB2_SYS_CFG_CIA_IPATOV_MASK 0x00000080ul
336 #define UWB2_SYS_CFG_SPI_CRCEN_MASK 0x00000040ul
337 #define UWB2_SYS_CFG_PHR_6M8_MASK 0x00000020ul
338 #define UWB2_SYS_CFG_PHR_MODE_MASK 0x00000010ul
339 #define UWB2_SYS_CFG_DIS_DRXB_MASK 0x00000008ul
340 #define UWB2_SYS_CFG_DIS_FCE_MASK 0x00000004ul
341 #define UWB2_SYS_CFG_DIS_FCS_TX_MASK 0x00000002ul
342 #define UWB2_SYS_CFG_FFEN_MASK 0x00000001ul
343 
348 #define UWB2_TX_FCTRL_LO_TXB_OFFSET_MASK 0x03FF0000ul
349 #define UWB2_TX_FCTRL_LO_TXPSR_MASK 0x0000F000ul
350 #define UWB2_TX_FCTRL_LO_TR_MASK 0x00000800ul
351 #define UWB2_TX_FCTRL_LO_TX_BR_MASK 0x00000400ul
352 #define UWB2_TX_FCTRL_LO_TXFLEN_MASK 0x000003FFul
353 
358 #define UWB2_TX_FCTRL_HI_FINE_PLEN_MASK 0xFF00u
359 
364 #define UWB2_SYS_ENABLE_LO_ARFE_EN_MASK 0x20000000ul
365 #define UWB2_SYS_ENABLE_LO_CPERR_EN_MASK 0x10000000ul
366 #define UWB2_SYS_ENABLE_LO_HPDWARN_EN_MASK 0x08000000ul
367 #define UWB2_SYS_ENABLE_LO_RXSTO_EN_MASK 0x04000000ul
368 #define UWB2_SYS_ENABLE_LO_PLLHILO_EN_MASK 0x02000000ul
369 #define UWB2_SYS_ENABLE_LO_RCINIT_EN_MASK 0x01000000ul
370 #define UWB2_SYS_ENABLE_LO_SPIRDY_EN_MASK 0x00800000ul
371 #define UWB2_SYS_ENABLE_LO_RXPTO_EN_MASK 0x00200000ul
372 #define UWB2_SYS_ENABLE_LO_RXOVRR_EN_MASK 0x00100000ul
373 #define UWB2_SYS_ENABLE_LO_VWARN_EN_MASK 0x00080000ul
374 #define UWB2_SYS_ENABLE_LO_CIAERR_EN_MASK 0x00040000ul
375 #define UWB2_SYS_ENABLE_LO_RXFTO_EN_MASK 0x00020000ul
376 #define UWB2_SYS_ENABLE_LO_RXFSL_EN_MASK 0x00010000ul
377 #define UWB2_SYS_ENABLE_LO_RXFCE_EN_MASK 0x00008000ul
378 #define UWB2_SYS_ENABLE_LO_RXFCG_EN_MASK 0x00004000ul
379 #define UWB2_SYS_ENABLE_LO_RXFR_EN_MASK 0x00002000ul
380 #define UWB2_SYS_ENABLE_LO_RXPHE_EN_MASK 0x00001000ul
381 #define UWB2_SYS_ENABLE_LO_RXPHD_EN_MASK 0x00000800ul
382 #define UWB2_SYS_ENABLE_LO_CIADONE_EN_MASK 0x00000400ul
383 #define UWB2_SYS_ENABLE_LO_RXSFDD_EN_MASK 0x00000200ul
384 #define UWB2_SYS_ENABLE_LO_RXPRD_EN_MASK 0x00000100ul
385 #define UWB2_SYS_ENABLE_LO_TXFRS_EN_MASK 0x00000080ul
386 #define UWB2_SYS_ENABLE_LO_TXPHS_EN_MASK 0x00000040ul
387 #define UWB2_SYS_ENABLE_LO_TXPRS_EN_MASK 0x00000020ul
388 #define UWB2_SYS_ENABLE_LO_TXFRB_EN_MASK 0x00000010ul
389 #define UWB2_SYS_ENABLE_LO_AAT_EN_MASK 0x00000008ul
390 #define UWB2_SYS_ENABLE_LO_SPICRCE_EN_MASK 0x00000004ul
391 #define UWB2_SYS_ENABLE_LO_CPLOCK_EN_MASK 0x00000002ul
392 
397 #define UWB2_SYS_STATUS_LO_ARFE_MASK 0x20000000ul
398 #define UWB2_SYS_STATUS_LO_CPERR_MASK 0x10000000ul
399 #define UWB2_SYS_STATUS_LO_HPDWARN_MASK 0x08000000ul
400 #define UWB2_SYS_STATUS_LO_RXSTO_MASK 0x04000000ul
401 #define UWB2_SYS_STATUS_LO_PLLHILO_MASK 0x02000000ul
402 #define UWB2_SYS_STATUS_LO_RCINIT_MASK 0x01000000ul
403 #define UWB2_SYS_STATUS_LO_SPIRDY_MASK 0x00800000ul
404 #define UWB2_SYS_STATUS_LO_RXPTO_MASK 0x00200000ul
405 #define UWB2_SYS_STATUS_LO_RXOVRR_MASK 0x00100000ul
406 #define UWB2_SYS_STATUS_LO_VWARN_MASK 0x00080000ul
407 #define UWB2_SYS_STATUS_LO_CIAERR_MASK 0x00040000ul
408 #define UWB2_SYS_STATUS_LO_RXFTO_MASK 0x00020000ul
409 #define UWB2_SYS_STATUS_LO_RXFSL_MASK 0x00010000ul
410 #define UWB2_SYS_STATUS_LO_RXFCE_MASK 0x00008000ul
411 #define UWB2_SYS_STATUS_LO_RXFCG_MASK 0x00004000ul
412 #define UWB2_SYS_STATUS_LO_RXFR_MASK 0x00002000ul
413 #define UWB2_SYS_STATUS_LO_RXPHE_MASK 0x00001000ul
414 #define UWB2_SYS_STATUS_LO_RXPHD_MASK 0x00000800ul
415 #define UWB2_SYS_STATUS_LO_CIADONE_MASK 0x00000400ul
416 #define UWB2_SYS_STATUS_LO_RXSFDD_MASK 0x00000200ul
417 #define UWB2_SYS_STATUS_LO_RXPRD_MASK 0x00000100ul
418 #define UWB2_SYS_STATUS_LO_TXFRS_MASK 0x00000080ul
419 #define UWB2_SYS_STATUS_LO_TXPHS_MASK 0x00000040ul
420 #define UWB2_SYS_STATUS_LO_TXPRS_MASK 0x00000020ul
421 #define UWB2_SYS_STATUS_LO_TXFRB_MASK 0x00000010ul
422 #define UWB2_SYS_STATUS_LO_AAT_MASK 0x00000008ul
423 #define UWB2_SYS_STATUS_LO_SPICRCE_MASK 0x00000004ul
424 #define UWB2_SYS_STATUS_LO_CPLOCK_MASK 0x00000002ul
425 #define UWB2_SYS_STATUS_LO_IRQS_MASK 0x00000001ul
426 
431 #define UWB2_SYS_STATUS_HI_CCA_FAIL_MASK 0x1000u
432 #define UWB2_SYS_STATUS_HI_SPIERR_MASK 0x0800u
433 #define UWB2_SYS_STATUS_HI_SPI_UNF_MASK 0x0400u
434 #define UWB2_SYS_STATUS_HI_SPI_OVF_MASK 0x0200u
435 #define UWB2_SYS_STATUS_HI_CMD_ERR_MASK 0x0100u
436 #define UWB2_SYS_STATUS_HI_AER_ERR_MASK 0x0080u
437 #define UWB2_SYS_STATUS_HI_AES_DONE_MASK 0x0040u
438 #define UWB2_SYS_STATUS_HI_GPIOIRQ_MASK 0x0020u
439 #define UWB2_SYS_STATUS_HI_VT_DET_MASK 0x0010u
440 #define UWB2_SYS_STATUS_HI_RXPREJ_MASK 0x0002u
441 
446 #define UWB2_CHAN_CTRL_RX_PCODE_MASK 0x1F00u
447 #define UWB2_CHAN_CTRL_TX_PCODE_MASK 0x00F8u
448 #define UWB2_CHAN_CTRL_SFD_TYPE_IEEE_4A 0x0000u
449 #define UWB2_CHAN_CTRL_SFD_TYPE_DW_8 0x0002u
450 #define UWB2_CHAN_CTRL_SFD_TYPE_DW_16 0x0004u
451 #define UWB2_CHAN_CTRL_SFD_TYPE_IEEE_4Z 0x0006u
452 #define UWB2_CHAN_CTRL_SFD_TYPE_MASK 0x0006u
453 #define UWB2_CHAN_CTRL_RF_CHAN_MASK 0x0001u
454 
459 #define UWB2_RX_FINFO_RXPACC_MASK 0xFFF00000ul
460 #define UWB2_RX_FINFO_RXPSR_MASK 0x000C0000ul
461 #define UWB2_RX_FINFO_RXPRF_MASK 0x00030000ul
462 #define UWB2_RX_FINFO_RNG_MASK 0x00008000ul
463 #define UWB2_RX_FINFO_RXBR_MASK 0x00002000ul
464 #define UWB2_RX_FINFO_RXNSPL_MASK 0x00001800ul
465 #define UWB2_RX_FINFO_RXFLEN_MASK 0x000003FFul
466 
471 #define UWB2_STS_CFG_CPS_LEN_64 0x0007u
472 #define UWB2_STS_CFG_CPS_LEN_MASK 0x00FFu
473 #define UWB2_STS_CFG_RESERVED_BITS 0x1000u
474 
479 #define UWB2_RX_TUNE_DGC_CFG_THR_64_OPTIMISED 0x6400u
480 #define UWB2_RX_TUNE_DGC_CFG_THR_64_MASK 0x7E00u
481 #define UWB2_RX_TUNE_DGC_CFG_RX_TUNE_EN_MASK 0x0001u
482 #define UWB2_RX_TUNE_DGC_CFG_RESERVED_BITS 0x80F4u
483 #define UWB2_RX_TUNE_DGC_CFG_0 0x10000240ul
484 #define UWB2_RX_TUNE_DGC_CFG_1 0x1B6DA489ul
485 #define UWB2_RX_TUNE_DGC_LUT_0_CH5 0x0001C0FDul
486 #define UWB2_RX_TUNE_DGC_LUT_0_CH9 0x0002A8FEul
487 #define UWB2_RX_TUNE_DGC_LUT_1_CH5 0x0001C43Eul
488 #define UWB2_RX_TUNE_DGC_LUT_1_CH9 0x0002AC36ul
489 #define UWB2_RX_TUNE_DGC_LUT_2_CH5 0x0001C6BEul
490 #define UWB2_RX_TUNE_DGC_LUT_2_CH9 0x0002A5FEul
491 #define UWB2_RX_TUNE_DGC_LUT_3_CH5 0x0001C77Eul
492 #define UWB2_RX_TUNE_DGC_LUT_3_CH9 0x0002AF3Eul
493 #define UWB2_RX_TUNE_DGC_LUT_4_CH5 0x0001C736ul
494 #define UWB2_RX_TUNE_DGC_LUT_4_CH9 0x0002AF7Dul
495 #define UWB2_RX_TUNE_DGC_LUT_5_CH5 0x0001CFB5ul
496 #define UWB2_RX_TUNE_DGC_LUT_5_CH9 0x0002AFB5ul
497 #define UWB2_RX_TUNE_DGC_LUT_6_CH5 0x0001CFF5ul
498 #define UWB2_RX_TUNE_DGC_LUT_6_CH9 0x0002AFB5ul
499 
504 #define UWB2_RX_CAL_COMP_DLY_EN_READ 0x00010000ul
505 #define UWB2_RX_CAL_COMP_DLY_OPTIMAL 0x00020000ul
506 #define UWB2_RX_CAL_COMP_DLY_MASK 0x000F0000ul
507 #define UWB2_RX_CAL_CAL_EN_MASK 0x00000010ul
508 #define UWB2_RX_CAL_CAL_MODE_NORMAL 0x00000000ul
509 #define UWB2_RX_CAL_CAL_MODE_CALIBRATION 0x00000001ul
510 #define UWB2_RX_CAL_CAL_MODE_MASK 0x00000003ul
511 
516 #define UWB2_RX_CAL_STS_CALIBRATION_DONE 0x01
517 
522 #define UWB2_RX_CAL_RESI_CALIBRATION_FAILED 0x1FFFFFFFul
523 
528 #define UWB2_RX_CAL_RESQ_CALIBRATION_FAILED 0x1FFFFFFFul
529 
534 #define UWB2_GPIO_MODE_MSGP8_GPIO8 0x01000000ul
535 #define UWB2_GPIO_MODE_MSGP8_IRQ 0x00000000ul
536 #define UWB2_GPIO_MODE_MSGP8_MASK 0x07000000ul
537 #define UWB2_GPIO_MODE_MSGP7_GPIO7 0x00200000ul
538 #define UWB2_GPIO_MODE_MSGP7_SYNC 0x00000000ul
539 #define UWB2_GPIO_MODE_MSGP7_MASK 0x00E00000ul
540 #define UWB2_GPIO_MODE_MSGP6_EXTRXE 0x00040000ul
541 #define UWB2_GPIO_MODE_MSGP6_GPIO6 0x00000000ul
542 #define UWB2_GPIO_MODE_MSGP6_MASK 0x001C0000ul
543 #define UWB2_GPIO_MODE_MSGP5_EXTTXE 0x00008000ul
544 #define UWB2_GPIO_MODE_MSGP5_GPIO5 0x00000000ul
545 #define UWB2_GPIO_MODE_MSGP5_MASK 0x00038000ul
546 #define UWB2_GPIO_MODE_MSGP4_IRQ 0x00002000ul
547 #define UWB2_GPIO_MODE_MSGP4_EXTPA 0x00001000ul
548 #define UWB2_GPIO_MODE_MSGP4_GPIO4 0x00000000ul
549 #define UWB2_GPIO_MODE_MSGP4_MASK 0x00007000ul
550 #define UWB2_GPIO_MODE_MSGP3_PDOA_SW_3 0x00000400ul
551 #define UWB2_GPIO_MODE_MSGP3_TXLED 0x00000200ul
552 #define UWB2_GPIO_MODE_MSGP3_GPIO3 0x00000000ul
553 #define UWB2_GPIO_MODE_MSGP3_MASK 0x00000E00ul
554 #define UWB2_GPIO_MODE_MSGP2_PDOA_SW_2 0x00000080ul
555 #define UWB2_GPIO_MODE_MSGP2_RXLED 0x00000040ul
556 #define UWB2_GPIO_MODE_MSGP2_GPIO2 0x00000000ul
557 #define UWB2_GPIO_MODE_MSGP2_MASK 0x000001C0ul
558 #define UWB2_GPIO_MODE_MSGP1_PDOA_SW_1 0x00000010ul
559 #define UWB2_GPIO_MODE_MSGP1_SFDLED 0x00000008ul
560 #define UWB2_GPIO_MODE_MSGP1_GPIO1 0x00000000ul
561 #define UWB2_GPIO_MODE_MSGP1_MASK 0x00000038ul
562 #define UWB2_GPIO_MODE_MSGP0_PDOA_SW_0 0x00000002ul
563 #define UWB2_GPIO_MODE_MSGP0_RXOKLED 0x00000001ul
564 #define UWB2_GPIO_MODE_MSGP0_GPIO0 0x00000000ul
565 #define UWB2_GPIO_MODE_MSGP0_MASK 0x00000007ul
566 
571 #define UWB2_DTUNE_0_DTOB4_MASK 0x0010u
572 #define UWB2_DTUNE_0_PAC_MASK 0x0003u
573 #define UWB2_DTUNE_0_RESERVED_BITS 0x100Cu
574 
579 #define UWB2_RX_SFD_TOC_DEFAULT 0x0081u
580 
585 #define UWB2_DTUNE_3_DEFAULT 0xAF5F584Cul
586 #define UWB2_DTUNE_3_OPTIMAL 0xAF5F35CCul
587 
592 #define UWB2_DTUNE_4_RX_SFD_HLDOFF 0x20000000ul
593 #define UWB2_DTUNE_4_RX_SFD_HLDOFF_DEFAULT 0x14000000ul
594 #define UWB2_DTUNE_4_RX_SFD_HLDOFF_MASK 0xFF000000ul
595 
600 #define UWB2_RF_TX_CTRL_1_OPTIMAL 0x0E
601 
606 #define UWB2_RF_TX_CTRL_2_CHANNEL_5 0x1C071134ul
607 #define UWB2_RF_TX_CTRL_2_CHANNEL_9 0x1C010034ul
608 
613 #define UWB2_LDO_CTRL_VDDHVTX_VREF_MASK 0x08000000ul
614 #define UWB2_LDO_CTRL_VDDTX2_VREF_MASK 0x00400000ul
615 #define UWB2_LDO_CTRL_VDDTX1_VREF_MASK 0x00200000ul
616 #define UWB2_LDO_CTRL_VDDHVTX_EN_MASK 0x00000800ul
617 #define UWB2_LDO_CTRL_VDDIF2_EN_MASK 0x00000100ul
618 #define UWB2_LDO_CTRL_VDDTX2_EN_MASK 0x00000040ul
619 #define UWB2_LDO_CTRL_VDDTX1_EN_MASK 0x00000020ul
620 #define UWB2_LDO_CTRL_VDDPLL_EN_MASK 0x00000010ul
621 #define UWB2_LDO_CTRL_VDDMS3_EN_MASK 0x00000004ul
622 #define UWB2_LDO_CTRL_VDDMS2_EN_MASK 0x00000002ul
623 #define UWB2_LDO_CTRL_VDDMS1_EN_MASK 0x00000001ul
624 
629 #define UWB2_LDO_RLOAD_OPTIMAL 0x14
630 
635 #define UWB2_PLL_CFG_CHANNEL_5 0x1F3Cu
636 #define UWB2_PLL_CFG_CHANNEL_9 0x0F3Cu
637 
642 #define UWB2_PLL_CAL_CAL_EN_MASK 0x0100u
643 #define UWB2_PLL_CAL_PLL_CFG_LD_MASK 0x0030u
644 #define UWB2_PLL_CAL_USE_OLD_MASK 0x0002u
645 #define UWB2_PLL_CAL_RESERVED_BITS 0x0001u
646 #define UWB2_PLL_CAL_OPTIMAL 0x0081u
647 
652 #define UWB2_XTAL_TRIM_DEFAULT 0x2E
653 #define UWB2_XTAL_TRIM_MASK 0x3F
654 
659 #define UWB2_OTP_CFG_DGC_SEL_MASK 0x2000u
660 #define UWB2_OTP_CFG_OPS_SEL_LONG 0x0000u
661 #define UWB2_OTP_CFG_OPS_SEL_SHORT 0x1000u
662 #define UWB2_OTP_CFG_OPS_SEL_MASK 0x1800u
663 #define UWB2_OTP_CFG_OPS_KICK_MASK 0x0400u
664 #define UWB2_OTP_CFG_BIAS_KICK_MASK 0x0100u
665 #define UWB2_OTP_CFG_LDO_KICK_MASK 0x0080u
666 #define UWB2_OTP_CFG_DGC_KICK_MASK 0x0040u
667 #define UWB2_OTP_CFG_OTP_WRITE_MR_MASK 0x0008u
668 #define UWB2_OTP_CFG_OTP_WRITE_MASK 0x0004u
669 #define UWB2_OTP_CFG_OTP_READ_MASK 0x0002u
670 #define UWB2_OTP_CFG_OTP_MAN_MASK 0x0001u
671 
676 #define UWB2_STS_CONF_1_STS_PGR_EN_MASK 0x80000000ul
677 #define UWB2_STS_CONF_1_STS_SS_EN_MASK 0x40000000ul
678 #define UWB2_STS_CONF_1_STS_CQ_EN_MASK 0x20000000ul
679 #define UWB2_STS_CONF_1_FP_AGREED_EN_MASK 0x10000000ul
680 #define UWB2_STS_CONF_1_RES_B0_DEFAULT 0x00000094ul
681 #define UWB2_STS_CONF_1_RES_B0_MASK 0x000000FFul
682 #define UWB2_STS_CONF_1_RESERVED_BITS 0x003EED00ul
683 
688 #define UWB2_DIAG_TMC_CIA_RUN_MASK 0x04000000ul
689 #define UWB2_DIAG_TMC_CIA_WDEN_MASK 0x01000000ul
690 #define UWB2_DIAG_TMC_HIRQ_POL_MASK 0x00200000ul
691 #define UWB2_DIAG_TMC_TX_PSTM_MASK 0x00000010ul
692 
697 #define UWB2_SYS_STATE_PMSC_STATE_WAKEUP 0x00000000ul
698 #define UWB2_SYS_STATE_PMSC_STATE_IDLE_RC 0x00010000ul
699 #define UWB2_SYS_STATE_PMSC_STATE_IDLE 0x00030000ul
700 #define UWB2_SYS_STATE_PMSC_STATE_TX 0x00080000ul
701 #define UWB2_SYS_STATE_PMSC_STATE_RX 0x00120000ul
702 #define UWB2_SYS_STATE_PMSC_STATE_MASK 0x001F0000ul
703 #define UWB2_SYS_STATE_RX_STATE_IDLE 0x00000000ul
704 #define UWB2_SYS_STATE_RX_STATE_START_ANALOG 0x00000100ul
705 #define UWB2_SYS_STATE_RX_STATE_RX_RDY 0x00000400ul
706 #define UWB2_SYS_STATE_RX_STATE_PREAMBLE_FND 0x00000500ul
707 #define UWB2_SYS_STATE_RX_STATE_PREAMBLE_TO 0x00000600ul
708 #define UWB2_SYS_STATE_RX_STATE_SFD_FND 0x00000700ul
709 #define UWB2_SYS_STATE_RX_STATE_CNFG_PHR_RX 0x00000800ul
710 #define UWB2_SYS_STATE_RX_STATE_PHR_RX_STRT 0x00000900ul
711 #define UWB2_SYS_STATE_RX_STATE_DATA_RATE_RDY 0x00000A00ul
712 #define UWB2_SYS_STATE_RX_STATE_DATA_RX_SEQ 0x00000C00ul
713 #define UWB2_SYS_STATE_RX_STATE_CNFG_DATA_RX 0x00000D00ul
714 #define UWB2_SYS_STATE_RX_STATE_PHR_NOT_OK 0x00000E00ul
715 #define UWB2_SYS_STATE_RX_STATE_LAST_SYMBOL 0x00000F00ul
716 #define UWB2_SYS_STATE_RX_STATE_WAIT_RSD_DONE 0x00001000ul
717 #define UWB2_SYS_STATE_RX_STATE_RSP_OK 0x00001100ul
718 #define UWB2_SYS_STATE_RX_STATE_RSP_NOT_OK 0x00001200ul
719 #define UWB2_SYS_STATE_RX_STATE_MASK 0x00003F00ul
720 #define UWB2_SYS_STATE_TX_STATE_IDLE 0x00000000ul
721 #define UWB2_SYS_STATE_TX_STATE_PREAMBLE 0x00000001ul
722 #define UWB2_SYS_STATE_TX_STATE_SFD 0x00000002ul
723 #define UWB2_SYS_STATE_TX_STATE_PHR 0x00000003ul
724 #define UWB2_SYS_STATE_TX_STATE_SDE 0x00000004ul
725 #define UWB2_SYS_STATE_TX_STATE_DATA 0x00000005ul
726 #define UWB2_SYS_STATE_TX_STATE_MASK 0x0000000Ful
727 
732 #define UWB2_CLK_CTRL_LP_CLK_EN_MASK 0x00800000ul
733 #define UWB2_CLK_CTRL_GPIO_DRST_N_MASK 0x00080000ul
734 #define UWB2_CLK_CTRL_GPIO_DCLK_EN_MASK 0x00040000ul
735 #define UWB2_CLK_CTRL_GPIO_CLK_EN_MASK 0x00010000ul
736 #define UWB2_CLK_CTRL_ACC_MCLK_EN_MASK 0x00008000ul
737 #define UWB2_CLK_CTRL_SAR_CLK_EN_MASK 0x00000400ul
738 #define UWB2_CLK_CTRL_CIA_CLK_EN_MASK 0x00000100ul
739 #define UWB2_CLK_CTRL_ACC_CLK_EN_MASK 0x00000040ul
740 #define UWB2_CLK_CTRL_TX_CLK_AUTO 0x00000000ul
741 #define UWB2_CLK_CTRL_TX_CLK_FORCE 0x00000010ul
742 #define UWB2_CLK_CTRL_TX_CLK_MASK 0x00000030ul
743 #define UWB2_CLK_CTRL_RX_CLK_AUTO 0x00000000ul
744 #define UWB2_CLK_CTRL_RX_CLK_FORCE 0x00000004ul
745 #define UWB2_CLK_CTRL_RX_CLK_MASK 0x0000000Cul
746 #define UWB2_CLK_CTRL_SYS_CLK_AUTO 0x00000000ul
747 #define UWB2_CLK_CTRL_SYS_CLK_FORCE_FC_4 0x00000001ul
748 #define UWB2_CLK_CTRL_SYS_CLK_FORCE_PLL 0x00000002ul
749 #define UWB2_CLK_CTRL_SYS_CLK_FORCE_FC 0x00000003ul
750 #define UWB2_CLK_CTRL_SYS_CLK_MASK 0x00000003ul
751 #define UWB2_CLK_CTRL_RESERVED_BITS 0xF0300200ul
752 
757 #define UWB2_SEQ_CTRL_LP_CLK_DIV_MASK 0xFC000000ul
758 #define UWB2_SEQ_CTRL_FORCE2INIT_MASK 0x00800000ul
759 #define UWB2_SEQ_CTRL_CIARUNE_MASK 0x00020000ul
760 #define UWB2_SEQ_CTRL_PLL_SYNC_MASK 0x00008000ul
761 #define UWB2_SEQ_CTRL_ARXSLP_MASK 0x00001000ul
762 #define UWB2_SEQ_CTRL_ATXSLP_MASK 0x00000800ul
763 #define UWB2_SEQ_CTRL_AINIT2IDLE_MASK 0x00000100ul
764 #define UWB2_SEQ_CTRL_RESERVED_BITS 0x00010638ul
765 
770 #define UWB2_LED_CTRL_FORCE_TRIG_MASK 0x000F0000ul
771 #define UWB2_LED_CTRL_BLINK_EN_MASK 0x00000100ul
772 #define UWB2_LED_CTRL_BLINK_TIM_200MS 0x00000010ul
773 #define UWB2_LED_CTRL_BLINK_TIM_400MS 0x00000020ul
774 #define UWB2_LED_CTRL_BLINK_TIM_MASK 0x000000FFul
775 
780 #define UWB2_BIAS_CTRL_MASK 0x1F
781 
786 #define UWB2_CHANNEL_5 0x05
787 #define UWB2_CHANNEL_9 0x09
788 #define UWB2_TX_PLEN_32 0x04
789 #define UWB2_TX_PLEN_64 0x01
790 #define UWB2_TX_PLEN_128 0x05
791 #define UWB2_TX_PLEN_256 0x09
792 #define UWB2_TX_PLEN_512 0x0D
793 #define UWB2_TX_PLEN_1024 0x02
794 #define UWB2_TX_PLEN_1536 0x06
795 #define UWB2_TX_PLEN_2048 0x0A
796 #define UWB2_TX_PLEN_4096 0x03
797 #define UWB2_PAC_SIZE_4 0x03
798 #define UWB2_PAC_SIZE_8 0x00
799 #define UWB2_PAC_SIZE_16 0x01
800 #define UWB2_PAC_SIZE_32 0x02
801 #define UWB2_TX_CODE_MIN 0x01
802 #define UWB2_TX_CODE_9 0x09
803 #define UWB2_TX_CODE_24 0x18
804 #define UWB2_TX_CODE_MAX 0x1D
805 #define UWB2_RX_CODE_MIN 0x01
806 #define UWB2_RX_CODE_9 0x09
807 #define UWB2_RX_CODE_24 0x18
808 #define UWB2_RX_CODE_MAX 0x1D
809 #define UWB2_SFD_TYPE_IEEE_4A 0x00
810 #define UWB2_SFD_TYPE_DW_8 0x01
811 #define UWB2_SFD_TYPE_DW_16 0x02
812 #define UWB2_SFD_TYPE_IEEE_4Z 0x03
813 #define UWB2_DATA_RATE_850KBS 0x00
814 #define UWB2_DATA_RATE_6800KBS 0x01
815 
820 #define UWB2_DEFAULT_CHANNEL UWB2_CHANNEL_5
821 #define UWB2_DEFAULT_TX_PLEN UWB2_TX_PLEN_128
822 #define UWB2_DEFAULT_PAC UWB2_PAC_SIZE_8
823 #define UWB2_DEFAULT_TX_CODE UWB2_TX_CODE_9
824 #define UWB2_DEFAULT_RX_CODE UWB2_RX_CODE_9
825 #define UWB2_DEFAULT_SFD_TYPE UWB2_SFD_TYPE_DW_8
826 #define UWB2_DEFAULT_DATA_RATE UWB2_DATA_RATE_6800KBS
827 #define UWB2_DEFAULT_SFD_TO ( 128 + 1 + 8 - 8 ) // preamble length + 1 + SFD length - PAC size.
828 
833 #define UWB2_RX_TX_LEDS_DISABLE 0
834 #define UWB2_RX_TX_LEDS_ENABLE 1
835 
840 #define UWB2_IC_STATE_INIT 0
841 #define UWB2_IC_STATE_IDLE 1
842 #define UWB2_IC_STATE_IDLE_RC 2
843 
848 #define UWB2_DEV_ID 0xDECA0302ul
849 #define UWB2_DEV_ID_RIDTAG_MASK 0xFFFF0000ul
850 #define UWB2_DEV_ID_MODEL_MASK 0x0000FF00ul
851 #define UWB2_DEV_ID_VER_MASK 0x000000F0ul
852 #define UWB2_DEV_ID_REV_MASK 0x0000000Ful
853 
858 #define UWB2_MASK_ALL_32 0xFFFFFFFFul
859 #define UWB2_MASK_NONE_32 0x00000000ul
860 #define UWB2_MASK_ALL_16 0xFFFFu
861 #define UWB2_MASK_NONE_16 0x0000u
862 #define UWB2_MASK_ALL_8 0xFF
863 #define UWB2_MASK_NONE_8 0x00
864 
869 #define UWB2_SPI_WRITE 0x8000u
870 #define UWB2_SPI_16BIT_ADDR 0x4000u
871 #define UWB2_SPI_FAST_CMD 0x0100u
872 #define UWB2_SPI_MASKED_WRITE_8BIT 0x0001u
873 #define UWB2_SPI_MASKED_WRITE_16BIT 0x0002u
874 #define UWB2_SPI_MASKED_WRITE_32BIT 0x0003u
875 #define UWB2_SPI_BASE_ADDR_MASK 0x3E00u
876 #define UWB2_SPI_SUB_ADDR_MASK 0x01FCu
877 #define UWB2_SPI_MODE_MASK 0x0003u
878 
883 #define UWB2_WAIT_TIMEOUT_MS 5000u
884 
893 #define UWB2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
894 #define UWB2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE
895  // uwb2_set
897 
912 #define UWB2_MAP_MIKROBUS( cfg, mikrobus ) \
913  cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
914  cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
915  cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
916  cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
917  cfg.wup = MIKROBUS( mikrobus, MIKROBUS_AN ); \
918  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
919  cfg.ext = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
920  cfg.irq = MIKROBUS( mikrobus, MIKROBUS_INT )
921  // uwb2_map // uwb2
924 
929 typedef struct
930 {
931  uint8_t channel;
932  uint8_t tx_plen;
933  uint8_t pac;
934  uint8_t tx_code;
935  uint8_t rx_code;
936  uint8_t sfd_type;
937  uint8_t data_rate;
938  uint16_t sfd_to;
941 
946 typedef struct
947 {
948  // Output pins
949  digital_out_t wup;
950  digital_out_t rst;
952  // Input pins
953  digital_in_t ext;
954  digital_in_t irq;
956  // Modules
957  spi_master_t spi;
959  pin_name_t chip_select;
961 } uwb2_t;
962 
967 typedef struct
968 {
969  // Communication gpio pins
970  pin_name_t miso;
971  pin_name_t mosi;
972  pin_name_t sck;
973  pin_name_t cs;
975  // Additional gpio pins
976  pin_name_t wup;
977  pin_name_t rst;
978  pin_name_t ext;
979  pin_name_t irq;
981  // static variable
982  uint32_t spi_speed;
983  spi_master_mode_t spi_mode;
984  spi_master_chip_select_polarity_t cs_polarity;
986 } uwb2_cfg_t;
987 
992 typedef enum
993 {
994  UWB2_OK = 0,
995  UWB2_ERROR = -1
996 
998 
1015 
1029 err_t uwb2_init ( uwb2_t *ctx, uwb2_cfg_t *cfg );
1030 
1043 err_t uwb2_default_cfg ( uwb2_t *ctx );
1044 
1056 err_t uwb2_send_cmd ( uwb2_t *ctx, uint8_t cmd );
1057 
1072 err_t uwb2_read_reg ( uwb2_t *ctx, uint16_t reg, uint8_t *data_out, uint16_t len );
1073 
1088 err_t uwb2_write_reg ( uwb2_t *ctx, uint16_t reg, uint8_t *data_in, uint16_t len );
1089 
1102 err_t uwb2_read_reg_8bit ( uwb2_t *ctx, uint16_t reg, uint8_t *data_out );
1103 
1116 err_t uwb2_read_reg_16bit ( uwb2_t *ctx, uint16_t reg, uint16_t *data_out );
1117 
1130 err_t uwb2_read_reg_32bit ( uwb2_t *ctx, uint16_t reg, uint32_t *data_out );
1131 
1144 err_t uwb2_write_reg_8bit ( uwb2_t *ctx, uint16_t reg, uint8_t data_in );
1145 
1158 err_t uwb2_write_reg_16bit ( uwb2_t *ctx, uint16_t reg, uint16_t data_in );
1159 
1172 err_t uwb2_write_reg_32bit ( uwb2_t *ctx, uint16_t reg, uint32_t data_in );
1173 
1187 err_t uwb2_modify_reg_8bit ( uwb2_t *ctx, uint16_t reg, uint8_t and_mask, uint8_t or_mask );
1188 
1202 err_t uwb2_modify_reg_16bit ( uwb2_t *ctx, uint16_t reg, uint16_t and_mask, uint16_t or_mask );
1203 
1217 err_t uwb2_modify_reg_32bit ( uwb2_t *ctx, uint16_t reg, uint32_t and_mask, uint32_t or_mask );
1218 
1232 err_t uwb2_read_otp ( uwb2_t *ctx, uint16_t address, uint32_t *data_out, uint16_t len );
1233 
1243 void uwb2_set_rst_pin ( uwb2_t *ctx, uint8_t state );
1244 
1254 void uwb2_set_wup_pin ( uwb2_t *ctx, uint8_t state );
1255 
1264 uint8_t uwb2_get_ext_pin ( uwb2_t *ctx );
1265 
1274 uint8_t uwb2_get_irq_pin ( uwb2_t *ctx );
1275 
1285 
1297 
1309 err_t uwb2_power_up_ic ( uwb2_t *ctx );
1310 
1324 
1337 err_t uwb2_configure_ic ( uwb2_t *ctx, uwb2_chip_cfg_t *config );
1338 
1353 err_t uwb2_set_ic_state ( uwb2_t *ctx, uint8_t state );
1354 
1368 err_t uwb2_load_ic_rx_lut ( uwb2_t *ctx, uint8_t channel );
1369 
1382 
1397 err_t uwb2_set_rx_tx_leds ( uwb2_t *ctx, uint8_t mode );
1398 
1412 err_t uwb2_wait_for_status_lo ( uwb2_t *ctx, uint32_t status );
1413 
1424 err_t uwb2_clear_status ( uwb2_t *ctx );
1425 
1439 err_t uwb2_send_message ( uwb2_t *ctx, uint8_t *data_in, uint16_t len );
1440 
1456 err_t uwb2_read_message ( uwb2_t *ctx, uint8_t *data_out, uint16_t *len );
1457 
1458 #ifdef __cplusplus
1459 }
1460 #endif
1461 #endif // UWB2_H
1462  // uwb2
1464 
1465 // ------------------------------------------------------------------------ END
uwb2_modify_reg_32bit
err_t uwb2_modify_reg_32bit(uwb2_t *ctx, uint16_t reg, uint32_t and_mask, uint32_t or_mask)
UWB 2 modify register 32bit function.
uwb2_read_reg_32bit
err_t uwb2_read_reg_32bit(uwb2_t *ctx, uint16_t reg, uint32_t *data_out)
UWB 2 read register 32bit function.
uwb2_get_ext_pin
uint8_t uwb2_get_ext_pin(uwb2_t *ctx)
UWB 2 get ext pin function.
uwb2_power_up_ic
err_t uwb2_power_up_ic(uwb2_t *ctx)
UWB 2 power up IC function.
uwb2_chip_cfg_t
UWB 2 Click chip configuration object.
Definition: uwb2.h:930
uwb2_t::irq
digital_in_t irq
Definition: uwb2.h:954
uwb2_send_cmd
err_t uwb2_send_cmd(uwb2_t *ctx, uint8_t cmd)
UWB 2 send cmd function.
uwb2_t::chip_select
pin_name_t chip_select
Definition: uwb2.h:959
uwb2_cfg_setup
void uwb2_cfg_setup(uwb2_cfg_t *cfg)
UWB 2 configuration object setup function.
spi_specifics.h
This file contains SPI specific macros, functions, etc.
uwb2_send_message
err_t uwb2_send_message(uwb2_t *ctx, uint8_t *data_in, uint16_t len)
UWB 2 send message function.
uwb2_write_reg_8bit
err_t uwb2_write_reg_8bit(uwb2_t *ctx, uint16_t reg, uint8_t data_in)
UWB 2 write register 8bit function.
uwb2_cfg_t::ext
pin_name_t ext
Definition: uwb2.h:978
uwb2_read_otp
err_t uwb2_read_otp(uwb2_t *ctx, uint16_t address, uint32_t *data_out, uint16_t len)
UWB 2 read otp function.
uwb2_calibrate_ic_pgf
err_t uwb2_calibrate_ic_pgf(uwb2_t *ctx)
UWB 2 calibrate IC PGF function.
uwb2_chip_cfg_t::sfd_to
uint16_t sfd_to
Definition: uwb2.h:938
uwb2_clear_status
err_t uwb2_clear_status(uwb2_t *ctx)
UWB 2 clear status function.
uwb2_t::wup
digital_out_t wup
Definition: uwb2.h:949
uwb2_chip_cfg_t::sfd_type
uint8_t sfd_type
Definition: uwb2.h:936
uwb2_modify_reg_16bit
err_t uwb2_modify_reg_16bit(uwb2_t *ctx, uint16_t reg, uint16_t and_mask, uint16_t or_mask)
UWB 2 modify register 16bit function.
uwb2_cfg_t::miso
pin_name_t miso
Definition: uwb2.h:970
UWB2_ERROR
@ UWB2_ERROR
Definition: uwb2.h:995
uwb2_set_rx_tx_leds
err_t uwb2_set_rx_tx_leds(uwb2_t *ctx, uint8_t mode)
UWB 2 set RX TX LEDs function.
uwb2_cfg_t::mosi
pin_name_t mosi
Definition: uwb2.h:971
uwb2_write_reg
err_t uwb2_write_reg(uwb2_t *ctx, uint16_t reg, uint8_t *data_in, uint16_t len)
UWB 2 write register function.
uwb2_cfg_t::cs_polarity
spi_master_chip_select_polarity_t cs_polarity
Definition: uwb2.h:984
uwb2_initialize_ic
err_t uwb2_initialize_ic(uwb2_t *ctx)
UWB 2 initialize IC function.
uwb2_read_message
err_t uwb2_read_message(uwb2_t *ctx, uint8_t *data_out, uint16_t *len)
UWB 2 read message function.
uwb2_load_ic_rx_lut
err_t uwb2_load_ic_rx_lut(uwb2_t *ctx, uint8_t channel)
UWB 2 load IC RX lut function.
uwb2_get_irq_pin
uint8_t uwb2_get_irq_pin(uwb2_t *ctx)
UWB 2 get irq pin function.
uwb2_t
UWB 2 Click context object.
Definition: uwb2.h:947
uwb2_read_reg_8bit
err_t uwb2_read_reg_8bit(uwb2_t *ctx, uint16_t reg, uint8_t *data_out)
UWB 2 read register 8bit function.
uwb2_reset_device
void uwb2_reset_device(uwb2_t *ctx)
UWB 2 reset device function.
uwb2_cfg_t::sck
pin_name_t sck
Definition: uwb2.h:972
uwb2_cfg_t::spi_speed
uint32_t spi_speed
Definition: uwb2.h:982
uwb2_read_reg
err_t uwb2_read_reg(uwb2_t *ctx, uint16_t reg, uint8_t *data_out, uint16_t len)
UWB 2 read register function.
uwb2_write_reg_16bit
err_t uwb2_write_reg_16bit(uwb2_t *ctx, uint16_t reg, uint16_t data_in)
UWB 2 write register 16bit function.
uwb2_set_wup_pin
void uwb2_set_wup_pin(uwb2_t *ctx, uint8_t state)
UWB 2 set wup pin function.
uwb2_cfg_t::wup
pin_name_t wup
Definition: uwb2.h:976
uwb2_chip_cfg_t::pac
uint8_t pac
Definition: uwb2.h:933
uwb2_default_cfg
err_t uwb2_default_cfg(uwb2_t *ctx)
UWB 2 default configuration function.
uwb2_return_value_t
uwb2_return_value_t
UWB 2 Click return value data.
Definition: uwb2.h:993
uwb2_set_ic_state
err_t uwb2_set_ic_state(uwb2_t *ctx, uint8_t state)
UWB 2 set IC state function.
uwb2_t::spi
spi_master_t spi
Definition: uwb2.h:957
uwb2_chip_cfg_t::rx_code
uint8_t rx_code
Definition: uwb2.h:935
uwb2_cfg_t::irq
pin_name_t irq
Definition: uwb2.h:979
uwb2_cfg_t::spi_mode
spi_master_mode_t spi_mode
Definition: uwb2.h:983
uwb2_chip_cfg_t::tx_code
uint8_t tx_code
Definition: uwb2.h:934
uwb2_check_communication
err_t uwb2_check_communication(uwb2_t *ctx)
UWB 2 check communication function.
uwb2_t::rst
digital_out_t rst
Definition: uwb2.h:950
uwb2_modify_reg_8bit
err_t uwb2_modify_reg_8bit(uwb2_t *ctx, uint16_t reg, uint8_t and_mask, uint8_t or_mask)
UWB 2 modify register 8bit function.
uwb2_chip_cfg_t::data_rate
uint8_t data_rate
Definition: uwb2.h:937
uwb2_configure_ic
err_t uwb2_configure_ic(uwb2_t *ctx, uwb2_chip_cfg_t *config)
UWB 2 configure IC function.
uwb2_chip_cfg_t::tx_plen
uint8_t tx_plen
Definition: uwb2.h:932
uwb2_chip_cfg_t::channel
uint8_t channel
Definition: uwb2.h:931
uwb2_cfg_t
UWB 2 Click configuration object.
Definition: uwb2.h:968
uwb2_init
err_t uwb2_init(uwb2_t *ctx, uwb2_cfg_t *cfg)
UWB 2 initialization function.
uwb2_cfg_t::rst
pin_name_t rst
Definition: uwb2.h:977
UWB2_OK
@ UWB2_OK
Definition: uwb2.h:994
uwb2_cfg_t::cs
pin_name_t cs
Definition: uwb2.h:973
uwb2_wait_for_status_lo
err_t uwb2_wait_for_status_lo(uwb2_t *ctx, uint32_t status)
UWB 2 wait for status lo function.
uwb2_read_reg_16bit
err_t uwb2_read_reg_16bit(uwb2_t *ctx, uint16_t reg, uint16_t *data_out)
UWB 2 read register 16bit function.
uwb2_write_reg_32bit
err_t uwb2_write_reg_32bit(uwb2_t *ctx, uint16_t reg, uint32_t data_in)
UWB 2 write register 32bit function.
uwb2_t::ext
digital_in_t ext
Definition: uwb2.h:953
uwb2_set_rst_pin
void uwb2_set_rst_pin(uwb2_t *ctx, uint8_t state)
UWB 2 set rst pin function.