ecggsr  2.0.0.0
ecggsr.h
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44 // ----------------------------------------------------------------------------
45 
46 #ifndef _ECGGSR_H_
47 #define _ECGGSR_H_
48 
49 #ifdef __cplusplus
50 extern "C"{
51 #endif
52 
53 #include "drv_digital_out.h"
54 #include "drv_digital_in.h"
55 #include "drv_i2c_master.h"
56 
57 // -------------------------------------------------------------- PUBLIC MACROS
58 
79 #define ECGGSR_SLAVE_ADDRESS 0x30
80  // ecggsr_cfg
81 
92 #define ECGGSR_MAP_MIKROBUS( cfg, mikrobus ) \
93  cfg.scl_pin = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
94  cfg.sda_pin = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
95  cfg.enable_pin = MIKROBUS( mikrobus, MIKROBUS_CS );
96 
97  // ecggsr_map
99  // ecggsr
101 
102 
107 #define ECGGSR_RETVAL uint8_t
108 
114 #define ECGGSR_GPIO_SYNC_REG 0x0F
115 #define ECGGSR_LED_CFG_REG 0x10
116 #define ECGGSR_LED_WAIT_LOW_REG 0x11
117 #define ECGGSR_LED1_CURRL_REG 0x12
118 #define ECGGSR_LED1_CURRH_REG 0x13
119 #define ECGGSR_LED2_CURRL_REG 0x14
120 #define ECGGSR_LED2_CURRH_REG 0x15
121 #define ECGGSR_LED3_CURRL_REG 0x16
122 #define ECGGSR_LED3_CURRH_REG 0x17
123 #define ECGGSR_LED4_CURRL_REG 0x18
124 #define ECGGSR_LED4_CURRH_REG 0x19
125 #define ECGGSR_LED12_MODE_REG 0x2C
126 #define ECGGSR_LED34_MODE_REG 0x2D
127 #define ECGGSR_MAN_SEQ_CFG_REG 0x2E
128 #define ECGGSR_PD_CFG_REG 0x1A
129 #define ECGGSR_PDOFFX_LEDOFF_REG 0x1B
130 #define ECGGSR_PDOFFX_LEDON_REG 0x1C
131 #define ECGGSR_PD_AMPRCCFG_REG 0x1D
132 #define ECGGSR_PD_AMPCFG_REG 0x1E
133 #define ECGGSR_OFE1_PD_THCFG_REG 0x1F
134 #define ECGGSR_SEQ_CNT_REG 0x30
135 #define ECGGSR_SEQ_DIV_REG 0x31
136 #define ECGGSR_SEQ_START_REG 0x32
137 #define ECGGSR_SEQ_PER_REG 0x33
138 #define ECGGSR_SEQ_LED_ST_REG 0x34
139 #define ECGGSR_SEQ_LED_STO_REG 0x35
140 #define ECGGSR_SEQ_SECLED_STA_REG 0x36
141 #define ECGGSR_SEQ_SECLED_STO_REG 0x37
142 #define ECGGSR_SEQ_ITG_STA_REG 0x38
143 #define ECGGSR_SEQ_ITG_STO_REG 0x39
144 #define ECGGSR_SEQ_SDP1_STA_REG 0x3A
145 #define ECGGSR_SEQ_SDP1_STO_REG 0x3B
146 #define ECGGSR_SEQ_SDP2_STA_REG 0x3C
147 #define ECGGSR_SEQ_SDP2_STO_REG 0x3D
148 #define ECGGSR_SEQ_SDM1_STA_REG 0x3E
149 #define ECGGSR_SEQ_SDM1_STO_REG 0x3F
150 #define ECGGSR_SEQ_SDM2_STA_REG 0x40
151 #define ECGGSR_SEQ_SDM2_STO_REG 0x41
152 #define ECGGSR_SEQ_ADC_REG 0x42
153 #define ECGGSR_SEQ_ADC2TIA_REG 0x43
154 #define ECGGSR_SEQ_ADC3TIA_REG 0x44
155 #define ECGGSR_SD_SUBS_REG 0x45
156 #define ECGGSR_SEQ_CFG_REG 0x46
157 #define ECGGSR_SEQ_ERR_REG 0x47
158 #define ECGGSR_SEQ_OVS_SEL_REG 0x48
159 #define ECGGSR_SEQ_OVS_VAL_REG 0x49
160 #define ECGGSR_SEQ_DIS_SEL_REG 0x4A
161 #define ECGGSR_SEQ_DIS_VAL1_REG 0x4B
162 #define ECGGSR_SEQ_DIS_VAL2_REG 0x4C
163 #define ECGGSR_CYC_COUNTER_REG 0x60
164 #define ECGGSR_SEQ_COUNTER_REG 0x61
165 #define ECGGSR_SUBS_COUNTER_REG 0x62
166 #define ECGGSR_OFE_CFGA_REG 0x50
167 #define ECGGSR_OFE1_SD_THCFG_REG 0x51
168 #define ECGGSR_OFE_CFGC_REG 0x52
169 #define ECGGSR_OFE_CFGD_REG 0x53
170 #define ECGGSR_OFE1_CFGA_REG 0x54
171 #define ECGGSR_OFE1_CFGB_REG 0x55
172 #define ECGGSR_OFE2_PD_THCFG_REG 0x56
173 #define ECGGSR_OFE2_SD_THCFG_REG 0x57
174 #define ECGGSR_OFE2_CFGA_REG 0x58
175 #define ECGGSR_OFE2_CFGB_REG 0x59
176 #define ECGGSR_LTFDATA0_L_REG 0x20
177 #define ECGGSR_LTFDATA0_H_REG 0x21
178 #define ECGGSR_LTFDATA1_L_REG 0x22
179 #define ECGGSR_LTFDATA1_H_REG 0x23
180 #define ECGGSR_ITIME_REG 0x24
181 #define ECGGSR_LTF_CONFIG_REG 0x25
182 #define ECGGSR_LTF_SEL_REG 0x26
183 #define ECGGSR_LTF_GAIN_REG 0x27
184 #define ECGGSR_LTF_CONTROL_REG 0x28
185 #define ECGGSR_AZ_CONTROL_REG 0x29
186 #define ECGGSR_OFFSET0_REG 0x2A
187 #define ECGGSR_OFFSET1_REG 0x2B
188 #define ECGGSR_LTF_THRESHOLD_LOW0_REG 0x6C
189 #define ECGGSR_LTF_THRESHOLD_LOW1_REG 0x6D
190 #define ECGGSR_LTF_THRESHOLD_HIGH0_REG 0x6E
191 #define ECGGSR_LTF_THRESHOLD_HIGH1_REG 0x6F
192 #define ECGGSR_EAF_CFG_REG 0x70
193 #define ECGGSR_EAF_GST_REG 0x80
194 #define ECGGSR_EAF_BIAS_REG 0x81
195 #define ECGGSR_EAF_DAC_REG 0x82
196 #define ECGGSR_EAF_DAC1_L_REG 0x83
197 #define ECGGSR_EAF_DAC1_H_REG 0x84
198 #define ECGGSR_EAF_DAC2_L_REG 0x85
199 #define ECGGSR_EAF_DAC2_H_REG 0x86
200 #define ECGGSR_EAF_DAC_CFG_REG 0x87
201 #define ECGGSR_OFE_NOTCH_REG 0x5A
202 #define ECGGSR_ECG_MODE_REG 0x5B
203 #define ECGGSR_ECG_CFGA_REG 0x5C
204 #define ECGGSR_ECG_CFGB_REG 0x5D
205 #define ECGGSR_ECG_THRESHOLD_LOW_REG 0x6A
206 #define ECGGSR_ECG_THRESHOLD_HIGH_REG 0x6B
207 #define ECGGSR_ECG_CFGC_REG 0x5E
208 #define ECGGSR_ECG_CFGD_REG 0x5F
209 #define ECGGSR_ADC_THRESHOLD_REG 0x68
210 #define ECGGSR_ADC_THRESHOLD_CFG_REG 0x69
211 #define ECGGSR_ADC_CFGA_REG 0x88
212 #define ECGGSR_ADC_CFGB_REG 0x89
213 #define ECGGSR_ADC_CFGC_REG 0x8A
214 #define ECGGSR_ADC_CHANNEL_MASK_L_REG 0x8B
215 #define ECGGSR_ADC_CHANNEL_MASK_H_REG 0x8C
216 #define ECGGSR_ADC_DATA_L_REG 0x8E
217 #define ECGGSR_ADC_DATA_H_REG 0x8F
218 #define ECGGSR_FIFO_CFG_REG 0x78
219 #define ECGGSR_FIFO_CNTRL_REG 0x79
220 #define ECGGSR_FIFOL_REG 0xFE
221 #define ECGGSR_FIFOH_REG 0xFF
222 #define ECGGSR_CONTROL_REG 0x00
223 #define ECGGSR_GPIO_A_REG 0x08
224 #define ECGGSR_GPIO_E_REG 0x09
225 #define ECGGSR_GPIO_O_REG 0x0A
226 #define ECGGSR_GPIO_I_REG 0x0B
227 #define ECGGSR_GPIO_P_REG 0x0C
228 #define ECGGSR_GPIO_SR_REG 0x0D
229 #define ECGGSR_SUBID_REG 0x91
230 #define ECGGSR_ID_REG 0x92
231 #define ECGGSR_STATUS_REG 0xA0
232 #define ECGGSR_STATUS2_REG 0xA1
233 #define ECGGSR_CLIPSTATUS_REG 0xA2
234 #define ECGGSR_LEDSTATUS_REG 0xA3
235 #define ECGGSR_FIFOSTATUS_REG 0xA4
236 #define ECGGSR_LTFSTATUS_REG 0xA5
237 #define ECGGSR_FIFOLEVEL_REG 0xA6
238 #define ECGGSR_INTENAB_REG 0xA8
239 #define ECGGSR_INTENAB2_REG 0xA9
240 #define ECGGSR_INTR_REG 0xAA
241 #define ECGGSR_INTR2_REG 0xAB
242 
243 #define ECGGSR_DEV_ID_MASK 0xFC
244 #define ECGGSR_DEV_ID 0x54
245 
246 
247 // 35mA current flows through LEDs.
248 #define ECGGSR_LED_CURR_LOW_2 0x80
249 #define ECGGSR_LED_CURR_HIGH_2 0x59
250 
251 
252 // 100mA current flows through LEDs.
253 #define ECGGSR_LED_CURR_LOW_3 0xC0
254 #define ECGGSR_LED_CURR_HIGH_3 0xFF
255 
256 // PPG related definitions.
257 #define ECGGSR_ENABLE_OSC_AND_LDO 0x03
258 #define ECGGSR_READ_VALUE_CONTROL_REG 0x83
259 #define ECGGSR_ENABLE_REF_AND_DIODES 0x8B
260 #define ECGGSR_ENABLE_LED12_OUTPUT 0x99
261 #define ECGGSR_ENABLE_LED4_OUTPUT 0x90
262 #define ECGGSR_CONF_PHOTODIODE 0x3E
263 #define ECGGSR_SUNLIGHT_COMPENSATION 0x5E
264 #define ECGGSR_FEEDBACK_RESISTOR 0xE2
265 #define ECGGSR_ENABLE_PHOTOAMPLIFIER 0xBC
266 #define ECGGSR_START_PPG 0xE1
267 #define ECGGSR_ENABLE_ADC 0x01
268 #define ECGGSR_START_ADC_CONVERSION 0x01
269 #define ECGGSR_ENABLE_OFE_AND_BIAS 0xE6
270 #define ECGGSR_OFE1_CFGA 0x70
271 #define ECGGSR_OFE2_CFGA 0x70
272 #define ECGGSR_ADC_DATA_H_MASK 0x3F
273 #define ECGGSR_PPG_SCALE_VAL 0x64
274 #define ECGGSR_PD_LED_CURRENT 0x80
275 #define ECGGSR_PPG_L_THRESHOLD 0x48
276 #define ECGGSR_PPG_H_THRESHOLD 0x5F
277 #define ECGGSR_PPG_MAX_VAL 0x64
278 
279 // ECG related definitions.
280 #define ECGGSR_ENABLE_SIG_REFERENCE 0x80
281 #define ECGGSR_ENABLE_BIAS_AND_GAIN 0x09
282 #define ECGGSR_INPUT_AND_REF_VOLTAGE 0xB0
283 #define ECGGSR_RESISTIVE_BIASING 0xA0
284 #define ECGGSR_GAIN_SETTINGS_STAGES1_2 0x0B
285 #define ECGGSR_ENABLE_ECG_AMPLIFIER 0x88
286 #define ECGGSR_GAIN_SETTINGS_STAGE3 0x04
287 #define ECGGSR_ENABLE_REF_AMPLIFIER 0x01
288 #define ECGGSR_START_SEQUENCER 0xE1
289 #define ECGGSR_SELECT_EFE 0x40
290 #define ECGGSR_SELECT_AMPLIFIER_INPUT 0x01
291 #define ECGGSR_ECG_SCALE_VAL 0x02
292 
293 // GSR related definitions.
294 #define ECGGSR_ENABLE_GPIO1_ANALOG 0x02
295 #define ECGGSR_SET_SLEW_RATE_GPIO1 0x02
296 #define ECGGSR_SET_GPIO1_AS_INPUT 0x46
297 #define ECGGSR_SET_RES_BIAS_GPIO1 0x40
298 
299  // generic_registers
301  // ecggsr
303 
304 // --------------------------------------------------------------- PUBLIC TYPES
305 
315 typedef enum
316 {
320 
323 
328 typedef struct
329 {
331  i2c_master_t i2c;
332 
334  uint8_t slave_address;
335 
337  pin_name_t enable_pin;
338 
339 } ecggsr_t;
340 
346 typedef struct
347 {
349  pin_name_t scl_pin;
350  pin_name_t sda_pin;
351  pin_name_t enable_pin;
352 
354  uint32_t i2c_speed;
355  uint8_t i2c_address;
356 
359 
360 } ecggsr_cfg_t;
361 
366 typedef enum
367 {
371  // End types group
373 // ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
374 
387 
395 err_t ecggsr_init( ecggsr_t *ctx, ecggsr_cfg_t* cfg );
396 
404 
413 err_t ecggsr_write_reg( ecggsr_t *ctx, uint8_t register_address, uint8_t transfer_data );
414 
424 err_t ecggsr_read_reg( ecggsr_t *ctx, uint8_t register_address, uint8_t *data_out, uint8_t num_of_regs );
425 
432 void ecggsr_read_dev_id( ecggsr_t *ctx, uint8_t *dev_id_out );
433 
439 void ecggsr_reset( ecggsr_t *ctx );
440  // End public_function group
442 
443 #ifdef __cplusplus
444 }
445 #endif
446 
447 #endif // _ECGGSR_H_
448 // ------------------------------------------------------------------------- END
ecggsr_reset
void ecggsr_reset(ecggsr_t *ctx)
ECG GSR Reset function.
ecggsr_default_cfg
void ecggsr_default_cfg(ecggsr_t *ctx, ecggsr_cfg_t *cfg)
Click Default Configuration function.
ecggsr_cfg_t::i2c_address
uint8_t i2c_address
Definition: ecggsr.h:355
ecggsr_t::i2c
i2c_master_t i2c
Definition: ecggsr.h:331
ENABLE_OXIMETER_FUNCTIONALITY
@ ENABLE_OXIMETER_FUNCTIONALITY
Definition: ecggsr.h:317
ENABLE_HEARTRATE_FUNCTIONALITY
@ ENABLE_HEARTRATE_FUNCTIONALITY
Definition: ecggsr.h:318
ecggsr_t
Context structure.
Definition: ecggsr.h:329
ecggsr_cfg_t::scl_pin
pin_name_t scl_pin
Definition: ecggsr.h:349
ecggsr_init_error
@ ecggsr_init_error
Definition: ecggsr.h:369
ecggsr_cfg_t::click_functionality
ecggsr_functionality_t click_functionality
Definition: ecggsr.h:358
ENABLE_GALVANIC_SKIN_RESPONSE_FUNCTIONALITY
@ ENABLE_GALVANIC_SKIN_RESPONSE_FUNCTIONALITY
Definition: ecggsr.h:319
DEFAULT_ECGGSR_CLICK_FUNCTIONALITY
@ DEFAULT_ECGGSR_CLICK_FUNCTIONALITY
Definition: ecggsr.h:321
ecggsr_functionality_t
ecggsr_functionality_t
ECG GSR type of measurement selector.
Definition: ecggsr.h:316
ecggsr_cfg_t::i2c_speed
uint32_t i2c_speed
Definition: ecggsr.h:354
ecggsr_cfg_t
Configuration structure.
Definition: ecggsr.h:347
ecggsr_t::enable_pin
pin_name_t enable_pin
Definition: ecggsr.h:337
ecggsr_write_reg
err_t ecggsr_write_reg(ecggsr_t *ctx, uint8_t register_address, uint8_t transfer_data)
Generic Write function.
ecggsr_cfg_setup
void ecggsr_cfg_setup(ecggsr_cfg_t *cfg)
ECG GSR configuration object setup function.
ecggsr_init
err_t ecggsr_init(ecggsr_t *ctx, ecggsr_cfg_t *cfg)
Initialization function.
ecggsr_err_t
ecggsr_err_t
Error Code.
Definition: ecggsr.h:367
ecggsr_cfg_t::enable_pin
pin_name_t enable_pin
Definition: ecggsr.h:351
ecggsr_read_reg
err_t ecggsr_read_reg(ecggsr_t *ctx, uint8_t register_address, uint8_t *data_out, uint8_t num_of_regs)
Generic Read function.
ecggsr_ok
@ ecggsr_ok
Definition: ecggsr.h:368
ecggsr_read_dev_id
void ecggsr_read_dev_id(ecggsr_t *ctx, uint8_t *dev_id_out)
ECG GSR Read ID function.
ecggsr_t::slave_address
uint8_t slave_address
Definition: ecggsr.h:334
ecggsr_cfg_t::sda_pin
pin_name_t sda_pin
Definition: ecggsr.h:350